AMD AM186EM User manual

Am186EM and Am188EM
Microcontrollers
User’s Manual

© 1997 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in
its products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of publication, but AMD makes no representations or warranties with
respect to the accuracy or completeness of the contents of this publication or the information contained herein, and reserves the right to make
changes at any time, without notice. AMD disclaims responsibility for any consequences resulting from the use of the information included in this
publication.
This publication neither states nor implies any representations or warranties of any kind, including but not limited to, any implied warranty of
merchantability or fitness for a particular purpose. AMD products are not authorized for use as critical components in life support devices or
systems without AMD’s written approval. AMD assumes no liability whatsoever for claims associated with the sale or use (including the use of
engineering samples) of AMD products except as provided in AMD’s Terms and Conditions of Sale for such products.
Trademarks
AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386 and Am486 are registered trademarks, and Am186, Am188, E86, AMD Facts-On-Demand,
and K86 are trademarks of Advanced Micro Devices, Inc.
FusionE86 is a service mark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

iii
IF YOU HAVE QUESTIONS, WE’RE HERE TO HELP YOU.
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a
customer training center. Expert technical assistance is available from the worldwide staff
ofAMDfieldapplicationengineersandfactorysupportstafftoanswer E86™familyhardware
and software development questions.
Hotline and World Wide Web Support
For answers to technical questions, AMD provides a toll-free number for direct access to
our corporate applications hotline. Also available is the AMD World Wide Web home page and
FTP site, which provides the latest E86 family product information, including technical information
and data on upcoming product releases.
Corporate Applications Hotline
[phone] toll-free for U.S. and Canada
44-(0) 1276-803-299 U.K. and Europe hotline
World Wide Web Home Page and FTP Site
To access the AMD home page, go to http://www.amd.com.
To download documents and software,ftp to ftp.amd.com and log on asanonymous using
your E-mail address as a password. Or via your web browser, go to ftp://ftp.amd.com.
Questions, requests, and input concerning AMD’s WWW pages can be sent via E-mail to
[email protected].
Documentation and Literature
Free E86 family information such as data books, user’s manuals, data sheets, application
notes, the FusionE86SM Partner Solutions Catalog, and other literature is available with a
simple phone call. Internationally, contact your local AMD sales office for complete E86
family literature.
Literature Ordering
800-222-9323 toll-free for U.S. and Canada
512-602-5651 direct dial worldwide
512-602-7639 fax
800-222-9323 AMD Facts-On-Demand™faxback service
toll-free for U.S. and Canada

iv

Table of Contents v
TABLE OF CONTENTS
PREFACE INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
PURPOSE OF THIS MANUAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
INTENDED AUDIENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
USER’S MANUAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
AMD DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xx
E86 Family xx
CHAPTER 1 FEATURES AND PERFORMANCE
1.1 KEY FEATURES AND BENEFITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.2 DISTINCTIVE CHARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-2
1.3 APPLICATION CONSIDERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.3.2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.3.3 Serial Communications Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
1.4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS . . . . . . . . . . .1-6
CHAPTER 2 PROGRAMMING
2.1 REGISTER SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.1 Processor Status Flags Register . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.2 MEMORY ORGANIZATION AND ADDRESS GENERATION . . . . . . . . .2-3
2.3 I/O SPACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.4 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
2.5 SEGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.6 DATA TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
2.7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
CHAPTER 3 SYSTEM OVERVIEW
3.1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
3.1.1 Pins That Are Used by Emulators . . . . . . . . . . . . . . . . . . . . . . .3-15
3.2 BUS OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-16
3.3 BUS INTERFACE UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.3.1 Nonmultiplexed Address Bus . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.3.2 Byte Write Enables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-19
3.3.3 Pseudo Static RAM (PSRAM) Support . . . . . . . . . . . . . . . . . . . .3-19
3.4 CLOCK AND POWER MANAGEMENT UNIT . . . . . . . . . . . . . . . . . . . .3-20
3.4.1 Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
3.4.2 Crystal-Driven Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . .3-20
3.4.3 External Source Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
3.4.4 System Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
3.4.5 Power-Save Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
CHAPTER 4 PERIPHERAL CONTROL BLOCK
4.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.1.1 Peripheral Control Block Relocation Register
(RELREG, Offset FEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
4.1.2 Reset Configuration Register (RESCON, Offset F6h). . . . . . . . . .4-5
4.1.3 Processor Release Level Register (PRL, Offset F4h). . . . . . . . . .4-6
4.1.4 Power-Save Control Register (PDCON, Offset F0h). . . . . . . . . . .4-7
4.2 INITIALIZATION AND PROCESSOR RESET . . . . . . . . . . . . . . . . . . . . .4-8

Table of Contents
vi
CHAPTER 5 CHIP SELECT UNIT
5.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
5.2 CHIP SELECT TIMING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.3 READY AND WAIT-STATE PROGRAMMING . . . . . . . . . . . . . . . . . . . . .5-2
5.4 CHIP SELECT OVERLAP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-2
5.5 CHIP SELECT REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-3
5.5.1 Upper Memory Chip Select Register (UMCS, Offset A0h) . . . . . .5-4
5.5.2 Low Memory Chip Select Register (LMCS, Offset A2h) . . . . . . . .5-6
5.5.3 Midrange Memory Chip Select Register (MMCS, Offset A6h) . . .5-8
5.5.4 PCS and MCS Auxiliary Register (MPCS, Offset A8h) . . . . . . . .5-10
5.5.5 Peripheral Chip Select Register (PACS, Offset A4h) . . . . . . . . .5-12
CHAPTER 6 REFRESH CONTROL UNIT
6.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
6.1.1 Memory Partition Register (MDRAM, Offset E0h) . . . . . . . . . . . .6-1
6.1.2 Clock Prescaler Register (CDRAM, Offset E2h) . . . . . . . . . . . . . .6-2
6.1.3 Enable RCU Register (EDRAM, Offset E4h) . . . . . . . . . . . . . . . .6-2
CHAPTER 7 INTERRUPT CONTROL UNIT
7.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.1.1 Definitions of Interrupt Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-1
7.1.2 Interrupt Conditions and Sequence. . . . . . . . . . . . . . . . . . . . . . . .7-4
7.1.3 Interrupt Priority. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-5
7.1.4 Software Exceptions, Traps, and NMI. . . . . . . . . . . . . . . . . . . . . .7-6
7.1.5 Interrupt Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-7
7.1.6 Interrupt Controller Reset Conditions . . . . . . . . . . . . . . . . . . . . . .7-8
7.2 MASTER MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.2.1 Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
7.2.2 Cascade Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-10
7.2.3 Special Fully Nested Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-11
7.2.4 Operation in a Polled Environment . . . . . . . . . . . . . . . . . . . . . . .7-11
7.2.5 End-of-Interrupt Write to the EOI Register . . . . . . . . . . . . . . . . .7-11
7.3 MASTER MODE INTERRUPT CONTROLLER REGISTERS . . . . . . . .7-12
7.3.1 INT0 and INT1 Control Registers
(I0CON, Offset 38h, I1CON, Offset 3Ah) (Master Mode) . . . . . .7-13
7.3.2 INT2 and INT3 Control Registers
(I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode) . . . . . .7-15
7.3.3 INT4 Control Register (I4CON, Offset 40h) (Master Mode) . . . .7-16
7.3.4 Timer and DMA Interrupt Control Registers
(TCUCON, Offset 32h, DMA0CON, Offset 34h, DMA1CON,
Offset 36h) (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
7.3.5 Watchdog Timer Interrupt Control Register (WDCON,
Offset 42h) (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
7.3.6 Serial Port Interrupt Control Register (SPICON, Offset 44h)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
7.3.7 Interrupt Status Register (INTSTS, Offset 30h)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
7.3.8 Interrupt Request Register (REQST, Offset 2Eh)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-21
7.3.9 In-Service Register (INSERV, Offset 2Ch)
(Master Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
7.3.10 Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode). . .7-23
7.3.11 Interrupt Mask Register (IMASK, Offset 28h) (Master Mode) . . .7-24
7.3.12 Poll Status Register (POLLST, Offset 26h) (Master Mode). . . . .7-25
7.3.13 Poll Register (POLL, Offset 24h) (Master Mode). . . . . . . . . . . . .7-26
7.3.14 End-of-Interrupt Register (EOI, Offset 22h) (Master Mode) . . . .7-27
7.4 SLAVE MODE OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28

Table of Contents vii
7.4.1 Slave Mode Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . .7-28
7.4.2 Slave Mode Interrupt Controller Registers . . . . . . . . . . . . . . . . .7-28
7.4.3 Timer and DMA Interrupt Control Registers
(T0INTCON, Offset 32h, T1INTCON, Offset 38h, T2INTCON, Offset
3Ah, DMA0CON, Offset 34h, DMA1CON, Offset 36h)
(Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-29
7.4.4 Interrupt Status Register (INTSTS, Offset 30h) (Slave Mode) . .7-30
7.4.5 Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode).7-31
7.4.6 In-Service Register (INSERV, Offset 2Ch) (Slave Mode) . . . . . .7-32
7.4.7 Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode). . . .7-33
7.4.8 Interrupt Mask Register (IMASK, Offset 28h) (Slave Mode) . . . .7-34
7.4.9 Specific End-of-Interrupt Register (EOI, Offset 22h)
(Slave Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35
7.4.10 Interrupt Vector Register (INTVEC, Offset 20h) (Slave Mode) . .7-36
CHAPTER 8 TIMER CONTROL UNIT
8.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1
8.2.1 Timer Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
8.2.2 Timer 0 and Timer 1 Mode and Control Registers
(T0CON, Offset 56h, T1CON, Offset 5Eh) . . . . . . . . . . . . . . . . . .8-3
8.2.3 Timer 2 Mode and Control Register (T2CON, Offset 66h) . . . . . .8-5
8.2.4 Timer Count Registers
(T0CNT, Offset 50h, T1CNT, Offset 58h, T2CNT, Offset 60h) . . .8-6
8.2.5 Timer Maxcount Compare Registers
(T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah,
T1CMPB, Offset 5Ch, T2CMPA, Offset 62h) . . . . . . . . . . . . . . . .8-7
CHAPTER 9 DMA CONTROLLER
9.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.2 DMA OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
9.3 PROGRAMMABLE DMA REGISTERS. . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
9.3.1 DMA Control Registers (D0CON, Offset CAh, D1CON,
Offset DAh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
9.3.2 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC,
Offset D8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-5
9.3.3 DMA Destination Address High Register
(High Order Bits) (D0DSTH, Offset C6h, D1DSTH, Offset D6h). .9-6
9.3.4 DMA Destination Address Low Register (Low Order Bits)
(D0DSTL, Offset C4h, D1DSTL, Offset D4h) . . . . . . . . . . . . . . . .9-7
9.3.5 DMA Source Address High Register (High Order Bits)
(D0SRCH, Offset C2h, D1SRCH, Offset D2h) . . . . . . . . . . . . . . .9-8
9.3.6 DMA Source Address Low Register (Low Order Bits)
(D0SRCL, Offset C0h, D1SRCL, Offset D0h) . . . . . . . . . . . . . . . .9-9
9.4 DMA REQUESTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
9.4.1 Synchronization Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
9.4.2 DMA Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.3 DMA Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.4 DMA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
9.4.5 DMA Channels on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
CHAPTER 10 ASYNCHRONOUS SERIAL PORT
10.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-1
10.2.1 Serial Port Control Register (SPCT, Offset 80h). . . . . . . . . . . . .10-2
10.2.2 Serial Port Status Register (SPSTS, Offset 82h) . . . . . . . . . . . .10-4
10.2.3 Serial Port Transmit Data Register (SPTD, Offset 84h) . . . . . . .10-5
10.2.4 Serial Port Receive Data Register (SPRD, Offset 86h). . . . . . . .10-6
10.2.5 Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88h). .10-7

Table of Contents
viii
CHAPTER 11 SYNCHRONOUS SERIAL INTERFACE
11.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
11.1.1 Four-Pin Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
11.2 PROGRAMMABLE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
11.2.1 Synchronous Serial Status Register (SSS, Offset 10h). . . . . . . .11-3
11.2.2 Synchronous Serial Control Register (SSC, Offset 12h). . . . . . .11-4
11.2.3 Synchronous Serial Transmit 1 Register (SSD1, Offset 14h)
Synchronous Serial Transmit 0 Register (SSD0, Offset 16h) . . .11-5
11.2.4 Synchronous Serial Receive Register (SSR, Offset 18h) . . . . . .11-6
11.3 SSI PROGRAMMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-7
CHAPTER 12 PROGRAMMABLE I/O PINS
12.1 OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-1
12.2 PIO MODE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-3
12.2.1 PIO Mode 1 Register (PIOMODE1, Offset 76h) . . . . . . . . . . . . .12-3
12.2.2 PIO Mode 0 Register (PIOMODE0, Offset 70h) . . . . . . . . . . . . .12-3
12.3 PIO DIRECTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-4
12.3.1 PIO Direction 1 Register (PDIR1, Offset 78h) . . . . . . . . . . . . . .12-4
12.3.2 PIO Direction 0 Register (PDIR0, Offset 72h) . . . . . . . . . . . . . .12-4
12.4 PIO DATA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
12.4.1 PIO Data Register 1 (PDATA1, Offset 7Ah) . . . . . . . . . . . . . . . .12-5
12.4.2 PIO Data Register 0 (PDATA0, Offset 74h) . . . . . . . . . . . . . . . .12-5
12.5 OPEN-DRAIN OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12-5
APPENDIX A REGISTER SUMMARY

Table of Contents ix
LIST OF FIGURES
Figure 1-1 Am186ES Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-4
Figure 1-2 Am188ES Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
Figure 1-3 Basic Functional System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-6
Figure 2-1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Figure 2-2 Processor Status Flags Register (F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
Figure 2-3 Physical Address Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
Figure 2-4 Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-4
Figure 2-5 Supported Data Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-9
Figure 3-1 Am186ES Microcontroller Address Bus—Normal Read and Write Operation.3-21
Figure 3-2 Am186ES Microcontroller—Read and Write with Address Bus
Disable In Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-21
Figure 3-3 Am188ES Microcontroller Address Bus—Normal Read
and Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
Figure 3-4 Am188ES Microcontroller—Read and Write with Address
Bus Disable In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-22
Figure 3-5 Oscillator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-26
Figure 3-6 Clock Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-27
Figure 4-1 Peripheral Control Block Relocation Register . . . . . . . . . . . . . . . . . . . . . . . . . .4-3
Figure 4-2 Reset Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-4
Figure 4-3 Processor Release Level Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Figure 4-4 Auxiliary Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-6
Figure 4-5 System Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-7
Figure 5-1 Upper Memory Chip Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
Figure 5-2 Low Memory Chip Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
Figure 5-3 Midrange Memory Chip Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-8
Figure 5-4 PCS and MCS Auxiliary Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
Figure 5-5 Peripheral Chip Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-12
Figure 6-1 Memory Partition Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-1
Figure 6-2 Clock Prescaler Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Figure 6-3 Enable RCU Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
Figure 6-4 Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-3
Figure 7-1 External Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . .7-8
Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections . . . . . . . . . . . . .7-10
Figure 7-3 Cascade Mode Interrupt Controller Connections. . . . . . . . . . . . . . . . . . . . . . .7-11
Figure 7-4 INT0 and INT1 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-14
Figure 7-5 INT2 and INT3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-15
Figure 7-6 INT4 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-16
Figure 7-7 Timer/DMA Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-17
Figure 7-8 Serial Port 0/1 Interrupt Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Figure 7-9 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-19
Figure 7-10 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-20
Figure 7-11 Interrupt In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-22
Figure 7-12 Priority Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23
Figure 7-13 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-24
Figure 7-14 Poll Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-25
Figure 7-15 Poll Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-26
Figure 7-16 Example EOI Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27
Figure 7-17 End-of-Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-27
Figure 7-18 Timer and DMA Interrupt Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .7-29
Figure 7-19 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-30
Figure 7-20 Interrupt Request Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-31
Figure 7-21 Interrupt In-Service Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-32
Figure 7-22 Priority Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33
Figure 7-23 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-34
Figure 7-24 Specific End-of-Interrupt Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-35
Figure 7-25 Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-36
Figure 8-1 Typical Waveform Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-1

Table of Contents
x
Figure 8-1 Timer 0 and Timer 1 Mode and Control Registers. . . . . . . . . . . . . . . . . . . . . . .8-3
Figure 8-2 Timer 2 Mode and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-5
Figure 8-3 Timer Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-6
Figure 8-4 Timer Maxcount Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-7
Figure 9-1 DMA Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-2
Figure 9-2 DMA Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-3
Figure 9-3 DMA Transfer Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-6
Figure 9-4 DMA Destination Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-7
Figure 9-5 DMA Destination Address Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-8
Figure 9-6 DMA Source Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-9
Figure 9-7 DMA Source Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-10
Figure 9-8 Source-Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-12
Figure 9-9 Destination Synchronized DMA Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-13
Figure 10-10 DCE/DTE Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
Figure 10-11 CTS/RTR Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3
Figure 10-1 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
Figure 10-2 Serial Port 0/1 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-9
Figure 10-3 Serial Port 0/1 Transmit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-11
Figure 10-4 Serial Port Receive 0/1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-12
Figure 10-5 Serial Port 0/1 Baud Rate Divisor Registers . . . . . . . . . . . . . . . . . . . . . . . . .10-14
Figure 11-1 Programmable I/O Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-1
Figure 11-3 PIO Mode 0 Register (PIOMODE0, offset 70h) . . . . . . . . . . . . . . . . . . . . . . . .11-3
Figure 11-2 PIO Mode 1 Register (PIOMODE1, offset 76h) . . . . . . . . . . . . . . . . . . . . . . . .11-3
Figure 11-4 PIO Direction 1 Register (PDIR1, offset 78h) . . . . . . . . . . . . . . . . . . . . . . . . .11-4
Figure 11-5 PIO Direction 0 Register (PDIR0, offset 72h) . . . . . . . . . . . . . . . . . . . . . . . . .11-4
Figure 11-6 PIO Data 1 Register (PDATA1, offset 7Ah) . . . . . . . . . . . . . . . . . . . . . . . . . .11-5
Figure 11-7 PIO Data 0 Register (PDATA0, offset 74h). . . . . . . . . . . . . . . . . . . . . . . . . . .11-5
Figure A-1 Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-4

Table of Contents xi
LIST OF TABLES
Table 2-1 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
Table 2-2 Segment Register Selection Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-8
Table 2-3 Memory Addressing Mode Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
Table 3-1 Numeric PIO Pin Designations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-13
Table 3-2 Alphabetic PIO Pin Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-14
Table 3-3 Programming Am186ES Microcontroller Bus Width . . . . . . . . . . . . . . . . . . . .3-24
Table 4-1 Peripheral Control Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-2
Table 4-2 Processor Release Level (PRL) Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-5
Table 4-3 Initial Register State After Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-9
Table 5-1 Chip Select Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
Table 5-2 UMCS Block Size Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-4
Table 5-3 LMCS Block Size Programming Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6
Table 5-4 MCS Block Size Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-10
Table 5-5 PCS Address Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
Table 5-6 PCS3–PCS0 Wait-State Encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-13
Table 6-7 Watchdog Timer COUNT Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
Table 6-8 Watchdog Timer Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6-4
Table 7-1 Am186ES and Am188ES Microcontroller Interrupt Types. . . . . . . . . . . . . . . . .7-4
Table 7-2 Interrupt Controller Registers in Master Mode . . . . . . . . . . . . . . . . . . . . . . . . .7-13
Table 7-3 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-18
Table 7-4 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-23
Table 7-5 Interrupt Controller Registers in Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . .7-28
Table 7-6 Priority Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-33
Table 8-1 Timer Control Unit Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
Table 9-1 DMA Controller Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-1
Table 9-2 Synchronization Type. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-4
Table 9-3 Maximum DMA Transfer Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9-11
Table 10-4 Serial Port External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-2
Table 10-1 Asynchronous Serial Port Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .10-4
Table 10-2 DMA Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-5
Table 10-3 Serial Port MODE Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-7
Table 10-4 Common Baud Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10-13
Table 11-1 PIO Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-2
Table 11-2 PIO Mode and PIO Direction Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-3
Table A-1 Internal Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .A-1

Table of Contents
xii

Introduction and Overview xiii
PREFACE
INTRODUCTION AND OVERVIEW
DESIGN PHILOSOPHY
AMD’s Am186 and Am188 family of microcontrollers is based on the architecture of the
original 8086 and 8088 microcontrollers, and currently includes the 80C186, 80C188,
80L186, 80L188, Am186™EM, Am188™EM, Am186EMLV, Am188EMLV, Am186ES,
Am188ES, Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers. The
Am186EM and Am188EM microcontrollers provide a natural migration path for 80C186/
188 designs that need performance and cost enhancements.
The Am186EM and Am188EM microcontrollers provide alow-cost,high-performance solution
for embedded system designers who want to use the x86 architecture. By integrating multiple
functional blocks with the CPU, the Am186EM and Am188EM microcontrollers eliminate the
need for off-chip system-interface logic. It is possible to implement a fully functional system with
ROM and RAM, serial interfaces, and custom I/O capability without additional system-interface
logic.
The Am186EM and Am188EM microcontrollers can operate at frequencies up to 40 MHz.
The microcontrollers include an on-board PLL so that the input clock can be one-to-one
with the internal processor clock. The Am186EM and Am188EM microcontrollers are
available in versions operating at 20, 25, 33, and 40 MHz.
PURPOSE OF THIS MANUAL
This manual describes the technical features and programming interface of the Am186EM
andAm188EM microcontrollers.Thecompleteinstructionsetisdocumentedin the
Am186
and Am188 Family Instruction Set Manual,
order #21267.
INTENDED AUDIENCE
This manual is intended for computer hardware and software engineers and system
architectswhoaredesigningorareconsideringdesigningsystemsbasedontheAm186EM
and Am188EM microcontrollers.
USER’S MANUAL OVERVIEW
This manual contains information on the Am186EM and Am188EM microcontrollers and
is essential for system architects and design engineers. Additional information is available
in the form ofdata sheets, application notes,and otherdocumentation that isprovided with
software products and hardware-development tools.
The information in this manual is organized into 12 chapters and 1 appendix.
nChapter 1 introduces the features and performance aspects of the Am186EM and
Am188EM microcontrollers.
nChapter 2 describes the programmer’s model of the Am186 and Am188 family
microcontrollers, including an instruction set overview and register model.
nChapter 3 provides an overview of the system interfaces, along with clocking
features.

Introduction and Overview
xiv
nChapter 4 provides a description of the peripheral control block along with power
management and reset configuration.
nChapter 5 provides a description of the chip select unit.
nChapter 6 provides a description of the refresh control unit.
nChapter 7 provides a description of the on-chip interrupt controller.
nChapter 8 describes the timer control unit.
nChapter 9 describes the DMA controller.
nChapter 10 describes the asynchronous serial port.
nChapter 11 describes the synchronous serial interface.
nChapter 12 describes the programmable I/O pins.
nAppendix A includes a complete summary of peripheral registers and fields.
Forcompleteinformationonthe Am186EM andAm188EMmicrocontrollerpinlists,timing,
thermalcharacteristics,andphysicaldimensions,pleaserefertothe
Am186EM/EMLVand
Am188EM/EMLV Microcontrollers Data Sheet
(order# 19168).
AMD DOCUMENTATION
E86 Family
ORDER NO. DOCUMENT TITLE
19168 Am186EM/EMLV and Am188EM/EMLV Microcontrollers Data Sheet
Hardware documentation: pin descriptions, functional descriptions, absolute
maximum ratings, operating ranges, switching characteristics and waveforms,
connection diagrams and pinouts, and package physical dimensions.
21267 Am186 and Am188 Family Instruction Set Manual
Providesadetaileddescriptionandexamplesforeachinstructionincludedinthe
Am186 and Am188 Family Instruction Set.
19255 FusionE86SM Catalog
Provides information on tools that speed an E86 family embedded product to
market. Includes products from expert suppliers of embedded development so-
lutions.
20071 E86 Family Support Tools Brief
ListsavailableE86 familysoftwareandhardwaredevelopmenttools,as wellas
contact information for suppliers.
21058 FusionE86 Development Tools Reference CD
Provides a single-source multimedia tool for customer evaluation of AMD prod-
ucts,aswellasFusionpartnertoolsandtechnologiesthatsupporttheE86family
of microcontrollers and microprocessors. Technicaldocumentation for the E86
family is included on the CD in PDF format.
To order literature, contact the nearest AMD sales office or call 800-222-9323 (in the U.S.
and Canada) or direct dial from any location 512-602-5651.
Literature is also available in postscript and PDF formats on the AMD web site. To access the
AMD home page, go to http://www.amd.com. To download documents and software, ftp to
ftp.amd.com and log on as anonymous using your E-mail address as a password. Or via
your web browser, go to ftp://ftp.amd.com.

Features and Performance 1-1
CHAPTER
1FEATURES AND PERFORMANCE
Compared to the 80C186/188 microcontrollers, the Am186™EM and Am188™EM
microcontrollers enable designers to increase performance and functionality, while
reducing the cost, size, and power consumption of embedded systems. The Am186EM
andAm188EMmicrocontrollersarecost-effective,enhancedversionsoftheAMD80C186/
188 devices.
The Am186EM and Am188EM microcontrollers are the ideal upgrade for 80C186/188
designs requiring 80C186/188-compatibility, increased performance, serial
communications, and a glueless bus interface. Developed exclusively for the embedded
marketplace, the Am186EM and Am188EM microcontrollers increase the performance of
existing 80C186/188 systems while decreasing their cost.
Because the Am186EM and Am188EM microcontrollers integrate on-chip peripherals and
offer up to twice the performance of an 80C186/188, they are ideal upgrade solutions for
customers requiring more integration and performance than their present x86 solution
delivers.
1.1 KEY FEATURES AND BENEFITS
The Am186EM and Am188EM microcontrollers extend the AMD family of microcontrollers
based on the industry-standard x86 architecture. The Am186EM and Am188EM
microcontrollers deliver higher performance and more integration than the 80C186/188
core microcontrollers. Upgrading to the Am186EM or Am188EM microcontrollers is
attractive for the following reasons:
nMinimized total system cost—The new peripherals and on-chip system-interface logic
reduce the cost of existing 80C186 designs.
nx86softwarecompatibility—80C186/188-compatibleandupward-compatiblewiththe
AMD E86 family.
nEnhancedperformance—TheAm186EMandAm188EMmicrocontrollerscanprovide
increasedperformanceover80C186/188systems,andthenonmultiplexedaddressbus
offers faster, unbuffered access to memory.
nNo wait-state operation—At 40 MHz with 70-ns memories.
nEnhancedfunctionality—Thenewandenhancedon-chipperipheralsoftheAm186EM
and Am188EM microcontrollers include an asynchronous serial port, a watchdog timer
interrupt,anadditionalinterruptpin,ahigh-speedsynchronousserialinterface,aPSRAM
controller, a 16-bit Reset Configuration register, enhanced chip-select functionality, 32
programmable I/Os, and additional interrupt signals.
The Am186EM and Am188EM microcontrollers are part of the AMD E86 family of embedded
microcontrollersandmicroprocessorsbasedonthex86architecture.The16-bitmembersofthe
E86 family, referred to throughout this manual as the Am186 and Am188 family, include the
80C186, 80C188, 80L186, 80L188, Am186EMLV, Am188EMLV, Am186ES, Am188ES,
Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers.

Features and Performance
1-2
The Am186EM and Am188EM microcontrollers are designed to meet the most common
requirements of embedded products developed for the office automation, mass storage,
communications, and general embedded markets. Applications include disk drives, hand-
held terminals, fax machines, terminals, printers, photocopiers, feature phones, cellular
phones, PBXs, multiplexers, modems, and industrial controls.
1.2 DISTINCTIVE CHARACTERISTICS
A block diagram of each microcontroller is shown in Figure 1-1 and Figure 1-2. The
Am186EM microcontroller uses a 16-bit external bus, while the Am188EM microcontroller
has an 8-bit external bus.
The Am186EM and Am188EM microcontrollers provide the following features:
nHigh performance:
— 20-, 25-, 33-, and 40-MHz operating frequencies
— Support for zero wait-state operation at 40 MHz with 70-ns memory
— 1-Mbyte memory address space and 64-Kbyte I/O space
nNew features remove the requirement for a 2x clock input and provide faster access to
memory:
— Phase-locked loop (PLL) allows processor to operate at the clock input frequency
— Nonmultiplexed address bus
nNew integrated peripherals increase functionality while reducing system cost:
— 32 programmable I/O (PIO) pins
— Asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers
— Pseudo-static RAM (PSRAM) controller includes auto refresh capability
— Reset Configuration register
— Synchronous serial interface allows high-speed, half-duplex, bidirectional data
transfer to and from application-specific integrated circuits (ASICs)
— Additional external interrupts
nFamiliar 80C186 peripherals:
— Two independent DMA channels
— Programmable interrupt controller with five external interrupts
— Three programmable 16-bit timers
— Timer 1 can be configured to provide a watchdog timer interrupt
— Programmable memory and peripheral chip-select logic
— Programmable wait-state generator
— Power-save mode
nSoftware-compatible with the 80C186/188 microcontroller
nWidely available native development tools, applications, and system software
nAvailable in the following packages:
— 100-pin, thin quad flat pack (TQFP)
— 100-pin, plastic quad flat pack (PQFP)

Features and Performance 1-3
Figure 1-1 Am186EM Microcontroller Block Diagram
Note:
* All PIO signals are shared with otherphysical pins. See the pin descriptions in Chapter 3and Table
3-1 on page 3-9 for information on shared functions.
S2–S0
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
Execution
Unit Chip-Select
Unit
Clock and
Power
Management
Unit
Control
Registers
16-Bit Count
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
20-Bit Source
Pointers
Control
Registers
Control
Registers
Control
Registers
01(WDT)2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control Registers Control
Registers
CLKOUTB
CLKOUTA INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0 DRQ1
VCC
GND
TMRIN0 TMRIN1
ARDY
SRDY
DT/R
DEN
HOLD
HLDA
Asynchronous
Serial Port
Synchronous Serial
Interface
TXD
RXD
SCLK SDATA
SDEN0 SDEN1
NMI
A19–A0
AD15–AD0
ALE
BHE/ADEN
WR
WLB
WHB
RD
RES
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0
PCS5/A1
UCS/ONCE1
X2
X1
Control
Registers
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
Control
Registers
S6/
UZI
CLKDIV2

Features and Performance
1-4
Figure 1-2 Am188EM Microcontroller Block Diagram
Note:
* All PIO signals are shared with otherphysical pins. See the pin descriptions in Chapter 3and Table
3-1 on page 3-9 for information on shared functions.
S2–S0
Interrupt
Control Unit
Timer Control
Unit DMA
Unit
Bus
Interface
Unit
Execution
Unit Chip-Select
Unit
Clock and
Power
Management
Unit
Control
Registers
16-Bit Count
Registers
Max Count A
Registers 16-Bit Count
Registers
20-Bit Destination
Pointers
20-Bit Source
Pointers
Control
Registers
Control
Registers
Control
Registers
01(WDT)2 0 1
Max Count B
Registers
Refresh
Control
Unit
Control
Registers Control Registers Control
Registers
CLKOUTB
CLKOUTA INT4
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
INT0 TMROUT0 TMROUT1
DRQ0 DRQ1
VCC
GND
TMRIN0 TMRIN1
ARDY
SRDY
DT/R
DEN
HOLD
HLDA
Asynchronous
Serial Port
Synchronous Serial
Interface
TXD
RXD
SCLK SDATA
SDEN0 SDEN1
NMI
S6/
A19–A0
AD7–AD0
ALE
WR
WB
RD
RES
LCS/ONCE0
MCS2–MCS0
PCS6/A2
PCS3–PCS0
PCS5/A1
UCS/ONCE1
X2
X1
UZI
Control
Registers
PSRAM
Control
Unit
MCS3/RFSH
PIO
Unit PIO31–
PIO0*
Control
Registers
AO15–AO8
RFSH2/ADEN
CLKDIV2

Features and Performance 1-5
1.3 APPLICATION CONSIDERATIONS
The integration enhancements of the Am186EM and Am188EM microcontrollers provide
ahigh-performance,low-system-costsolutionfor16-bitembeddedmicrocontrollerdesigns.
The nonmultiplexed address bus (A19–A0) eliminates system-interface logic for memory
devices, while the multiplexed address/data bus maintains the value of existing customer-
specific peripherals and circuits within the upgraded design.
The nonmultiplexed address bus is available in addition to the 80C186 and 80C188
microcontrollers’ multiplexed address/data bus (AD15–AD0). The two buses can operate
simultaneously or the AD15–AD0 bus can be configured to operate only during the data
phase of a bus cycle. See the BHE/ADEN andRFSH2/ADEN pin descriptions in Chapter 3,
and see section 5.5.1 and section 5.5.2 for additional information regarding the AD15–AD0
address enabling and disabling.
Figure 1-3 illustrates a functional system design that uses the integrated peripheral set to
achieve high performance with reduced system cost.
Figure 1-3 Basic Functional System Design
1.3.1 Clock Generation
The integrated PLL clock-generation circuitry of the Am186EM and Am188EM
microcontrollers allows the use of a
times-one crystal frequency. The design in Figure 1-3
achieves 40-MHz CPU operation with a 40-MHz crystal.
The integrated PLL lowers system cost by reducing the cost of the crystal and reduces
electromechanical interference (EMI) in the system.
X2
X1
RS-232 Level
Converter
TXD
RXD
LCS
UCS
WHB
WLB
WE
Address
Data
OE
CS
WE
RD
WE
Address
Data
OE
CS
WE
AD15–AD0
A19–A0
Flash PROM
Static RAM
Serial Port
Am186EM
Microcontroller
40-MHz
Crystal

Features and Performance
1-6
1.3.2 Memory Interface
The integrated memory controller logic of the Am186EM and Am188EM microcontrollers
providesadirectaddressbusinterfaceto memorydevices.The useofanexternaladdress
latch controlled by the address latch enable (ALE) signal is not required.
Individual byte write-enable signals are provided to eliminate the need for external high/
low-byte, write-enable circuitry. The maximum bank size programmable for the memory
chip-select signals is increased to 512 Kbytes to facilitate the use of high-density memory
devices.
Improved memory timing specifications enables the use of no-wait-state memories with
70-ns access times at 40-MHz CPU operation. This reduces overall system cost
significantly by allowing the use of commonly available memory devices.
Figure 1-3 illustrates an Am186EM microcontroller-based SRAM configuration. The
memory interface requires the following:
nThe processor A19–A0 bus connects to the memory address inputs.
nThe AD bus connects directly to the data inputs/outputs.
nThe chip selects connect to the memory chip-select inputs.
Read operations require that the RDoutput connects to the SRAM Output Enable (OE) input
pins. Write operations require that the byte write enables connect to the SRAM Write Enable
(WE) input pins.
The design uses 2-Mbit (256-Kbyte) memory technology to fully populate the available
address space. Two Flash PROM devices provide 512 Kbytes of nonvolatile program
storage, and two static RAM devices provide 512 Kbytes of variable storage area.
1.3.3 Serial Communications Port
The integrated universal asynchronous receiver/transmitter (UART) controller in the
Am186EM and Am188EM microcontrollers eliminates the need for external logic to
implement a communications interface. The integrated UART generates the serial clock
from the CPU clock so that no external time-base oscillator is required.
Figure 1-3 shows a minimal implementation of an RS-232 console or modem
communications port. The RS-232 to CMOS voltage-level converter is required for the
proper electrical interface with the external device.
TheAm186EMandAm188EMmicrocontrollersalsoincludeasynchronousserialinterface.
For more information, see Chapter 11.
1.4 THIRD-PARTY DEVELOPMENT SUPPORT PRODUCTS
The FusionE86 Program of Partnerships for Application Solutions provides the customer with
an array of products designed to meet critical time-to-market needs. Products and solutions
available from the AMD FusionE86 partners include emulators, hardware and software
debuggers, board-level products, and software development tools, among others.
In addition, mature development tools and applications for the x86 platform are widely
available in the general marketplace.