Analog Devices AD9361 User manual

AD9361 Reference Manual
UG-570
One Technology Way •P. O . Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
AD9361 Reference Manual
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.| Page 1 of 128
GENERAL INFORMATION
Complete specifications for the AD9361 part can be found in the AD9361 data sheet, which is available from Analog Devices, Inc., and
should be consulted in conjunction with this user guide when using the evaluation board.
Additional information about the AD9361 registers can be found in the AD9361 Register Map Reference Manual. While the register map
is provided as a convince and informational for those who want to understand the low level operation of the part, it is not recommended
to attempt to create your own software. Analog Devices provides complete drivers for the AD9361 for both bare metal/No-OS and
operating systems (Linux). The AD9361 and AD9364 share the same API. The AD9361 and AD9364 drivers can be found at:
•Linux wiki page
•No-OS wiki page
Support for these drivers can be found at:
•Linux engineer zone page
•No-OS engineer zone page
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TABLE OF CONTENTS
General Information ........................................................................ 1
Revision History ............................................................................... 4
Introduction ...................................................................................... 5
Terminology.................................................................................. 5
Register and Bit Syntax ................................................................ 5
Initialization and Calibration.......................................................... 6
Overview........................................................................................ 6
Initalization Calibrations............................................................. 7
BBPLL VCO Calibration ............................................................. 8
RF Synthesizer Charge Pump Calibration ................................ 8
RF Synthesizer VCO Calibration ............................................... 8
Baseband Rx Analog Filter Calibration..................................... 9
Baseband Tx Analog Filter Calibration................................... 10
Baseband Tx Secondary Filter .................................................. 11
Rx TIA Calibration Equations .................................................. 11
Rx ADC Setup............................................................................. 11
Baseband DC Offset Calibration.............................................. 11
Baseband DC Offset Tracking .................................................. 11
RF DC Offset Calibration.......................................................... 12
Rx Quadrature Tracking Calibration....................................... 13
Tx Quadrature Calibration ....................................................... 13
Reference Clock Requirements..................................................... 14
Overview...................................................................................... 14
DCXO Setup and Operation..................................................... 14
Reference Clock Setup and Operation .................................... 15
Phase Noise Specification.......................................................... 15
RF and BBPLL Synthesizer............................................................ 16
Overview...................................................................................... 16
RFPLL Introduction................................................................... 16
AD9361 PLL Architecture......................................................... 16
Reference Block .......................................................................... 16
Main PLL Block .......................................................................... 17
Charge Pump Current ............................................................... 18
RFPLL Loop Filter...................................................................... 18
VCO Configuration ................................................................... 18
VCO Calibration......................................................................... 18
VCO Vtune Measurement......................................................... 18
Lock Detector.............................................................................. 18
Synthesizer Look Up Table........................................................ 19
TDD Mode Faster Lock Times ................................................. 19
External LO ................................................................................. 19
Baseband PLL (BBPLL) ............................................................. 19
BBPLL VCO................................................................................ 20
BBPLL Charge Pump................................................................. 21
BBPLL Loop Filter...................................................................... 21
Fast Lock Profiles............................................................................ 22
Overview ..................................................................................... 22
Fast Lock Initial Wider BW Option......................................... 22
Configuring and Using a Fast Lock Profile............................. 23
Fast Lock Pin Select ................................................................... 24
Enable State Machine Guide ......................................................... 25
Overview ..................................................................................... 25
ENSM State Definitions............................................................. 25
Modes of Operation ................................................................... 26
Sleep State.................................................................................... 30
Filter Guide...................................................................................... 31
Overview ..................................................................................... 31
Tx Signal Path ............................................................................. 31
Tx Digital Filter Blocks.............................................................. 31
Tx Analog Filter Blocks ............................................................. 32
Rx Signal Path ............................................................................. 33
Rx Analog Filter Blocks ............................................................. 33
Rx Digital Filter Blocks.............................................................. 33
Digital Rx Block Delay............................................................... 34
Gain Control ................................................................................... 35
Overview ..................................................................................... 35
Gain Control Threshold Detectors .......................................... 36
LMT Overload Detector............................................................ 36
ADC Overload Detector ........................................................... 36
Low Power Threshold................................................................ 36
Average Signal Power................................................................. 36
Settling Times ............................................................................. 37
Peak Overload Wait Time ......................................................... 37
Settling Delay.............................................................................. 37
Gain Table Overview ................................................................. 37
Full Table Mode .......................................................................... 37
Split Table Mode ......................................................................... 38
Digital Gain................................................................................. 38
MGC Overview .......................................................................... 38
Slow Attack AGC Mode ............................................................ 40
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Slow Attack AGC Gain Update Time.......................................40
Overloads in Slow Attack AGC Mode......................................41
Slow Attack AGC and Gain Tables ...........................................41
Hybrid AGC Mode .....................................................................42
Fast Attack AGC Mode...............................................................42
State 0: RESET .............................................................................43
State 1: Peak Overload Detect ...................................................43
State 2: Measure Power and Lock Level Gain Change ...........44
State 3: Measure Power and Peak Overload Detect................44
State 4: Unlock Gain ...................................................................44
State 5: Gain Lock and Measure Power....................................45
Custom Gain Tables ........................................................................47
Overview ......................................................................................47
RF DC Cal Bit..............................................................................49
Maximum Full Table/LMT Table Index...................................49
External LNA...............................................................................49
Received Signal Strength Indicator (RSSI) ..................................50
Overview ......................................................................................50
Mode Select and Measurement Duration................................50
RSSI Weighting............................................................................50
RSSI Delay and RSSI Wait..........................................................50
RSSI Preamble and RSSI Symbol ..............................................51
RSSI RFIR.....................................................................................51
RSSI Gain Step Calibration........................................................51
Transmit Power Control.................................................................55
Overview ......................................................................................55
Tx Attenuation Words................................................................55
Attenuation Word Update Options ..........................................55
Tx Power Monitor ...........................................................................56
Overview ......................................................................................56
Tx Power Monitor Description .................................................56
Input Matching/Attenuation Network .....................................57
Tx Power Monitor Gain Control...............................................58
TPM Dynamic Range.................................................................59
Example of Tx Mon Configuration and Measurement of TPM
Transfer Function........................................................................59
TPM Test Mode...........................................................................60
RF Port Interface .............................................................................61
Overview ......................................................................................61
Rx Signal Path Interface .............................................................62
Tx Signal Path Interface .............................................................69
Factory Calibrations .......................................................................71
Overview ......................................................................................71
Internal DCXO............................................................................71
Tx RSSI (Tx Monitor).................................................................71
Rx RSSI.........................................................................................71
Rx GM/LNA Gain Step Calibration .........................................72
Tx Power Out vs. Tx Attenuation and Tx Power Out vs.
Carrier Frequency.......................................................................72
Control Output................................................................................73
Overview ......................................................................................73
Description of Control Output Signals ....................................74
0x035 = 0x00 (Calibration Busy and Done)............................74
0x035 = 0x01 (PLL Lock)...........................................................75
0x035 = 0x02 (Calibration Busy) ..............................................75
0x035 = 0x03 (Rx Gain Control) ..............................................75
0x035 = 0x04 (Rx Gain Control) ..............................................76
0x035 = 0x05 (Rx Gain Control) ..............................................76
0x035 = 0x06 (Rx Gain Control) ..............................................76
0x035 = 0x07 (Rx Gain Control) ..............................................76
0x035 = 0x08 (Rx Gain Control) ..............................................76
0x035 = 0x09 (RxOn, TxOn, RSSI) ..........................................77
0x035 = 0x0A (Digital Overflow) .............................................77
0x035 = 0x0B (Calibration and ENSM States)........................77
0x035 = 0x0C (Gain Control) ...................................................77
0x035 = 0x0D (Tx Quadrature and RF DC Calibration
Status) ...........................................................................................78
0x035 = 0x0E (Rx Quadrature and BB DC Calibration
Status) ...........................................................................................78
0x035 = 0x0F (Gain Control) ....................................................78
0x035 = 0x10 (Gain Control and RSSI) ...................................78
0x035 = 0x11 (AuxADC Digital Output) ................................78
0x035 = 0x12 (Gain Control, Power Word Ready).................78
0x035 = 0x13 (Gain Control, Power Word Ready).................79
0x035 = 0x14 (Digital Overflow) ..............................................79
0x035 = 0x15 (DC Offset Tracking) .........................................79
0x035 = 0x16 (Gain Control) ....................................................79
0x035 = 0x17 (Gain Control) ....................................................80
0x035 = 0x18 (DC Offset Tracking, Power Word Ready) .....80
0x035 = 0x19 (Charge Pump Calibration States) ...................80
0x035 = 0x1A (Rx VCO and ALC Calibration States)...........80
0x035 = 0x1B (Tx VCO and ALC Calibration States) ...........80
0x035 = 0x1C (Rx VCO Calibration States)............................80
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0x035 = 0x1D (Tx VCO Calibration States)........................... 80
0x035 = 0x1E (Gain Control, Temp Sense Valid, AuxADC
Valid)............................................................................................ 81
0x035 = 0x1F (Gain Control).................................................... 81
AuxADC/AuxDAC/GPO/Temp Sensor ...................................... 82
Overview...................................................................................... 82
AuxDAC ...................................................................................... 82
AuxADC ...................................................................................... 83
Internal Temperature Sensor .................................................... 84
General Purpose Output Control............................................. 85
Baseband Synchronization ............................................................ 87
Overview...................................................................................... 87
Multichip Synchronization........................................................ 87
Procedure..................................................................................... 88
Synchronization Verification .................................................... 89
Digital Interface Specification....................................................... 90
Overview...................................................................................... 90
CMOS Mode Data Path and Clock Signals............................. 91
CMOS Maximum Clock Rates and Signal Bandwidths........ 92
Single Port Half Duplex Mode (CMOS).................................. 93
Single Port TDD Functional Timing (CMOS) ....................... 94
Single Port Full Duplex Mode (CMOS) .................................. 97
Single Port FDD Functional Timing (CMOS) ....................... 99
Dual Port Half Duplex Mode (CMOS).................................. 100
Dual Port TDD Functional Timing (CMOS)....................... 101
Dual Port Full Duplex Mode (CMOS) .................................. 103
Dual Port FDD Functional Timing (CMOS) ....................... 104
Data Bus Idle and Turnaround Periods (CMOS) ................ 105
Data Path Timing Parameters (CMOS) ................................ 105
LVDS Mode Data Path and Clock Signals ............................ 106
LVDS Mode Data Path Signals ............................................... 107
LVDS Maximum Clock Rates and Signal Bandwidths ....... 108
Dual Port Full Duplex Mode (LVDS).................................... 109
Data Path Functional Timing (LVDS)................................... 109
Data Path Timing Parameters (LVDS).................................. 111
Serial Peripheral Interface (SPI)............................................. 113
Additional Interface Signals.................................................... 116
Power Supply and Layout Guide ................................................ 117
Overview ................................................................................... 117
PCB Material And Stack Up Selection .................................. 117
RF Transmission Line Layout................................................. 118
Fan-out and Trace Space Guidelines ..................................... 119
Component Placement and Routing Guidelines ................. 120
Power Management and System Noise Considerations...... 120
Power Distributions for Different Power Supply Domains 124
Rx LO Frequency Deviations Due to Power Supply
Transients .................................................................................. 126
Related Links................................................................................. 128
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Change to Table 50 ....................................................................... 108
3/14—Revision 0: Initial Version

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INTRODUCTION
TERMINOLOGY
AGC
Automatic gain control where an algorithm in the AD9361
controls the receive path gain.
BBP
Baseband processor (or digital baseband).
BB
Baseband. Baseband received signals are those that have already
been downconverted from RF. Baseband transmit signals are
those that have not yet been upconverted to RF.
BB DC Cal
Baseband DC calibration. An on-chip calibration that reduces
the DC power in the received data by adding digital correction
words to the data between the Half-Band 1 filter and the receive
FIR filter. See the Initialization and Calibration section for more
information.
BBP
Baseband processor (or, digital baseband).
Cal
Calibration.
DC
Literally direct current. In this document, DC refers to
undesired received power in the center of the complex received
baseband spectrum.
ENSM
Enable state machine. This on-chip state machine moves the
AD9361 through its states and it also controls other functions
within the AD9361. See the Enable State Machine Guide section
for more information.
FDD
Frequency division duplex in which transmit and receive signals
can be present at the same time but use different frequencies
LMT
LNA, mixer, TIA. LMT refers to the LMT gain table as well as
an analog peak detector that monitors the signal level at the
input of the analog LPF. See the Gain Control section for more
information.
LO
Local oscillator, which refers to the desired RF carrier frequency
for the receiver and the transmitter.
LPF
Low-pass filter, which refers to the third-order analog low-pass
filter preceding the receive ADC and following the transmit
DAC.
LUT
Look up table, several calibration and functions depend on
either reading or storing look up tables for future use.
MGC
Manual gain control where the BBP controls some or all of the
gain control parameters in the AD9361.
PLL
Phase locked loop. The AD9361 uses PLLs to generate the
various clock rates within the chip as well as the Tx and Rx LO
frequencies.
RF
Radio frequency.
RF DC Cal
Radio frequency DC calibration is an on-chip calibration that
reduces DC power in the received data by applying a compen-
sating voltage between the LNA and the mixer. See the
Initialization and Calibration section for more information.
TDD
Time division duplex in which transmit and receive signals can
be present on the same frequency but at different times.
VCO
A voltage controlled oscillator (VCO) is a circuit in which the
output frequency of the oscillator is controlled by an input
voltage level. These VCOs are part of the PLLs on the AD9361.
The AD9361 must calibrate the VCOs before the frequency they
produce is accurate and stable.
REGISTER AND BIT SYNTAX
When a register with absolute bit locations is described in this
user guide, the format is always in hex for the register and
[Dx:Dy] for the bits. This format is best described by an
example such as 0x016[D0], which equates to Register 0x016
(hex), and only the lowest bit of this register. Thus, the register
and the bit locations are specifically delineated.
When describing the value of just a few bits, the following
format is used: x’byyy.
where
x equals the number of bits described.
b indicates binary.
yyy represents three digital bits with values of 0 or 1.
As an example, if two bits equal 2’b01, then the LSB = 1 and the
next higher bit = 0.
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INITIALIZATION AND CALIBRATION
OVERVIEW
The AD9361 powers up into a sleep state for minimal power consumption. Before the AD9361 is operational, its clocks must be
enabled and initial calibrations completed. The purpose of this section is to describe in detail the operation of the different initialization
calibrations.
Table 1 lists the initialization calibrations documented in this section.
Table 1. Initialization Calibrations Detailed in this Section
Calibration Run Frequency Calibration Done Bit
BBPLL VCO calibration Once; any time BBPLL frequency changes 0x5E[7], 1 when locked
RF synthesizer charge pump
calibration
Once Rx: 0x244[7], 1 when done
Tx: 0x284[7], 1 when done
RF synthesizer VCO calibration Occurs automatically when integer frequency word written. In TDD, occurs when TXNRX
changes logic level.
Rx: 0x247[1], 1 when locked
Tx: 0x287[1], 1 when locked
Baseband Rx analog filter tune
Once; update when BW changes
0x016[7], self clears when
done
Baseband Tx analog filter tune Once; update when BW changes
0x016[6], self clears when
done
Baseband Tx secondary filter tune Once; manual equations, update when BW changes
Rx TIA calibration Once; manual equations, update when BW changes
Rx ADC setup Once; manual LUT or equations, update when ADC sampling rate changes
Baseband DC offset Once 0x016[0], self clears when
done
RF DC offset Any time LO frequency changes more than 100 MHz 0x016[1], self clears when
done
Rx quadrature calibration Any time LO frequency changes more than 100 MHz Tracking runs continuously
Tx quadrature calibration Any time LO frequency changes more than 100 MHz 0x016[4], self clears when
done
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INITALIZATION CALIBRATIONS
Initialization calibrations are calibrations that must be run each
time the AD9361 device is powered up or hard reset using the
RESETB pin. Several of the calibrations only need to run once
during initialization and do not re-run during operation.
Others are dependent on the carrier frequency, temperature, or
other parameters and need to run initially and when certain
events occur (such as changing the carrier frequency more than
100 MHz). As long as power is applied to the AD9361 device,
the calibration results are stored, including while in the SLEEP
state.
The six calibrations in the calibration control are part of a
calibration sequence state machine. After a calibration
completes, the bit that was set to initialize the calibration will
self clear. If more than one calibration is enabled in a single
register write, the calibrations will progress in a set order
controlled by a state machine in the AD9361. Table 2 shows the
sequence of calibrations. When the calibration sequence state
holds a value of 0x1, the calibrations are complete. Some
calibrations depend on the results of previously run
calibrations. The Rx baseband filter and Tx baseband filter
calibrations are not part of the calibration sequence state
machine, and should run only when all other calibrations are
not running.
Table 2. Automatic Calibration Sequence and Calibration Status
Calibration Sequence State[3:0] Active Calibration
0x0 Calibration WAIT state
0x1 Calibrations done
0x2 Baseband DC offset calibration
0x3 RF Rx DC offset calibration
0x4 Tx1 quadrature calibration
0x5
Tx2 quadrature calibration
0x6 Rx1 quadrature calibration
0x7 Rx2 quadrature calibration
0x8 Tx monitor calibration (DC offset)
0x9 Rx GM\LNA gain step calibration
0xA to 0xF Flush states
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BBPLL VCO CALIBRATION
The BBPLL VCO calibration must be run during initialization
of the AD9361 device. This calibration is run as part of the
ad9361_bbpll_set_rate function. The maximum calibration
time is calculated in Equation 1.
3456
_
max
×






×
=ScaleCLKREF
ingDivideSett
BBPLL
VCOcalTime
(1)
RF SYNTHESIZER CHARGE PUMP CALIBRATION
The charge pump calibration must be run once during
initialization of the AD9361 device. This calibration matches
the up and down currents for the RF PLL’s charge pump, and is
run during the ad9361_txrx_synth_cp_calib function. This
calibration must be run the first time the AD9361 device enters
the ALERT state. The calibration completes after a maximum of
36864 (Scaled_REF_CLK_IN) cycles.
RF SYNTHESIZER VCO CALIBRATION
The AD9361 contains two synthesizers. When using TDD
mode, the Rx synthesizer is only enabled when TXNRX is low.
The Tx synthesizer is only enabled when TXNRX is high.
During initial calibrations, it is recommended to set the
AD9361 device into FDD mode to enable both synthesizers
while in the ALERT state to simplify calibrations.
The VCO calibration is run during the ad9361_set_rx_lo_freq
and ad9361_set_tx_lo_freq functions. First, set up any
synthesizer setup registers, then write the fractional frequency
words, followed by the integer frequency word last. The
calibration time can be traded off with calibration accuracy. It is
recommended for FDD applications, to use the longest
calibration for better accuracy since once in the FDD state, it
may be a long time before a synthesizer VCO calibration occurs
again. In TDD, the calibration time will need to be set to meet
the TDD turnaround time, while achieving the most accurate
calibration possible. In TDD, the Rx VCO calibration will occur
each time the receiver synthesizer is powered up (when TxRNX
switches from high to low logic level). The Tx VCO calibration
will occur each time the transmitter synthesizer is powered up
(when TXNRX switches from low to high logic level). See
Equation 2 for the calibration time.
The VCO calibrations can be masked (disabled) for certain
cases such as the fast lock synthesizer mode, or when an HFDD
application is required. Using the FDD Synth LUT instead of
the TDD Synth LUT could be used to acquire a temperature
stable lock for cases where there is not time to run the VCO
calibration in TDD.
Calibration completion can be detected by reading the Rx PLL
Lock bit and the Tx PLL Lock bit. The lock bits will read Logic 1
when the PLLs are locked. The bits are also available on the
control output pins.
9
_
12
2
,max
×





+
×
+
++=
ALC
count
2
us
usVCOcalTime
wait
ScaleCLKREF
N
waitRFPLL
(2)
where:
=8
 +18
( ×)
 =40
_ ×
 = 2()
Table 3. Example Calculated VCO Calibration Times for FDD Default Settings
VCO Cal Count REF_CLK Scale wait2(µs) waitALC (µs) Ncount Calibration Time (µs)
3 19.20 2 0.885 1.042 1024 255.073
3 30.72 2 0.553 0.651 1024 160.171
3 40.00 2 0.425 0.500 1024 123.475
Table 4. Example Calculated VCO Calibration Times for TDD Defaults
VCO Cal Count REF_CLK Scale wait2(µs) waitALC (µs) Ncount Calibration Time (µs)
1 19.20 2 0.885 1.042 256 75.073
1 30.72 2 0.553 0.651 256 47.671
1 40.00 2 0.425 0.500 256 37.075
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BASEBAND Rx ANALOG FILTER CALIBRATION
The baseband Rx analog filter calibration tunes the cutoff
frequency of the third-order Butterworth Rx anti-aliasing filter.
The Rx filter is located just before the ADC in the Rx signal
path and is normally calibrated to 1.4× the baseband channel
bandwidth (BBBW). This calibration is important for Rx
interferer rejection. Note that the BBBW is half the complex
bandwidth and coerced between 28 MHz to 0.20 MHz for the
equations used in this filter tuning. To calibrate this filter, the
BBPLL is divided down using a divide by 1 to 511 divider
dedicated to the Rx tuner block.
 =  × ()
, × .× (3)
The Rx baseband analog filter calibration runs during the
ad9361_set_rx_rf_bandwidth function. Calibration completion
can be monitored on a control output pin or by reading the
calibration control register until the Rx baseband filter
calibration bit self clears.
Because the filter calculation uses a ceiling function to generate
the divider there will be some quantization of the corner
frequency. If the quantization is too large it may be necessary to
adjust the desired BBBW to compensate.
, = × ()
.× ×  (4)
  =610 ×()
, × .× (5)
Table 5. Typical Rx Baseband Filter Calibration Times
Standard
Desired
BBBW (MHz)
BBPLL
Frequency (MHz) RxBBF Divider (decimal) Actual BBBW (MHz)
Maximum Calibration
Time (µs)
LTE 5 MHz 2.5 983.04 31 2.499 19.236
LTE 10MHz 5 983.04 16 4.841 9.928
LTE 15 MHz 7.5 737.28 8 7.262 6.619
LTE 20 MHz
10
983.04
8
9.683
4.964
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BASEBAND Tx ANALOG FILTER CALIBRATION
The baseband Tx analog filter calibration tunes the cutoff
frequency of the third-order Butterworth Tx anti-imaging filter.
The Tx filter is located just after the DAC in the Tx signal path
and is normally calibrated to 1.6× the BBBW. Note that the
BBBW is half the complex bandwidth and coerced between
20 MHz to 0.625 MHz for the equations used in this filter
tuning. To generate this Tx tune clock, the BBPLL is divided
down using a divide by 1 to 511 divider dedicated to the Tx
tuner block.
 =  × ()
, × .× (6)
The Tx baseband analog filter calibration runs as part of the
ad9361_set_tx_rf_bandwidth. Calibration completion can be
monitored on a control out pin or by reading calibration
control until the Tx baseband filter calibration bit self clears.
, = × ()
.× ×  (7)
  =355 ×()
, × .× (8)
Similar to the baseband Rx analog filter, there is quantization of
the corner frequency for the Tx analog filter as well. If the
quantization becomes too large it may be necessary to adjust the
desired BBBW.
Table 6. Typical Tx Baseband Filter Calibration Times
Standard
Desired
BBBW (MHz)
BBPLL Frequency
(MHz)
TxBBF Divider
(decimal) Actual BBBW (MHz)
Max Calibration
time (µs)
LTE 5 MHz 2.5 983.04 28 35.1086 10.1115
LTE 10MHz 5 983.04 14 70.2171 5.0558
LTE 15 MHz 7.5 737.28 7 105.326 3.3705
LTE 20 MHz 10 983.04 7 140.434 2.5278
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BASEBAND Tx SECONDARY FILTER
The baseband Tx secondary filter is a tunable single pole filter
after the baseband Tx analog filter. The Tx secondary filter
corner is ideally set to 5 times the baseband bandwidth to help
filter out of band Tx noise emissions. This filter is programmed
when the ad9361_set_tx_rf_bandwidth function is called.
Rx TIA CALIBRATION EQUATIONS
The Rx transimpedance amplifier (TIA) is located between the
mixer and Rx baseband analog filter. The TIA has two gain
settings (0 dB gain and −6 dB gain), and applies a single pole
filter with a corner at 2.5× the baseband bandwidth. The
corner frequency of the Rx TIA is programmed when the
ad9361_set_rx_rf_bandwidth function is called. When the gain
index in the AD9361 Rx gain table changes the Rx TIA gain
setting, the AD9361 device will automatically scale the amplifier
to maintain the same corner frequency.
Rx ADC SETUP
The receive ADC is a third-order continuous time delta-sigma
modulator and is highly programmable. The values in many of
the ADC registers change with sampling clock frequency while
others do not change but the correct initial settings are critical
for proper operation. The ADC is programmed with the
ad9361_set_rx_rf_bandwidth function.
BASEBAND DC OFFSET CALIBRATION
It is recommended to run the baseband DC offset calibration
once during device initialization in the ALERT state. Since the
baseband signal path does not change with different wireless
standards or clock frequencies, it should not need to be run
again. The baseband DC offset correction values are stored for
all of the Rx analog baseband filter gain steps. The correction
words are applied as the Rx gain changes based on the current
Rx gain table index. This calibration is run during the
ad9361_bb_dc_offset_calib function call.
The one-shot baseband DC offset calibration will complete in a
finite time depending on the device settings. The calibration
time is 404,000 ClkRF cycles.
BASEBAND DC OFFSET TRACKING
Baseband DC offset tracking should be used in conjunction
with the RF DC offset tracking option. A high-pass filter loop is
utilized to track DC changes caused by the RF DC offset and Rx
quadrature correction block. The speed and accuracy of the BB
DC tracking loop are configurable. Also, an option exists for the
BB DC offset tracking to attack/settle quickly after a gain
change and then after a certain time switch to slower DC offset
tracking updates. When using the tracking mode, first run an
initial one-shot baseband DC offset calibration to minimize any
static DC offsets in the signal chain. Then enable tracking along
with the desired tracking loop settings. Baseband DC offset
tracking is enabled in the ad9361_tracking_control function
call.
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UG-570 AD9361 Reference Manual
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RF DC OFFSET CALIBRATION
The RF DC offset calibration should be run once during
initialization, or potentially when moving to a new carrier
frequency that is more than 100 MHz away from the previous
carrier frequency. This calibration should be run in the ALERT
state while the Rx synthesizer is enabled. The calibration is run
during the ad9361_rf_dc_offset_calib function. The internal
calibration results LUT stores separate results for the RF Rx A
input. If using the RF Rx B or C inputs along with the RF Rx A
input, you should run the calibration twice, once with each
input band selected. After calibrating each band, switching
between from the A input to the B or C input should not
require another calibration. Since the B and C inputs use the
same calibration results, switching from Input B to Input C may
require running the RF DC offset calibration.
When using the full Rx gain table, the RF DC offset calibration
only calibrates at gain indexes that are designated to calibrate in
the Rx gain table. This is because several consecutive gain steps
may leave the front end gain at the same setting, while only
changing baseband gain settings. The RF DC offset correction is
only designed to remove DC offset due to the RF parts of the
signal chain. By only running the calibration at gain indexes
that actually change the front end gain, the calibration time is
reduced. If the LUT does not hold a DC correction value for the
current Rx gain index, it will use the DC offset correction for
the next higher gain index that was calibrated. In the case of a
split Rx gain table, the calibration runs at each LMT gain index.
The RF DC offset tracking is enabled by with the ad9361_
tracking_control function. The tracking triggers an RF DC
offset update based on three events: Rx gain change, no energy
detected, or when the ENSM exits the Rx state. The DC Offset
Update bit field setting allows enabling or disabling any
combination of these events. Disabling RF DC offset tracking
would use the initially calibrated RF DC offset and never update
the correction words.
The calibration time and accuracy is calculated using Equation 9
and Equation 10. The calibration begins at minimum gain
(index = 0) and moves toward maximum gain. The RF DC
offset correction for each enabled Rx gain index is stored in a
LUT and applied when the Rx gain index is used. If the full Rx
gain table is used, the RF DC offset is calibrated only at gain
indexes specified to calibrate in the Rx gain table. If the Rx
gain table is split, the Number of Enabled Gain indexes in
Equation 10 equals 41 gain steps.
Length Of Each Average = [{(RF DC Offset Count × 256) + 255} + 32] (9)
Total Calibration time(CLKRF Clock Cycles) = 21 ×Length Of Each Average × (Number of Enabled Gain indexes + 1) (10)
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AD9361 Reference Manual UG-570
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Rx QUADRATURE TRACKING CALIBRATION
The Rx quadrature tracking uses the Rx data to continuously
minimize the phase and gain error in the receive path. The
tracking algorithm is configured and enabled in the
ad9361_tracking_control function. As soon as the AD9361
ENSM enters the Rx or FDD state, the tracking will begin
minimizing the quadrature error.
Tx QUADRATURE CALIBRATION
The Tx quadrature calibration uses a calibration signal
internally to minimize the Tx DC offset, gain, and phase errors
to improve the performance of the transmit chain. The
ad9361_tx_quad_calib function configures and runs this
calibration during initialization in the ALERT state. Completion
of the calibration can be monitored by reading the Calibration
Control register until the appropriate bit self clears. When
changing the carrier frequency, a much faster refresh calibration
can be initiated if desired to update the Tx offset, gain and
phase error corrections. It is also recommended to refresh the
calibration results if the device temperature changes
dramatically. The AuxADC can be used to measure the device
temperature using the internal temperature sensor, and to know
when to refresh the Tx quadrature calibration.
The Tx quadrature calibration is a convergence algorithm, but
has a maximum calibration time described in the following
paragraphs. Equation 11 calculates the number of CLKRF clock
cycles used for maximum calibration time. CLKRF is the clock
rate at the output of the Tx FIR filter (after Tx FIR
interpolation).
94464#
)( ×= TxChannelsTX sclockcycleCLKRFeQuadcalTim
(11)
The Tx quadrature calibration stores a separate set of
calibration results for the Tx_A and Tx_B output paths. If using
both the Tx_A output and the Tx_B outputs, run the calibration
twice, once with each output path selected.
To setup the Tx quadrature calibration first make sure that the
NCO frequency is within the Rx baseband filter bandwidth.
Depending on the digital filter configuration, it may be
necessary to sweep the NCO phase offset to find the optimal
setting. More information on the setup of this phase sweep can
be found in the Tx Quad Cal FAQ on the AD9361 Engineer
Zone website.
If using a custom Rx gain table, verify that the Tx quadrature
calibration gain index in register Tx quad full/LMT gain points
to an index with the TIA index = 1 and LPF index = 0. When
using a split gain table, Register Tx Quad Full/LMT Gain
should point to a gain index with TIA index = 1. For a split gain
table, set the LPF index in Register Tx Quad LPF Gain to a
value of 0x00.
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UG-570 AD9361 Reference Manual
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REFERENCE CLOCK REQUIREMENTS
OVERVIEW
The AD9361 uses fractional-n phase locked loops (PLLs) to
generate the transmitter and receiver local oscillator (LO)
frequencies as well as the oscillator (the baseband PLL) used for
the data converters, digital filters, and I/O port. These PLLs all
require a reference clock input, which can be provided by an
external oscillator or by an external crystal (XO) and a digitally
programmable on-chip variable capacitor. The capacitor fine-
tunes the resulting reference clock frequency. This combination
of XO and trimming capacitor is collectively referred to as the
DCXO.
Applications such as wireless base stations require that the
reference clock lock to a system master clock. In these
situations, use an external oscillator such as a VCTCXO in
conjunction with a synchronizing PLL such as the AD9548.
Wireless user equipment (UE), however, dos not typically need
to be locked to a master clock but they do need to adjust the LO
frequency periodically to maintain connection with a base
station. The base station (BTS) occasionally informs the UE of
its frequency error relative to the BTS. By adjusting the
trimming capacitor, the baseband processor can adjust the
reference clock frequency and thus the LO frequency as needed.
The RFPLLs and the BBPLL should maintain minimal
frequency drift with temperature. However, typical XOs have an
S curve response of frequency vs. temperature, making it more
difficult for a baseband processor to correct the frequency error
at startup and during operation.
This section describes the setup, operation, and recommended
specification of the DCXO and reference clock.
DCXO SETUP AND OPERATION
To use the DCXO, connect an external crystal (XO) between the
XTALP and XTALN pins of the AD9361. Valid crystal resonant
frequencies range from 19 MHz to 50 MHz. The crystal must be
an AT cut fundamental mode of vibration with a load
capacitance of 10 p F.
By adjusting a capacitor within the AD9361, the resulting
DCXO frequency can be adjusted to compensate for XO
frequency tolerance and stability. This adjustment is enabled
using the ad9361_set_dcxo_tune function. The resolution of the
DCXO varies with coarse word with a worst-case resolution (at
coarse word = 0) of 0.0125 ppm. Using both coarse and fine
words, the DCXO can vary the frequency over a ±60 ppm
range.
Using a bench test, nominal DCXO trimming words should be
determined and then used in during initialization. These
nominal words should be written before the BBPLL is
calibrated. After initialization (after the BBPLL and RFPLLs are
programmed, calibrated, and locked), the DCXO words may be
written at any time.
Figure 1 shows the variation of DCXO frequency over all
possible variations of coarse and fine word. The XO nominal
frequency used in this test was 40 MHz.
Figure 1. DCXO Frequency vs. Coarse and Fine Words
40003000
39995000
39996000
39997000
39998000
39999000
40000000
40001000
40002000
01000 2000 3000 4000 5000 6000 7000 8000
DCXO FREQUENCY (Hz)
DCXO FINE WORD (REG 0x293 AND 0x294)
COARSE WORD IN 0x292 = 63
COARSE WORD IN 0x292 = 0
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AD9361 Reference Manual UG-570
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REFERENCE CLOCK SETUP AND OPERATION
If the DCXO is not used, an external reference clock needs to
be ac-coupled to XTALN (Pin M12). XTALP (Pin M11) is not
connected (leave floating). The clock frequency must be
between 5 MHz and 320 MHz, and can be scaled by 1×, ½×, ¼×
and 2× using BBPLL, Rx and Tx reference dividers. The valid
frequency range for the RFPLL phase detectors is 10 MHz to
80 MHz, and the scaled frequency of the reference clock must
be within this range. For optimum phase noise it is
recommended to operate the scaled clock as close to 80 MHz as
possible. The selection between DCXO and external reference
clock is made in the ad9361_init function.
The level for the clock should be 1.3 V p-p maximum(lower
swings can be used but will limit performance). This signal can
be a clipped sine wave or a CMOS signal. The best performance
will be seen with the highest slew rate possible.
The XTALN (Pin M12) has an input resistance of ~ 10 kΩ in
parallel with 10 pF.
PHASE NOISE SPECIFICATION
The AD9361 Rx and Tx RFPLLs use the DCXO or external
clock as their reference clock as well. For this reason, it is
extremely critical that the crystal or clock source have very low
phase noise. The recommended phase noise specification is
shown in Figure 2.
Figure 2. Phase Noise vs. Offset Frequency
–160
–140
–130
–120
–110
–100
–90
–80
10 100 1k 10k 100k 1M
PHASE NOISE (dBc/Hz)
OFFSET FREQUENCY (Hz)
–150
11668-003
Rev. A

UG-570 AD9361 Reference Manual
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RF AND BBPLL SYNTHESIZER
OVERVIEW
The AD9361 transceiver contains two identical RFPLL
synthesizers to generate the required LO signals, which are
programmed independently. One is programmed for the Rx
channel and the other for the Tx channel. The transceiver also
contains a BBPLL synthesizer to generate the required sampling
and internal operational clocks. The PLL synthesizers are all of
fractional–N architecture with completely integrated VCOs and
loop filters. They require no external parts to cover the entire
frequency range of the device. This configuration allows the use
of any convenient reference frequency for operation on any
channel with any sample rate. For FDD operation, the
frequency of Tx and Rx can be the same or different, and both
RFPLL synthesizers operate simultaneously. For TDD
operation, the RFPLL synthesizers alternately turn on as
appropriate for Rx and Tx frames.
RFPLL INTRODUCTION
The fundamental frequency of the RFPLLs is from 6 GHz to
12 GHz. Local oscillator frequencies ranging from 47 MHz to
6 GHz are created by dividing the PLL frequency. The Rx PLL is
configured and calibrated using the ad9361_set_rx_lo_freq
function, and the Tx PLL is configured using the
ad9361_set_tx_lo_freq function. Each synthesizer must be
configured and calibrated separately.
AD9361 PLL ARCHITECTURE
The following sections show block diagrams of the AD9361 PLL
that consist of the reference block, the main PLL block, and the
LO GEN output block. The VCO always operates between
6 GHz to 12 GHz.
REFERENCE BLOCK
The reference frequency can be generated via the on-chip
DCXO or an external clock source can provide this input to the
device. A MUX selects the desired source. The reference is then
split and applied to three independent conditioning blocks also
known as ref dividers. The conditioning blocks provide four
options such that the PLL reference frequency, FREF, (the loop
reference applied to the PLL phase detector) is either buffered,
doubled, halved, or divided by 4. Independent blocks make it
possible to have a different FREF for the RF and BBPLLs. The
reference scalers will be set by the ad9361_init function. For
best RFPLL performance, Analog Devices recommends
selecting a reference clock or crystal that will be able to scale as
close to 80 MHz as possible.
Figure 3. PLL Reference Block
H6
DO NOT USE
CONNECT H6 TO GROUND
DCXO
20MHz TO 50MHz
M11
M12
1
0
1
0
BBPLL
F
REF
FOR BEST
PERFORMANCE:
35MHz TO 80MHz
FOR BEST
PERFORMANCE:
35MHz TO 70MHz
XTALP OR
OPEN FOR EXTERNAL REFERENCE
XTALN OR
EXTERNAL REFERENCE INPUT
5MHz TO 320MHz
(19MHz TO 80MHz RECOMMENDED)
÷2
÷4
×2
÷2
÷4
×2
÷2
÷4
×2
TX SYNTH
F
REF
RX SYNTH
F
REF
10MHz TO 80MHz
10MHz TO 80MHz
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Rev. A

AD9361 Reference Manual UG-570
| Page 17 of 128
MAIN PLL BLOCK
The independent Rx and Tx PLLs use fractional-N techniques
to achieve the channel synthesis. The entire PLL is integrated
on-chip, including the VCO and the loop filter. The PLL always
operates over the range of 6 GHz 12 GHz. The charge pump
current is programmable as are all of the loop filter components
allowing optimization of performance parameters for almost
any application.
Configuration for a given frequency consists of a combination
of calculating the required divider values and referring to an
Analog Devices supplied lookup table to configure the VCO for
stable performance over temperature. The main PLL output is
divided by the VCO divider block to create the frequency bands
that allow the device to operate continuously from 70 MHz to
6 GHz. Figure 5 shows how the bands are created. The
synthesizer configuration registers, loop filter, integer and
fractional words, and VCO divider are calculated in the
ad9361_rx_lo_freq and ad9361_tx_lo_freq function calls.
Figure 4. PLL Synthesizer Block Diagram (Rx and Tx Synthesizers are Identical)
Figure 5. VCO Divider
8/9
PRE-SCALER
Σ-Δ
MODULATOR
LC VCO
PROGRAMMABLE
INTEGRATED LOOP
FILTER
CHARGE
PUMP
PFD
UP
DN
B COUNTER
A COUNTER
FO CAL
ALC CAL
VCO
LDO
2
4
×2
1Ω 1µF
CERAMIC
VCO LDO IN
CONNECTED EXTERNALLY
NECESSARY FOR LDO STABILITY
VCO LDO OUT
VDDA1P1-VCO
FOR BEST
PERFORMANCE
F
REF
= 35MHz TO 80MHz
FREF =
10MHz TO 80MHz
FREF =
5MHz TO 320MHz
0.1mA TO 6.4mA 0µA TO 787.5µA
12.5µA STEPS
TO
VCO DIVIDER
BLOCK
6GHz TO 12GHz
100µF
÷
÷
11668-005
MUX/SELECTABLE BUFFERS
÷2 ÷2 ÷2 ÷2÷2÷2÷2
VCO INPUT
6GHz TO 12GHz
IQIQIQIQ
LOILOQ
47MHz TO 6GHz
3GHz TO 6GHz 1.5GHz TO 3GHz 750MHz TO 1.5GHz 375MHz TO 750MHz 187.5MHz TO 375MHz 93.75MHz TO 187.5MHz 46.875MHz TO 93.750MHz
11668-006
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UG-570 AD9361 Reference Manual
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CHARGE PUMP CURRENT
The charge pump current is 6-bit programmable and varies
from 0.1 mA to 6.4 mA with 0.1 mA steps. The charge pump
current needs to be calibrated during initialization, and can
then use the Analog Devices supplied LUTs during operation.
RFPLL LOOP FILTER
The RFPLL loop filter is fully integrated on-chip and is a
standard passive Type II third-order filter with five 4-bit
programmable components (see Figure 6). The loop filter
values are included in the Analog Devices provided synthesizer
LUTs and should not be modified.
Figure 6. Loop Filter
VCO CONFIGURATION
VCO configuration consists of writing a few static registers
from an Analog Devices provided lookup table and then enabling
an automatic calibration procedure to configure the VCO tune
voltage (Vtune) and ALC. The VCO calibration is triggered in
one of three ways: when going from wait state to alert state,
when going from the synthesizer power-down state to the alert
state (TDD), or writing the LSBs of the Rx or Tx frequency
integer word. All LUT writes for the VCO, loop filter, and other
synthesizer settings should be written into the chip before
triggering the VCO calibration. Note that charge pump calibra-
tion should be completed before a VCO calibration is started.
When in TDD mode using hardware (ENABLE/TXNRX)
control and the device state machine is in the ALERT state, the
synthesizers power up and down with the state of the TXNRX
control line. A typical example sequence for TDD operation is
Rx-ALERT-Tx-ALERT-Rx. The BB controller sets the level of
the TXNRX line in ALERT to steer the device into the correct
next state. Then state machine advances to the next state with
the following ENABLE edge. During ALERT, as the BB
controller changes the level of TXNRX from low to high, the Rx
synthesizer turns off, the Tx synthesizer will turn on, and a Tx
VCO calibration will be triggered. Similarly, during a following
cycle, as the BB controller changes the state of TXNRX from
HIGH to LOW, the Tx synthesizer turns off, the Rx synthesizer
will turn on, and a Rx VCO calibration will be triggered.
Operationally, the BB processor should transition the TXNRX
line shortly after entering the alert mode so that the synthesizer
has as much of the time as possible between frames to calibrate
and lock. Typical TDD calibration plus lock times are on the
order of 45 µs to 60 µs. For faster lock times, refer to the TDD
Mode Faster Lock Times section.
VCO CALIBRATION
The time the calibration takes to complete is programmable.
Usually a fast calibration is appropriate for TDD systems, and a
slow calibration is appropriate for FDD. For TDD, the
synthesizer will only be on for a short time, so the danger that
temperature drift would cause it to lose lock is small. For FDD,
the synthesizer could potentially be locked indefinitely, so a
longer more accurate calibration is called for to ensure that
Vtune is sufficiently centered. Example calibration times are
shown in the RF Synthesizer VCO Calibration section.
The device includes a Fast Lock mode that makes it possible to
achieve faster than normal frequency changes by storing all
synthesizer programming information, including the VCO cal
result of this section, into either device registers or the BB
processor memory space to be recalled at a later time. See the
Fast Lock Profiles section for details.
VCO VTUNE MEASUREMENT
For debug purposes, the Vtune voltage can be output to a
package pin. The Vtune voltage is MUXed with the
corresponding (Rx or Tx) EXT_LO_IN pin. This is configured
by setting the VTune Out bit, 0x23B[6] (Rx) or 0x27B[6] (Tx).
For normal operation, these bits should be cleared.
LOCK DETECTOR
A lock detector bit is provided to indicate that the correspond-
ing synthesizer has achieved lock in the configured number of
clock. The lock detector is configured by setting the mode and
count values in the Lock Detect Config registers.
The Lock Detect Count bits set the maximum time allowed for
the RFPLL to lock. If it locks within the specified time, the lock
bits go high. The time is measured in reference clock cycles per
Table 7. It is recommended to use at least 1024 reference clock
cycles.
Table 7. Lock Detect Count
Lock Detect Count (decimal) Reference Clock Cycles
0 256
1 512
2 1024
3 2048
The Lock Detect Mode bits set the lock detect mode of
operation per Table 8. It is recommended to use run lock detect
continuously mode.
Table 8. RFPLL Lock Detect Mode
Lock Detect Mode
(Decimal) RFPLL Lock Detect Mode
0 Disable lock detect
1 Run lock detect once, when RFPLL is enabled
2 Run lock detect continuously
3 Do not use
C1
FROM
CHARGE
PUMP
TO VCO LDO
TO VCO
PROGRAMMABLE
INTEGRATED LOOP
FILTER
11668-007
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AD9361 Reference Manual UG-570
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SYNTHESIZER LOOK UP TABLE
Analog Devices provides synthesizer LUTs to generate the static
register writes needed for the VCO and loop filter. There is a set
of tables for FDD operation and a set of tables for TDD
operation. Each set of tables covers the entire VCO frequency
range, as well three different RFPLL loop reference frequencies.
The FDD tables enable the VCO temperature compensation
with the intent that the user will use longer, more accurate
calibration times for the device to remain in operation
indefinitely. In the TDD tables, the temperature compensation
is not enabled, because it is assumed that the VCO will be
calibrated between Tx and Rx frames. If temperature
compensation is required in a TDD operation then the FDD
tables can be used during the TDD synthesizer calibrations.
The provided LUTs are separated into three tables for 40 MHz,
60 MHz, and 80 MHz reference frequencies. The correct table
to use is the one that closest matches the loop FREF for the
operating mode. Refer to Table 9 for LUT selection based on
scaled reference frequency.
Table 9. Lookup Table Reference
RFPLL FREF Use Lookup Table
35 MHz to 50 MHz 40 MHz
50 MHz o 70 MHz 60 MHz
70 MHz to 80 MHz 80 MHz
TDD MODE FASTER LOCK TIMES
In TDD mode, the Rx and Tx synthesizers are alternately
turned on and off, following the state of the TXNRX control
line. Typically, the synthesizer is set to trigger a VCO
calibration every time it powers up so that it has a fresh
calibration value. If the LO frequency in TDD does not change
from frame to frame, it is not necessary to recalibrate the VCO
every time. The synthesizers retain the VCO calibration result
even after the synthesizer is powered down. When bursting
between Tx/ALERT/Rx … on the same LO frequency, the
synthesizer only needs to relock and can possibly be completed
in 25 µs or less, depending on the loop bandwidth.
To se tup synthesizer in this mode:
1. Setup the VCO for an FDD calibration.
2. Perform VCO calibration.
3. Set the Disable VCO Cal bit.
Step 3 disables the triggering of all VCO calibrations, including
writing of new Integer word. If a new calibration is needed, this
must be cleared.
Note that if the LO frequency is changed, the VCOs will need to
be recalibrated so it will retain the information pertaining to the
new frequency.
EXTERNAL LO
Unlike the internal synthesizers that always operate from 6 GHz
to 12 GHz no matter the RF tune frequency, the frequency
applied when an External LO is used is 2× the desired RF LO
frequency. The range of the EXT LO signal is from 140 MHz to
8 GHz, covering the RF tune frequency range of 70 MHz to
4 GHz. To setup the external LO use the ad9361_trx_ext_
lo_control function.
There are two separate EXT LO inputs, one for Rx and the other
for Tx. The recommended power level for the EXT LO signal at
the AD9361 pin is −3 dBm ≤ pin ≤ +3 dBm, and the maximum
pin must not exceed +6 dBm.
Note that the EXT_LO_IN package pins are multi-purposed
and they can take on a different functionality (Vtune
measurement) when the device is using internal synthesizers.
See the VCO Vtune Measurement section for information.
BASEBAND PLL (BBPLL)
The BBPLL is a fractional-N synthesizer used to synthesize the
digital clocks for the AD9361 chip. The BBPLL synthesizes an
integer multiple of the Rx ADC clock, the Tx DAC clock, all
analog calibration clocks, as well as the clocks used in the digital
section. The BBPLL operates of the range of 715 MHz to
1.430 GHz, which allows practically any sample rate to be
generated from any reference frequency. Table 10 is a listing of
common communication systems showing the system sample
rate and the corresponding BBPLL frequency. The output of the
BBPLL drives a programmable divider chain to result in the
desired sample rate and bus communication rate. The required
BBPLL frequency is usually back-calculated by deciding how
the channel filtering will be accomplished and then selecting
the appropriate output divider that allows the BBPLL to operate
within range. Refer to the Filter Guide section for available
filtering and decimation/integration setups.
Table 10. Clock Rates for the Rx and Tx Digital Data Paths
Plus the Appropriate BBPLL Output Frequencies
System
Sample Rate (MSPS)
BBPLL (MHz)
GSM 0.542 832
LTE 1.4 1.92 983.04
LTE 3.0 3.84 983.04
LTE 5 7.68 983.04
LTE 10 15.36 983.04
LTE 15 23.04 737.28
LTE 20
30.72
983.04
WiMAX 1.75 2 1024
WiMAX 3.5 4 1024
WiMAX 4.375 5 1280
WiMAX 7 8 1024
WiMAX 8.75 10 1280
WiMAX 5 5.6 716.8
WiMAX 10 11.2 716.8
WiMAX 20 22.4 1075.2
802.11a 20 1280
802.11n 40 1280
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UG-570 AD9361 Reference Manual
| Page 20 of 128
BBPLL VCO
The BBPLL VCO is a multiband ring oscillator with Kv of
550 MHz/V that requires a frequency calibration before
operation. The calibration is configured and run with the
ad9361_bbpll_set_rate function.
Figure 7 is a block diagram of the BBPLL. The reference
frequency for the loop is the output of the reference scaler
block, which is identical to, but independent from the reference
scaler blocks for the RFPLLs. The reference block is configured
to buffer, multiply, or divide the device reference frequency
before passing to the to the BBPLL phase detector. For best
performance, it is recommended that the BBPLL reference
scaler block be configured such that the resulting BBPLL FREF is
between 35 MHz to 70 MHz.
Figure 7. BBPLL Block Diagram
F
REF
÷2
÷4 UP
DWN
PFD LPF
F
OUT
F
VCO
715MHz TO 1430MHz
N ÷ (N + 1)
DSM
MODULUS = 2088960
FRACTIONAL WORD
INTEGER WORD
×2
11668-008
Rev. A