Analog Devices ADuCM310 Quick user guide

ADuCM310 Hardware Reference Manual
UG-549
One Technology Way •P. O. Box 9106 •Norwood, MA 02062-9106, U.S.A. •Tel: [phone] •Fax: [phone] •www.analog.com
How to Set Up and Use the ADuCM310
PLEASE SEE THE LAST PAGE FOR AN IMPORTANT
WARNING AND LEGAL TERMS AND CONDITIONS.Rev. C | Page 1 of 192
SCOPE
This reference manual provides a detailed description of the ADuCM310 functionality and features.
Full specifications on the ADuCM310 are available in the product data sheet, which must be consulted in conjunction with this reference
manual when using the device.
FUNCTIONAL BLOCK DIAGRAM
ON-CHIP
1.8V LDO
MEMORY
256k FLASH
32k SRAM
ARM
CORTEX-M3
PROCESSOR
MUX RESET
IOVDDx
AIN0
AIN9
VBUF_VREF2.5B
VDAC0
VDAC7
IDAC0
ADuCM310
VBUF_VREF2.5A
VBUF_1.2V
PVDDx
AVDDx
DGNDx
GENERAL-PURPOSE
I/O PORTS
SWDIO
SWCLK
POR
GPIO PORTS
UART PORT
2 × SPI PORT
2 × I2C PORT
EXT IRQs
INTERNALCHANNELS,
IDACs, TEMPERATURE,
SUPPLIES
2.5V
BAND GAP
VREF
DMA
NVIC
PLA
32 × ELEMENTS SERIAL
WIRE
32.768kHz
16MHz OSC
80MHz PLL
3 × GENERAL-PURPOSE TIMER
WATCHDOG TIMER
WAKE-UP TIMER
PWM
VDAC
VDAC
IDAC5
BUF 14-BIT
SAR ADC
IDAC
IDAC
PGND
11461-001
Figure 1.

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TABLE OF CONTENTS
Scope .................................................................................................. 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 4
Using the ADuCM310 Hardware Reference Manual .................. 5
Number Notations........................................................................ 5
Register Access Conventions ...................................................... 5
Acronyms and Abbreviations ..................................................... 5
Introduction to the ADuCM310 .................................................... 6
Main Features of the ADuCM310.............................................. 7
Memory Organization ................................................................. 8
Clocking Architecture...................................................................... 9
Clocking Architecture Features.................................................. 9
Clocking Architecture Block Diagram ...................................... 9
Clocking Architecture Overview.............................................. 10
Clocking Architecture Operation............................................. 10
Register Summary: Clock Architecture................................... 10
Register Details: Clock Architecture........................................ 10
Power Management Unit............................................................... 14
Power Management Unit Features ........................................... 14
Power Management Unit Overview......................................... 14
Power Management Unit Operation........................................ 14
Code Examples ........................................................................... 15
Register Summary: Power Management Unit ........................ 16
Register Details: Power Management Unit ............................. 16
ARM Cortex-M3 Processor .......................................................... 17
ARM Cortex-M3 Processor Features....................................... 17
ARM Cortex-M3 Processor Overview .................................... 18
ARM Cortex-M3 Processor Operation ................................... 18
ARM Cortex-M3 Processor Related Documents................... 18
ADC Circuit .................................................................................... 19
ADC Circuit Features ................................................................ 19
ADC Circuit Block Diagram..................................................... 19
ADC Circuit Overview.............................................................. 19
ADC Circuit Operation............................................................. 20
ADC Transfer Function............................................................. 20
ADC Typical Setup Sequence ................................................... 22
ADC Input Buffer....................................................................... 22
ADC Internal Channels............................................................. 23
ADC Support Circuits ............................................................... 24
Register Summary: ADC Circuit ............................................. 27
Register Details: ADC Circuit .................................................. 28
Register Summary: Additional Registers ................................ 32
Register Details: Additional Registers ..................................... 32
IDACs............................................................................................... 34
IDAC Features ............................................................................ 34
IDAC Block Diagram................................................................. 34
IDAC Overview.......................................................................... 34
Register Summary: IDAC ......................................................... 40
Register Details: IDAC............................................................... 40
VDACs............................................................................................. 46
VDAC Features........................................................................... 46
VDAC Block Diagram ............................................................... 46
VDAC Overview ........................................................................ 46
VDAC Operation ....................................................................... 47
Register Summary: VDAC........................................................ 49
Register Details: VDAC............................................................. 49
System Exceptions and Peripheral Interrupts............................. 56
Cortex-M3 and Fault Management ......................................... 56
External Interrupt Configuration ............................................ 59
Register Summary: External Interrupts .................................. 59
Register Details: External Interrupts ....................................... 60
Low Voltage Analog Die Interrupt Configuration................. 63
Register Summary: Low Voltage Die Interrupts .................... 63
Register Details: Low Voltage Die Interrupts ......................... 64
Reset ................................................................................................. 65
Reset Features ............................................................................. 65
Reset Operation.......................................................................... 65
Register Summary: Reset .......................................................... 65
Register Details: Reset ............................................................... 66
DMA Controller ............................................................................. 67
DMA Features............................................................................. 67
DMA Overview .......................................................................... 67
DMA Operation ......................................................................... 67
Interrupts..................................................................................... 68
DMA Priority.............................................................................. 68
Channel Control Data Structure .............................................. 68
Control Data Configuration ..................................................... 69
DMA Transfer Types (CHNL_CFG[2:0])............................... 70
Address Calculation................................................................... 72
Aborting DMA Transfers .......................................................... 72

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Register Summary: DMA...........................................................73
Register Details: DMA................................................................73
Flash Controller...............................................................................79
Flash Controller Features...........................................................79
Flash Controller Overview.........................................................79
Flash Controller Operation........................................................80
Flash Memory Operation...........................................................81
Register Summary: Flash Controller........................................87
Register Details: Flash Controller .............................................88
Silicon Identification.......................................................................97
Register Summary: Silicon Identification................................97
Register Details: Silicon Identification.....................................97
Digital Inputs/Outputs ...................................................................98
Digital Inputs/Outputs Features................................................98
Digital Inputs/Outputs Block Diagram....................................98
Digital Inputs/Outputs Overview .............................................98
Digital Inputs/Outputs Operation ............................................99
Digital Port Multiplex.............................................................. 100
Register Summary: Digital Input/Output............................. 102
Register Details: Digital Input/Output.................................. 103
I2C Serial Interface ....................................................................... 110
I2C Features............................................................................... 110
I2C Overview............................................................................. 110
I2C Operation............................................................................ 110
I2C Operating Modes............................................................... 112
Register Summary: I2C0.......................................................... 114
Register Details: I2C0 ............................................................... 115
Register Summary: I2C1.......................................................... 124
Register Details: I2C1............................................................... 125
Serial Peripheral Interfaces ......................................................... 134
SPI Features............................................................................... 134
SPI Overview ............................................................................ 134
SPI Operation ........................................................................... 134
SPI Transfer Initiation ............................................................. 135
SPI Interrupts............................................................................ 137
SPI Wire-OR’ed Mode (WOM) .............................................. 138
SPI CSERR Condition ............................................................. 138
SPI DMA ................................................................................... 138
SPI and Power-Down Modes.................................................. 139
Register Summary: SPI0.......................................................... 140
Register Details: SPI0............................................................... 140
Register Summary: SPI1 ..........................................................144
Register Details: SPI1................................................................144
UART Serial Interface...................................................................148
UART Features ..........................................................................148
UART Overview........................................................................148
UART Operation.......................................................................148
Register Summary: UART .......................................................152
Register Details: UART ............................................................152
General-Purpose Timers..............................................................157
General-Purpose Timers Features..........................................157
General-Purpose Timers Block Diagram ..............................157
General-Purpose Timers Overview .......................................157
General-Purpose Timers Operation ......................................158
Register Summary: General-Purpose Timer 0 .....................160
Register Details: General-Purpose Timer 0 ..........................160
Register Summary: General-Purpose Timer 1 .....................163
Register Details: General-Purpose Timer 1 ..........................163
Register Summary: General-Purpose Timer 2 .....................166
Register Details: General-Purpose Timer 2 ..........................166
Watchdog Timer............................................................................169
Watchdog Timer Features........................................................169
Watchdog Timer Block Diagram............................................169
Watchdog Timer Overview .....................................................169
Watchdog Timer Operation ....................................................169
Register Summary: Watchdog Timer.....................................169
Register Details: Watchdog Timer..........................................170
Wake-Up Timer.............................................................................172
Wake-Up Timer Features.........................................................172
Wake-Up Timer Block Diagram .............................................172
Wake-Up Timer Overview ......................................................172
Wake-Up Timer Operation .....................................................172
Register Summary: Wake-Up Timer ......................................174
Register Details: Wake-Up Timer ...........................................174
Pulse Width Modulation (PWM) ...............................................178
PWM Features ...........................................................................178
PWM Overview ........................................................................178
PWM Operation .......................................................................178
PWM Interrupt Generation ....................................................180
Register Summary: PWM........................................................181
Register Details: PWM.............................................................181
Programmable Logic Array (PLA) .............................................185

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PLA Features ............................................................................. 185
PLA Overview........................................................................... 185
PLA Operation.......................................................................... 186
Register Summary: PLA .......................................................... 189
Register Details: PLA ............................................................... 189
REVISION HISTORY
3/2020—Rev. B to Rev. C
Change to Table 127 ....................................................................... 97
6/2019—Rev. A to Rev. B
Added Table 44 Title ...................................................................... 48
Changes to Table 201.................................................................... 141
3/2016—Rev. 0 to Rev. A
Changes to Table 18........................................................................ 30
Deleted Endnote 1, Table 74; Renumbered Sequentially .......... 64
Changes to Protection, Integrity Section..................................... 78
Added ECC Error Handling Section..................................................81
Added ECC Error During Read Section and ECC Error During
Execution of Sign Command.................................................................. 82
Changes to Table 104 .............................................................................. 86
Changes to Table 105 .............................................................................. 87
Added ECC Enable/Disable, Error Response Register Section
and Table 121; Renumbered Sequentially........................................ 93
Added Flash 0 ECC Error Address Register Section, Table 122,
Flash 1 ECC Error Address Register Section, and Table 123 .......... 94
Change to Table 130 ................................................................................ 99
5/2015—Revision 0: Initial Version

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USING THE ADuCM310 HARDWARE REFERENCE MANUAL
NUMBER NOTATIONS
Table 1.
Notation Description
Bit N Bits are numbered in little endian format, that is, the least significant bit of a number is referred to as Bit 0.
V[x:y] Bit field representation covering Bit x to Bit y of a value or a field (V).
0xNN Hexadecimal (Base 16) numbers are preceded by the prefix 0x.
0bNN Binary (Base 2) numbers are preceded by the prefix 0b.
NN Decimal (Base 10) numbers are represented using no additional prefixes or suffixes.
REGISTER ACCESS CONVENTIONS
Table 2.
Mode Description
RW Memory location has read and write access.
RC Memory location is cleared after reading it.
R Memory location is read access only. A read always returns 0, unless otherwise specified.
W Memory location is write access only.
MMR bits that are not documented are reserved. Reserved bits must not be changed by the user.
ACRONYMS AND ABBREVIATIONS
Table 3.
Acronym/Abbreviation Description
ADC Analog-to-digital converter
DMA Direct memory access
GPIO General-purpose input and output
LSB Least significant byte/bit
MMR Memory mapped register
MSB Most significant byte/bit
NMI
Nonmaskable interrupt
NVIC
Nested vectored interrupt controller
Rx Receive
SAR Successive approximation register
SOA Semiconductor optical amplifier
SPI Serial peripheral interface
SWD Sync word detect/serial wire debug
Tx Transmit
UART Universal asynchronous transmitter
WDT Watchdog timer
WUT Wake-up timer

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INTRODUCTION TO THE ADuCM310
The ADuCM310 is a triple-die stack, system on-chip designed for diagnostic control on tunable laser optical module application. The
ADuCM310 features a 16-bit (14-bit no missing codes), multichannel, successive approximation register (SAR) ADC; an ARM Cortex™-M3
processor; eight voltage DACs; six current output DACs; and Flash/EE memory packaged in a 6 mm × 6 mm, 112-ball BGA package.
The bottom die in the stack supports the bulk of the low voltage analog circuitry and is largest of the three die. It contains the ADC,
VDAC, main IDAC circuits, as well as other analog support circuits like the low drift, precision 2.5 V voltage reference source.
The middle die in the stack supports the bulk of the digital circuitry including the ARM Cortex-M3 processor, the flash and SRAM
blocks, and all of the digital communication peripherals. Also provided on this die are the clock sources for the whole chip. A 16 MHz
internal oscillator is the source of an internal phase-locked loop (PLL) that outputs an 80 MHz system clock.
The top die, which is the smallest die, is developed on a high voltage process and supports the −5 V and +5 V VDAC outputs. It also
implements the SOA IDAC current sink circuit, which allows the external SOA diode to be pulled to a −3.0 V level to implement the fast
shutdown of the laser module.
Regarding the individual blocks, the ADC is capable of operating at conversion rates of up to 800 kSPS. There are 10 external inputs to the
ADC, and these can be configured as single-ended or differential. Several internal channels are available, including supply monitor
channels, an on-chip temperature sensor, and internal voltage reference monitor.
The voltage DACs are 12-bit string DACs with output buffers capable of sourcing between 10 mA and 50 mA, and all are capable of
driving 10 nF capacitive loads.
The low drift current DACs have 14-bit resolution and have varied full-scale output ranges from 0 mA to 20 mA to 0 mA to 250 mA on
the SOA IDAC. The SOA IDAC also comes with a 0 mA to −60 mA current sink capability.
A precision 2.5 V on-chip reference source is also provided. This reference is used by the internal ADC, IDACs, and VDAC circuits,
ensuring low drift performance for all of these peripherals. Also provided are two buffered reference outputs capable of sourcing up to
1.2 mA. These can be used externally to the chip.
The ADuCM310 integrates an 80 MHz ARM Cortex-M3 processor, which is a 32-bit RISC machine, offering up to 100 DMIPS peak
performance. The ARM Cortex-M3 processor also has a flexible 14-channel DMA controller supporting communication peripherals SPI,
UART, and I2C. There are 256 kB of nonvolatile Flash/EE memory and 32 kB of SRAM integrated on-chip.
A 16 MHz on-chip oscillator generates the 80 MHz system clock. This clock can be internally divided for the processor to operate at a
lower frequency, thus saving power. A low power, internal, 32 kHz oscillator is available and can clock the timers. There are three general-
purpose timers, a wake-up timer, and a system watchdog timer.
A range of communication peripherals can be configured as required in a specific application. These peripherals include UART, two I2Cs,
two SPI serial input/output communication controllers, GPIO ports, and PWM.
On-chip factory firmware supports in-circuit serial download via the UART, while nonintrusive emulation and program download is also
supported via the serial wire interface. These features are incorporated into a low cost development system supporting this precision
analog microcontroller family.
The ADuCM310 operates from 2.9 V to 3.6 V and is specified over a temperature range of −10°C to +85°C.

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MAIN FEATURES OF THE ADuCM310
ADC
•Multichannel, 14-bit, 800 kSPS SAR ADC
•14-bit no missing codes
•Low drift, on-chip voltage reference
DACs
•Eight voltage output DACs
•VDACs are 12-bit monotonic
•Six current output DACs
•One of these can source or sink current
•Current DACs when used as current sources are 14-bit monotonic
•Low drift, on-chip 2.5 V voltage reference source
•Two buffered reference outputs
Communication
•UART
•Industry standard, 16450 UART peripheral
•Support for DMA
•Two I2Cs
•2-byte transmit and receive FIFOs for the master and slave
•Support for DMA
•Automatic clock stretching option
•Two SPIs
•Master or slave mode with separate 4-byte Rx and Tx FIFOs
•Rx and Tx DMA channels
•8-channel PWM
•Multiple GPIO pins
Processing
•ARM Cortex-M3 processor operating from an internal 80 MHz system clock
•256 kB Flash/EE memory, 32 kB SRAM
•In-circuit download and debug via serial wire
•On-chip UART download capability
On-Chip Peripherals
•Three general-purpose timers
•Wake-up timer
•Watchdog timer
•32-element programmable logic array (PLA)
Packages and Temperature Range
•6 mm × 6 mm, 112-ball BGA package: −10°C to +85°C
Tools
•Low cost development system
•Third-party compiler and emulator tool support
Applications
•Tunable laser modules

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MEMORY ORGANIZATION
The ADuCM310 memory organization is described in this section.
Features
•Cortex-M3 memory system features
•Predefined memory map
•Support for bit-band operation for atomic operations
•Unaligned data access
•ADuCM310 on-chip peripherals are accessed via memory mapped registers, situated in the bit band region.
•User memory sizes options:
•32 kB SRAM
•256 kB Flash/EE memory
There is an on-chip kernel for manufacturer data and in-circuit download.
VENDOR SPECIFIC
PRIVATE PERIPHERAL
BUS—EXTERNAL
PRIVATE PERIPHERAL
BUS—INTERNAL
EXTERNAL DEVICE 1GB
(NOT AVAILABLE IN
ADuCM310)
EXTERNAL RAM 1GB
(NOT AVAILABLE IN
ADuCM310)
PERIPHERAL 0.5GB
SRAM 0.5GB
CODE 0.5GB
0xFFFF FFFF
0xE010 0000
0xE00F FFFF
0xE004 0000
0xE003 FFFF
0xE000 0000
0xDFFF FFFF
0xA000 0000
0x9FFF FFFF
0x6000 0000
0x5FFF FFFF
0x4000 0000
0x3FFF FFFF
0x2000 0000
0x1FFF FFFF
0x0000 000
0xE000 EF00
ADuCM310 MMRs
0xE000 E000
0x400AFFFF
ADuCM310 MMRs
0x4000 0000
0x2000 7FFF
ADuCM310 32kB SRAM
0x2000 0000
0x0004 0FFF
ADuCM310
KERNELSPACE 0x0004 0000
0x0003 FFFF
ADuCM310 256kB
FLASH/EE MEMORY 0x0000 0000
11461-002
Figure 2. Cortex-M3 Memory Map Diagram

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CLOCKING ARCHITECTURE
CLOCKING ARCHITECTURE FEATURES
The ADuCM310 integrates two on-chip oscillators and circuitry for an external crystal and external clock source:
•LFOSC is a 32 kHz, low power internal oscillator that is used in low power modes.
•HFOSC is a 16 MHz internal oscillator that is used in active mode. This is the default input to the PLL.
•HFXTAL is a 16 MHz external crystal oscillator.
•External clock input (ECLKIN) is available via the GPIO pin.
CLOCKING ARCHITECTURE BLOCK DIAGRAM
HFOSC
16MHz OSC
WATCHDOG
TIMER
WAKE-UP
TIMER
TIMER0CLK
01
11
00
01
11
00
10
T4CON[9:10]
CLKCON0[1:0]
TIMER1CLK
LFOSC
(INTERNAL)
ECLKIN
P1.0
PCLK
PCLK
HCLK
PCLK
HCLK
I
2
C0
UART
D2D
SPI0
SPI1
CORE
PWM
01
11
00
10
01
11
00
10
CLKCON0[1:0]
TIMER2CLK
PCLK
HCLK
80MHz SPLL
0
1
01
00
11
HFXTAL
16MHz OSC
CLKCON0[11]
CDPCLK
(CLKCON1[10:8]) I
2
C1
FLASH
ACLK
(TO LV DIE, ADC)
CDHCLK
(CLKCON1[2:0])
CLKCON5[3]
CLKCON5[4]
CLKCON5[5]
CLKCON5[6]
CLKCON5[0]
CLKCON5[1]
PCLK
UCLK
HCLK
CDD2DCLK
(CLKCON1[11])
11461-003
÷4
T0CON[5:6]
T1CON[5:6]
T2CON[5:6]
CLKCON0[11]
Figure 3. Clocking Architecture Block Diagram

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CLOCKING ARCHITECTURE OVERVIEW
The system clock, UCLK can be selected from an 80 MHz PLL output (default). An external clock on P1.0 can also be used for test purposes.
Internally, the system clock is divided into separate clocks:
•UCLK system clock
•System bus clock (HCLK) for the flash, SRAM, and DMA
•ACLK for the analog section of the chip; this is based on the 20 MHz peripheral bus clock (PCLK) output and goes to the low voltage
analog die
•PCLK for most peripherals
All ADC performance details are based on a 20 MHz ACLK (CLKCON1[10:8] = 010b). Performance at other clock speeds is not
guaranteed; therefore, do not change CLKCON1[10:8] when the ADC is being used.
CLOCKING ARCHITECTURE OPERATION
At power-up, the processor executes at 80 MHz, sourced from the 80 MHz PLL output. The clock source for the 80 MHz PLL is the
internal 16 MHz oscillator by default. User code can select the clock source for the system clock and can divide the clock by a factor of 1
to 128, where the clock divider bits are controlled by CLKCON1[2:0]. This allows slower code execution and reduced power consumption.
Note that P1.0 must be configured first as a clock input before the clock source is switched in the clock control register.
If the clock source for the 80 MHz SPLL is required to change from the internal 16 MHz oscillator to the external HFXTAL, observe the
following procedure:
1. Check that HFXTAL is stable by reading CLKSTAT0[14:12].
2. Change the system clock to the internal 16 MHz oscillator using CLKCON0[1:0].
3. Switch the input to the SPLL using CLKCON0[11].
4. Wait until the SPLL has locked by monitoring CLKSTAT0[2:0].
5. Change the system clock back to the SPLL clock.
REGISTER SUMMARY: CLOCK ARCHITECTURE
Table 4. Clocking Register Summary
Address Name Description Reset Access
0x40028000 CLKCON0 Miscellaneous clock settings register 0x0041 RW
0x40028004 CLKCON1 Clock dividers register 0x0200 RW
0x40028014 CLKCON5 User clock gating control register 0x0040 RW
0x40028018 CLKSTAT0 Clocking status register 0x0003 RW
REGISTER DETAILS: CLOCK ARCHITECTURE
Miscellaneous Clock Settings Register
Address: 0x40028000, Reset: 0x0041, Name: CLKCON0
Table 5. Bit Descriptions for CLKCON0
Bits Bit Name Description Reset Access
15 HFXTALIE High frequency crystal interrupt enable. 0x0 RW
0: an interrupt to the core is not generated on a HFXTAL OK or HFXTAL not OK.
1: an interrupt to the core is generated on a HFXTAL OK or HFXTAL not OK.
14 UPLLIE UPLL interrupt enable. 0x0 RW
0: UPLL interrupt is not generated.
1: UPLL interrupt is generated.
13 SPLLIE SPLL interrupt enable. 0x0 RW
0: system PLL interrupt is not generated.
1: system PLL interrupt is generated.
12 RESERVED Reserved. 0x0 R
11 PLLMUX PLL source selection. 0x0 RW
0: internal oscillator is selected (HFOSC).
1: external oscillator is selected (HFXTAL).

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Bits Bit Name Description Reset Access
[10:8] RESERVED Reserved. 0x0 RW
[7:4]
CLKOUT
GPIO clock out selection.
0x4
RW
0000: UCLK.
0001: LFOSC (32 kHz).
0010: HFOSC (16 MHz).
0100: core clock (default).
0101: PCLK.
1011: General-Purpose Timer 0 clock.
1100: wake-up timer clock.
1110: HFXTAL.
All other combinations are reserved.
[3:2] RESERVED Reserved. 0x0 R
[1:0] CLKMUX Clock selection. 0x1 RW
00: high frequency internal oscillator (HFOSC).
01: SPLL is selected (80 MHz).
10: UPLL is selected (60 MHz).
11: external GPIO port is selected (ECLKIN).
Clock Dividers Register
Address: 0x40028004, Reset: 0x0200, Name: CLKCON1
Table 6. Bit Descriptions for CLKCON1
Bits Bit Name Description Reset Access
[15:11] RESERVED Reserved 0x0 R
[10:8] CDPCLK PCLK divide bits. 0x2 RW
000: Reserved.
001: Reserved.
010: DIV4. Divide by 4 (PCLK is a quarter the frequency of root clock, 20 MHz).
All ADC specifications are based on this setting. Using any other setting may
affect ADC performance.
011: DIV8. Divide by 8.
100: DIV16. Divide by 16.
101: DIV32. Divide by 32.
110: DIV64. Divide by 64.
111: DIV128. Divide by 128.
[7:3] RESERVED Reserved. Always returns 0 when read. 0x0 R
[2:0] CDHCLK HCLK divide bits. 0x0 RW
000: DIV1. Divide by 1 (HCLK is equal to root clock).
001: DIV2. Divide by 2 (HCLK is half the frequency of root clock).
010: DIV4. Divide by 4 (HCLK is quarter the frequency of root clock).
011: DIV8. Divide by 8.
100: DIV16. Divide by 16.
101: DIV32. Divide by 32.
110: DIV64. Divide by 64.
111: DIV128. Divide by 128.

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User Clock Gating Control Register
Address: 0x40028014, Reset: 0x0040, Name: CLKCON5
The user clock gating control register (CLKCON5) controls the gates of the peripheral UCLKs.
Table 7. Bit Descriptions for CLKCON5
Bits Bit Name Description Reset Access
[15:7]
RESERVED
Reserved. Always returns 0 when read.
0x0
R
6 RESERVED Reserved. Always set to 1. 0x1 RW
5 UCLKUARTOFF UART clock user control. This bit disables the UCLK UART clock. It controls the
gate on UCLK UART in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK_UART is always off and this bit has no effect.
0x0 RW
0: die-to-die clock on permanently.
1: die-to-die clock enabled only during die-to-die transfers (recommended).
4 UCLKI2C1OFF I2C1 clock user control. This bit disables the UCLK I2C1 clock. It controls the
gate on UCLK I2C1 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the I2C1 UCLK is always off and this bit has no effect.
0x0 RW
0: clock on.
1: clock off.
3 UCLKI2C0OFF I
2
C0 clock user control. This bit disables the UCLK I
2
C0 clock. It controls the
gate on UCLK I2C0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK I2C0 is always off and this bit has no effect.
0x0 RW
0: clock on.
1: clock off.
2 RESERVED Reserved. 0x0 R
1 UCLKSPI1OFF SPI1 clock user control. This bit disables the UCLK SPI1 clock. It controls the
gate on UCLK SPI1 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK SPI1 is always off and this bit has no effect.
0x0 RW
0: clock on.
1: clock off.
0 UCLKSPI0OFF SPI0 clock user control. This bit disables the UCLK SPI0 clock. It controls the
gate on UCLK SPI0 in Power Mode 0 and Power Mode 1. In Power Mode 2
and Power Mode 3, the UCLK SPI0 is always off and this bit has no effect.
0x0 RW
0: clock on.
1: clock off.

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Clocking Status Register
Address: 0x40028018, Reset: 0x0003, Name: CLKSTAT0
The clocking status register monitors PLL and oscillator status.
Table 8. Bit Descriptions for CLKSTAT0
Bits Bit Name Description Reset Access
15 RESERVED Reserved. Always returns 0 when read. 0x0 R
14 HFXTALNOK HF crystal not stable. This bit is sticky. It interrupts the core when interrupts are
enabled. Write a 1 to this location to clear it.
0x0 RW
0: HF crystal stable signal has not been deasserted.
1: HF crystal stable signal has been deasserted.
13
HFXTALOK
HF crystal stable. This bit is sticky. It interrupts the core when interrupts are
enabled. Write a 1 to this location to clear it.
0x0
RW
0: HF crystal stable signal has not been asserted.
1: HF crystal stable signal has been asserted.
12 HFXTALSTATUS HF crystal status. 0x0 R
0: HF crystal is not stable or not enabled.
1: HF crystal is stable.
[11:3] RESERVED Reserved. 0x0 R
2 SPLLUNLOCK System PLL unlock. This bit is sticky. SPLLUNLOCK is set when the PLL loses
its lock. SPLLUNLOCK is used as the interrupt source to signal the core that
a lock was lost. Writing a 1 to this bit clears it. SPLLUNLOCK does not set
again unless the system PLL gains a lock and subsequently loses it again.
0x0 RW
0: no loss of PLL lock was detected.
1: PLL loss of lock was detected.
1 SPLLLOCK System PLL lock. This bit is sticky. SPLLLOCK is set when the PLL locks.
SPLLLOCK is used as the interrupt source to signal the core that a lock was
detected. Writing a 1 to this bit clears it. SPLLLOCK does not set again
unless the system PLL loses lock and subsequently locks again.
0x1 RW
0: no PLL lock event was detected.
1: PLL lock event was detected.
0 SPLLSTATUS System PLL status. Indicates the current status of the PLL. Initially, the system
PLL is unlocked. After a stabilization period, the PLL locks and is ready for
use as the system clock source. This is a read only bit. A write has no effect.
0x1 R
0: the PLL is not locked or not properly configured. The PLL is not ready for
use as the system clock source.
1: the PLL is locked and is ready for use as the system clock source.

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 14 of 192
POWER MANAGEMENT UNIT
POWER MANAGEMENT UNIT FEATURES
The power management unit (PMU) controls the different power modes of the ADuCM310.
The following four power modes are available:
•Active
•CORE_SLEEP
•SYS_SLEEP
•Hibernate
POWER MANAGEMENT UNIT OVERVIEW
The Cortex-M3 sleep modes are linked to the PMU modes and are described in this section. The PMU is in the always-on section. Each
mode provides a power reduction benefit with a corresponding reduction in functionality.
POWER MANAGEMENT UNIT OPERATION
The debug tools can prevent the Cortex-M3 from fully entering its power saving modes by setting bits in the debug logic. Only a power-on reset
resets the debug logic. Therefore, the device must be power cycled after using serial wire debug with application code containing the WFI
instruction.
Power Mode: Active Mode, Mode 0
The system is fully active. Memories and all user enabled peripherals are clocked, and the Cortex-M3 processor is executing instructions.
Note that the Cortex-M3 processor manages the internal clocks and can be in a partial clock gated state. This clock gating affects only the
internal Cortex-M3 processing core. Automatic clock gating is used on all blocks. User code can use a WFI command to put the Cortex-
M3 processor into sleep mode; it is independent of the power mode settings of the PMU.
When the ADuCM310 wakes up from any of the low power modes, the device returns to Mode 0.
Power Mode: CORE_SLEEP Mode, Mode 1
In CORE_SLEEP mode, the system gates the clock to the Cortex-M3 core after the Cortex-M3 has entered sleep mode. The rest of the
system remains active. No instructions can be executed; however, DMA transfers can continue to occur between peripherals and
memories. The Cortex-M3 processor FCLK is active, and the device wakes up using the NVIC.
Power Mode: SYS_SLEEP Mode, Mode 2
In SYS_SLEEP mode, the system gates HCLK and PCLK after the Cortex-M3 has entered sleep mode. The gating of these clocks stops all
AHB attached masters/slaves and all peripherals attached to APB. Peripheral clocks are all off, and they are no longer user programmable.
The NVIC clock (FCLK) remains active, and the NVIC processes wake-up events.
Power Mode: Hibernate Mode, Mode 3
In hibernate mode, the system disables power to all combinational logic and places sequential logic in retain mode. Because FCLK is
stopped, the number of sources capable of waking up the system is restricted. The sources listed in Table 64 are the only sources able to
wake up the system.
Enter Power Mode 1 to Power Mode 3 when the processor is not in an interrupt handler. If Power Mode 1 to Power Mode 3 is entered
when the processor is in an interrupt handler, the power-down mode can be exited only by a reset or a higher priority interrupt source.

ADuCM310 Hardware Reference Manual UG-549
Rev. C | Page 15 of 192
CODE EXAMPLES
Code Example to Enter Power Saving Modes
SCB->SCR = 0x04; // sleepdeep mode
pADI_PWRCTL->PWRKEY = 0x4859; // key1
pADI_PWRCTL->PWRKEY = 0xF27B; // key2
pADI_PWRCTL->PWRMOD = 0x3; // Hibernate
__DSB();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
__WFI();
__nop();
__nop();
__nop();
__nop();
__nop();
__nop();
Code Example to Achieve Further Power Savings
pADI_ADC->ADCCON = 0; // Power off the ADC
pADI_IDAC0->IDACCON = 0x1; // Turn off IDAC0
pADI_IDAC1->IDACCON = 0x1; // Turn off IDAC1
pADI_IDAC2->IDACCON = 0x1; // Turn off IDAC2
pADI_IDAC3->IDACCON = 0x1; // Turn off IDAC3
pADI_VDAC0->DACCON = 0x100; // Turn off VDAC0
pADI_VDAC1->DACCON = 0x100; // Turn off VDAC1
pADI_VDAC2->DACCON = 0x100; // Turn off VDAC2
pADI_VDAC3->DACCON = 0x100; // Turn off VDAC3
pADI_VDAC4->DACCON = 0x100; // Turn off VDAC4
pADI_VDAC5->DACCON = 0x100; // Turn off VDAC5
pADI_VDAC6->DACCON = 0x100; // Turn off VDAC6
pADI_VDAC7->DACCON = 0x100; // Turn off VDAC7
pADI_CLKCTL->CLKCON0 &= 0xFFFC; // Switch to 16MHz clock
pADI_CLKCTL->CLKCON1 = 0x505; // Slow down system clocks
pADI_CLKCTL->CLKCON5 = 0x7B; // Turn off clocks to peripherals

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 16 of 192
REGISTER SUMMARY: POWER MANAGEMENT UNIT
Table 9. Power Management Register Summary
Address Name Description Reset Access
0x40002400
PWRMOD
Power modes
0x0000
RW
0x40002404 PWRKEY Key protection for PWRMOD 0x0000 RW
REGISTER DETAILS: POWER MANAGEMENT UNIT
Power Modes Register
Address: 0x40002400, Reset: 0x0000, Name: PWRMOD
Table 10. Bit Descriptions for PWRMOD
Bits Bit Name Description Reset Access
[14:2] RESERVED Reserved. These bits must be written 0 by user code. 0x0 R
[1:0] PWRMOD Power modes control bits. When read, these bits contain the last power
mode value entered by user code. Note that, to place the Cortex in
SLEEPDEEP mode for hibernate, the Cortex-M3 system control register
(Register 0xE000ED10) must be configured to 0x4 or 0x06.
0x0 RW
00: active mode.
01: CORE_SLEEP mode.
10: SYS_SLEEP mode.
11: hibernate mode.
Key Protection for PWRMOD Register
Address: 0x40002404, Reset: 0x0000, Name: PWRKEY
Table 11. Bit Descriptions for PWRKEY
Bits Bit Name Description Reset Access
[15:0] PWRKEY Power control key register. The PWRMOD register is key-protected. Two
writes to the key are necessary to change the value in the PWRMOD register:
first 0x4859, then 0xF27B. The PWRMOD register must then be written. A
write to any other register before writing to PWRMOD returns the protection
to the lock state.
0x0 RW

ADuCM310 Hardware Reference Manual UG-549
Rev. C | Page 17 of 192
ARM CORTEX-M3 PROCESSOR
ARM CORTEX-M3 PROCESSOR FEATURES
High Performance
•1.25 DMIPS/MHz.
•Many instructions, including multiply, are single cycle.
•Separate data and instruction buses allow simultaneous data and instruction accesses to be performed.
•Optimized for single-cycle flash usage.
Low Power
•Low standby current.
•Core implemented using advanced clock gating so that only the actively used logic consumes dynamic power.
•Power-saving mode support (sleep and deep sleep modes). The design has separate clocks to allow unused parts of the processor to
be stopped.
Advanced Interrupt Handling
•The nested vectored interrupt controller (NVIC) supports up to 240 interrupts, of which the ADuCM310 supports 50. The vectored
interrupt feature greatly reduces interrupt latency because there is no need for software to determine which interrupt handler to
serve. In addition, there is no need to have software to set up nested interrupt support.
•The ARM Cortex-M3 processor automatically pushes registers onto the stack at the entry interrupt and retrieves them at the exit
interrupt. This reduces interrupt handling latency and allows interrupt handlers to be normal C functions.
•Dynamic priority control for each interrupt.
•Latency reduction using late arrival interrupt acceptance and tail-chain interrupt entry.
•Immediate execution of a nonmaskable interrupt request for safety-critical applications.
System Features
•Support for bit-band operation and unaligned data access.
•Advanced fault handling features include various exception types and fault status registers.
Debug Support
•Serial wire debug interfaces (SW-DP).
•Flash patch and breakpoint (FPB) unit for implementing breakpoints. Limited to two hardware breakpoints.
•Data watchpoint and trigger (DWT) unit for implementing watchpoints trigger resources and system profiling. Limited to one
hardware watchpoint. The DWT does not support data matching for watchpoint generation because it only has one comparator.

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 18 of 192
ARM CORTEX-M3 PROCESSOR OVERVIEW
The ADuCM310 contains an embedded ARM Cortex-M3 processor, Revision r2p1. The ARM Cortex-M3 processor provides a high
performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low
power consumption while delivering outstanding computational performance and exceptional system response to interrupts.
ARM CORTEX-M3 PROCESSOR OPERATION
Several ARM Cortex-M3 processor components are flexible in their implementation. This section details the actual implementation of
these components in the ADuCM310.
Serial Wire Debug (SW/JTAG-DP)
The ADuCM310 only supports the serial wire interface via the SWCLK and SWDIO pins. It does not support the 5-wire JTAG interface.
ROM Table
The ADuCM310 implements the default ROM table.
Nested Vectored Interrupt Controller Interrupts (NVIC)
The ARM Cortex-M3 processor includes an NVIC, which offers several features:
•Nested interrupt support
•Vectored interrupt support
•Dynamic priority changes support
•Interrupt masking
In addition, the NVIC has a nonmaskable interrupt (NMI) input.
The NVIC is implemented on the ADuCM310, and more details are available in the System Exceptions and Peripheral Interrupts section.
Wake-Up Interrupt Controller (WIC)
The ADuCM310 has a modified WIC, which provides the lowest possible power-down current. More details are available in the Power
Management Unit section. It is not recommended to enter a power saving mode while servicing an interrupt. However, if the device does
enter a power saving mode while servicing an interrupt, it can be woken up only by a higher priority interrupt source.
µDMA
The ADuCM310 implements the ARM µDMA. More details are available in the DMA Controller section.
ARM CORTEX-M3 PROCESSOR RELATED DOCUMENTS
•Cortex-M3 Revision r2p1 Technical Reference Manual (DDI0337)
•ARM Processor Cortex-M3 (AT420) and Cortex-M3 with ETM (AT425): Errata Notice
•ARMv7-M Architecture Reference Manual (DDI0403)
•ARMv7-M Architecture Reference Manual Errata Markup
•ARM Debug Interface v5 Architecture Specification (IHI 0031)
•PrimeCell® µDMA Controller (PL230) Technical Reference Manual Revision r0p0 (DDI0417)

ADuCM310 Hardware Reference Manual UG-549
Rev. C | Page 19 of 192
ADC CIRCUIT
ADC CIRCUIT FEATURES
The ADuCM310 incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit no missing codes.
The flexible input multiplexer supports 10 external inputs and 14 internal channels. The internal channels include the following:
•Temperature sensor channel
•Internal 2.505 V reference
•External reference
•BUF_BREF2.5A and BUF_BREF2.5B
•Six IDAC channels. These are the voltage at each of the IDAC output pins
•PVDD_IDAC2 supply voltage
•IOVDD/2 supply voltage.
•AVDD/2 supply voltage
The input buffer can be selected for any channel to allow very low input current/input leakage specifications on these input channels. It is
recommended to use the input buffer for the AVDD/2, IOVDD/2, and temperature sensor channels.
The ADC features a high precision, low drift internal 2.505 V reference source.
An external reference can also be connected to the ADC_CAPP and ADC_CAPN pins.
The programmable ADC update rate is from 19.55 kSPS to 800 kSPS.
There is an internal digital comparator for the AIN4 channel. An interrupt can be generated if the digital comparator detects an ADC
result above/below a user defined threshold.
Each channel has its own distinct data register for its conversion result. For example, when AIN0 is selected, the result appears in
ADCDAT0; if AIN7 is selected, the result appears in ADCDAT7. For a differential measurement, the result always appears in the data
register of the positive channel.
ADC CIRCUIT BLOCK DIAGRAM
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
CC2C65,536C 4C131,072C
LSB SW+
MSB
LSB SW– MSB
CC2C65,536C 4C131,072C
AIN+
V
REF
AGND
AIN–
11461-004
Figure 4. ADC Circuit Block Diagram
ADC CIRCUIT OVERVIEW
The ADuCM310 incorporates a fast, multichannel, 16-bit ADC. The ADC is specified to be 14-bit no missing codes. The ADC can
operate from a 2.9 V to 3.6 V supply and is capable of providing a throughput of up to 800 kSPS. This ADC block provides the user with a
multichannel multiplexer, input buffer for high impedance input channels, on-chip reference, and SAR ADC.
The SAR ADC circuit is implemented on the low voltage analog die. The ARM Cortex-M3 processor interfaces to the ADC via an
internal parallel die-to-die interface.
Depending on the input signal configuration, the ADC can operate in one of the following two modes:
•Differential mode, to measure the difference between two signals.
•Single-ended mode, to measure any signal relative to AGND.
The converter accepts an analog input range of 0 to VREF when operating in single-ended mode. In fully differential mode, the
measurement range is ±VREF while each signal must be between the range of AGND to AVDD.

UG-549 ADuCM310 Hardware Reference Manual
Rev. C | Page 20 of 192
0
AV
DD
FS (V
REF
)
–FS (–V
REF
)
AIN+
AIN–
OUTPUT CODE
11461-005
Figure 5. Examples of Balanced Signals for Differential Mode
A high precision, low drift, factory-calibrated 2.505 V reference is provided on-chip. An external reference can also be connected to the
ADC_CAPP and ADC_CAPN pins.
Single or continuous conversion modes can be initiated in software. An external pin (alternate function of P2.4) can also generate a
repetitive trigger for ADC conversions.
ADC CIRCUIT OPERATION
The SAR ADC is based on a charge redistribution DAC. The capacitive DAC consists of two identical arrays of 18 binary weighted
capacitors that are connected to the two inputs of the comparator.
The ADC converts the voltage applied to the positive analog inputs (AIN+) and negative analog inputs (AIN−) in the following three steps:
1. Precharge Phase: during this phase, the precharge buffers connect the inputs to the capacitor arrays. This charges the capacitors
quickly with minimal loading of the external input source.
2. Acquisition Phase: during the acquisition phase, the capacitor arrays are connected directly to the inputs to fully charge the capacitor
arrays and eliminate any precharge buffer errors. The timing for the acquisition phase is set by ADCCNVC[25:16]; set this value to
1 µs for ADC update rates ≤500 kSPS (for example, ADCCNVC = 0x140028 for 500 kSPS). If the input buffer is not used when
measuring AVDD/2, IOVDD/2, or temperature sensor channels, set this value to 1.5 µs.
3. Conversion Phase: at the end of the acquisition phase, the internal CNV signal goes high and initiates the conversion phase. The
conversion begins with the SW+ and SW− switches being opened. This disconnects the two capacitor arrays from the analog inputs
and connects the analog inputs to AGND (−VREF). The conversion is completed by normal successive approximation.
The ADC block operates from an internally generated 20 MHz clock.
The ADC conversion rate is set by ADCCNVC[9:0].
ADC TRANSFER FUNCTION
Single-Ended Mode
In single-ended mode, the input range is 0 to VREF. The output coding is straight binary with 1 LSB = FS/65,536 or VREF/65,536 =
2.5 V/65,536 = 38.14 µV.
The data values in ADCDATx are aligned such that the MSB is in ADCDATx[27] and, therefore, the LSB is in ADCDATx[12].
The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, …, FS − 3/2 LSBs). The
ideal input/output transfer characteristic is shown in Figure 6.