Analog devices Ad9865 User manual

Broadband Modem Mixed-Signal Front End

AD9865

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

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registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Low cost 3.3 V CMOS MxFETM for broadband modems

10-bit D/A converter

2×/4× interpolation filter

200 MSPS DAC update rate

Integrated 23 dBm line driver with 19.5 dB gain control

10-bit, 80 MSPS A/D converter

−12 dB to +48 dB low noise RxPGA (< 3.0 nV/rtHz)

Third order, programmable low-pass filter

Flexible digital data path interface

Half- and full-duplex operation

Backward-compatible with AD9975 and AD9875

Various power-down/reduction modes

Internal clock multiplier (PLL)

2 auxiliary programmable clock outputs

Available in 64-lead chip scale package or bare die

APPLICATIONS

Powerline networking

VDSL and HPNA

FUNCTIONAL BLOCK DIAGRAM

10

XTAL

RX–

4

6

AD9865

10

0 TO –7.5dB

04493-0-001

0 TO –12dB

REGISTER

CONTROL

CLK

SYN.

ADC

80MSPS

2-4X IOUT_G+

IOUT_N+

IOUT_N–

IOUT_G–

CLKOUT_1

CLKOUT_2

OSCIN

RX+

IAMP

TxDAC

IOUT_P+

IOUT_P–

2

M

CLK

MULTIPLIER

2-POLE

LPF 1-POLE

LPF

0 TO 6dB

∆= 1dB – 6 TO 18dB

∆= 6dB –6 TO 24dB

∆= 6dB

SPI

AGC[5:0]

RXCLK

RXE/SYNC

ADIO[9:4]/

Tx[5:0]

ADIO[3:0]/

Rx[5:0]

TXCLK

T

XEN/SYNC

MODE

PWR DWN

Figure 1.

GENERAL DESCRIPTION

The AD9865 is a mixed-signal front end (MxFE) IC for

transceiver applications requiring Tx and Rx path functionality

with data rates up to 80 MSPS. Its flexible digital interface,

power saving modes, and high Tx-to-Rx isolation make it well

suited for half- and full-duplex applications. The digital inter-

face is extremely flexible allowing simple interfaces to digital

back ends that support half- or full-duplex data transfers, thus

often allowing the AD9865 to replace discrete ADC and DAC

solutions. Power saving modes include the ability to reduce

power consumption of individual functional blocks, or to power

down unused blocks in half-duplex applications. A serial port

interface (SPI®) allows software programming of the various

functional blocks. An on-chip PLL clock multiplier and

synthesizer provide all the required internal clocks, as well as

two external clocks from a single crystal or clock source.

The Tx signal path consists of a bypassable 2×/4× low-pass

interpolation filter, a 10-bit TxDAC, and a line driver. The

transmit path signal bandwidth can be as high as 34 MHz at an

input data rate of 80 MSPS. The TxDAC provides differential

current outputs that can be steered directly to an external load

or to an internal low distortion current amplifier. The current

amplifier (IAMP) can be configured as a current- or voltage-

mode line driver (with two external npn transistors) capable of

delivering in excess of 23 dBm peak signal power. Tx power can

be digitally controlled over a 19.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier

(RxPGA), a tunable low-pass filter (LPF), and a 10-bit ADC.

The low noise RxPGA has a programmable gain range of

−12 dB to +48 dB in 1 dB steps. Its input referred noise is less

than 3 nV/rtHz for gain settings beyond 36 dB. The receive path

LPF cutoff frequency can be set over a 15 MHz to 35 MHz

range or simply bypassed. The 10-bit ADC achieves excellent

dynamic performance over a 5 MSPS to 80 MSPS span. Both

the RxPGA and the ADC offer scalable power consumption

allowing power/performance optimization.

The AD9865 provides a highly integrated solution for many

broadband modems. It is available in a space saving 64-pin chip

scale package and is specified over the commercial (−40°C to

+85°C) temperature range.

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AD9865

Rev. A | Page 2 of 48

TABLE OF CONTENTS

Specifications..................................................................................... 3

Tx Path Specifications.................................................................. 3

Rx Path Specifications.................................................................. 4

Power Supply Specifications ....................................................... 5

Digital Specifications ................................................................... 6

Serial Port Timing Specifications............................................... 7

Half-Duplex Data Interface (ADIO Port) Timing

Specifications ................................................................................ 7

Full-Duplex Data Interface (Tx and Rx Port) Timing

Specifications ................................................................................ 8

Explanation of Test Levels........................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Rx Path Typical Performance Characteristics ........................ 12

TxDAC Path Typical Performance Characteristics ............... 16

IAMP Path Typical Performance Characteristics .................. 18

Serial Port ........................................................................................ 19

Register Map Description ......................................................... 21

Serial Port Interface (SPI) ......................................................... 21

Digital Interface .............................................................................. 23

Half-Duplex Mode ..................................................................... 23

Full-Duplex Mode ...................................................................... 24

RxPGA Control .......................................................................... 25

TxPGA Control .......................................................................... 27

Transmit Path .................................................................................. 28

Digital Interpolation Filters ...................................................... 28

TxDAC and IAMP Architecture .............................................. 28

Tx Programmable Gain Control.............................................. 30

TxDAC Output Operation........................................................ 30

IAMP Current-Mode Operation.............................................. 30

IAMP Voltage-Mode Operation .............................................. 31

IAMP Current Consumption Considerations........................ 32

Receive Path .................................................................................... 33

Rx Programmable Gain Amplifier........................................... 33

Low-Pass Filter ........................................................................... 34

Analog-to-Digital Converter (ADC)....................................... 35

AGC Timing Considerations.................................................... 36

Clock Synthesizer ........................................................................... 37

Power Control and Dissipation .................................................... 39

Power-Down ............................................................................... 39

Half-Duplex Power Savings ...................................................... 39

Power Reduction Options ......................................................... 40

Power Dissipation ...................................................................... 42

Mode Select upon Power-Up and Reset.................................. 42

Analog and Digital Loop-Back Test Modes............................ 43

PCB Design Considerations.......................................................... 44

Component Placement.............................................................. 44

Power Planes and Decoupling.................................................. 44

Ground Planes ............................................................................ 44

Signal Routing ............................................................................ 44

Evaluation Board ............................................................................ 46

Outline Dimensions ....................................................................... 47

Ordering Guide .......................................................................... 47

REVISION HISTORY

11/04—Data Sheet Changed from Rev. 0 to Rev. A

Changes to Specifications Tables.................................................... 3

Changes to Serial Table.................................................................. 19

Changes to Full Duplex Mode section......................................... 24

Change to TxDAC and IAMP Architecture section .................. 29

Change to TxDAC Output Operation section............................ 30

Insert equation................................................................................ 37

Change to Figure 84 caption ......................................................... 42

11/03—Revision 0: Initial Version

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AD9865

Rev. A | Page 3 of 48

SPECIFICATIONS

Tx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; fOSCIN = 50 MHz, fDAC = 200 MHz, RSET = 2.0 kΩ, unless otherwise

noted.

Table 1.

Parameter Temp Test Level Min Typ Max Unit

TxDAC DC CHARACTERISTICS

Resolution Full 10 Bits

Update Rate Full II 200 MSPS

Full-Scale Output Current (IOUTP_FS) Full IV 2 25 mA

Gain Error125°C I ±2 % FS

Offset Error 25°C V 2 µA

Voltage Compliance Range Full −1 +1.5 V

TxDAC GAIN CONTROL CHARACTERISTICS

Minimum Gain 25°C V −7.5 dB

Maximum Gain 25°C V 0 dB

Gain Step Size 25°C V 0.5 dB

Gain Step Accuracy 25°C IV Monotonic

Gain Range Error 25°C V ±2 dB

TxDAC AC CHARACTERISTICS2

Fundamental 0.5 dBm

Signal-to-Noise and Distortion (SINAD) Full IV 62.0 63.1 dBc

Signal-to-Noise Ratio (SNR) Full IV 62.5 63.2 dBc

Total Harmonic Distortion (THD) Full IV −77.7 −67.0 dBc

Spurious-Free Dynamic Range (SFDR) Full IV 67.1 79.3 dBc

IAMP DC CHARACTERISTICS

IOUTN Full-Scale Current = IOUTN+ + IOUTN− Full IV 2 105 mA

IOUTG Full-Scale Current = IOUTG+ + IOUTG− Full IV 2 150 mA

AC Voltage Compliance Range Full IV 1 7 V

IAMPN AC CHARACTERISTICS3

Fundamental 25°C 13 dBm

IOUTN SFDR (Third Harmonic) Full IV 43.3 45.2 dBc

IAMP GAIN CONTROL CHARACTERISTICS

Minimum Gain 25°C V −19.5 dB

Maximum Gain 25°C V 0 dB

Gain Step Size 25°C V 0.5 dB

Gain Step Accuracy 25°C IV Monotonic dB

IOUTN Gain Range Error 25°C V 0.5 dB

REFERENCE

Internal Reference Voltage425°C I 1.23 V

Reference Error Full V 0.7 3.4 %

Reference Drift Full V 30 ppm/oC

Tx DIGITAL FILTER CHARACTERISTICS (2× Interpolation)

Latency (Relative to 1/fDAC) Full V 43 Cycles

−0.2 dB Bandwidth Full V 0.2187 fOUT/fDAC

−3 dB Bandwidth Full V 0.2405 fOUT /fDAC

Stop-Band Rejection (0.289 fDAC to 0.711 fDAC) Full V 50 dB

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AD9865

Rev. A | Page 4 of 48

Parameter Temp Test Level Min Typ Max Unit

Tx DIGITAL FILTER CHARACTERISTICS (4× Interpolation)

Latency (Relative to 1/ FDAC) Full V 96 Cycles

−0.2 dB Bandwidth Full V 0.1095 fOUT/fDAC

−3 dB Bandwidth Full V 0.1202 fOUT /fDAC

Stop Band Rejection (0.289 fOSCIN to 0.711 fOSCIN) Full V 50 dB

PLL CLK MULTIPLIER

OSCIN Frequency Range Full IV 5 80 MHz

Internal VCO Frequency Range Full IV 20 200 MHz

Duty Cycle Full II 40 60 %

OSCIN Impedance 25°C V 100//3 ΜΩ/pF

CLKOUT1 Jitter525°C III 12 ps rms

CLKOUT2 Jitter625°C III 6 ps rms

CLKOUT1 and CLKOUT2 Duty Cycle7Full III 45 55 %

1Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1.23 V external reference and a 1 V p-p differential analog input).

2TxDAC IOUTFS = 20 mA, differential output with 1:1 transformer with source and load termination of 50 Ω, FOUT = 5 MHz, 4x interpolation.

3IOUN full-scale current = 80 mA, fOSCIN = 80 MHz, fDAC =160 MHz, 2x interpolation.

4Use external amplifier to drive additional load.

5Internal VCO operates at 200 MHz , set to divide-by-1.

6Because CLKOUT2 is a divided down version of OSCIN, its jitter is typically equal to OSCIN.

7CLKOUT2 is an inverted replica of OSCIN, if set to divide-by-1.

Rx PATH SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; half- or full-duplex operation with CONFIG = 0 default power bias

settings, unless otherwise noted.

Table 2.

Parameter Temp Test Level Min Typ Max Unit

Rx INPUT CHARACTERISTICS

Input Voltage Span (RxPGA Gain = −10 dB) Full III 6.33 V p-p

Input Voltage Span (RxPGA Gain = +48 dB) Full III 8 mV p-p

Input Common-Mode Voltage 25°C III 1.3 V

Differential Input Impedance 25°C III 400

4.0

Ω

pF

Input Bandwidth (with RxLPF Disabled, RxPGA = 0 dB) 25°C III 53 MHz

Input Voltage Noise Density (RxPGA Gain = 36 dB, f−3 dBF = 26 MHz) 25°C III 3.0 nV/rtHz

Input Voltage Noise Density (RxPGA Gain = 48 dB, f−3 dBF = 26 MHz) 25°C III 2.4 nV/rtHz

RxPGA CHARACTERISTICS

Minimum Gain 25°C III −12 dB

Maximum Gain 25°C III 48 dB

Gain Step Size 25°C III 1 dB

Gain Step Accuracy 25°C III Monotonic dB

Gain Range Error 25°C III 0.5 dB

RxLPF CHARACTERISTICS

Cutoff Frequency (f−3 dBF ) Range Full III 15 35 MHz

Attenuation at 55.2 MHz with f−3 dBF = 21 MHz 25°C III 20 dB

Pass-Band Ripple 25°C III ±1 dB

Settling Time to 5 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 20 ns

Settling Time to 60 dB RxPGA Gain Step @ fADC = 50 MSPS 25°C III 100 ns

ADC DC CHARACTERISTICS

Resolution NA NA 10 Bits

Conversion Rate Full II 5 80 MSPS

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AD9865

Rev. A | Page 5 of 48

Parameter Temp Test Level Min Typ Max Unit

Rx PATH LATENCY1

Full-Duplex Interface Full V 10.5 Cycles

Half-Duplex Interface Full V 10.0 Cycles

Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 50 MSPS2

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise and Distortion (SNR) 25°C III 43.7 dBc

Total Harmonic Distortion (THD) 25°C III −71 dBc

RxPGA Gain = 24 dB (Full-Scale =126 mV p-p)

Signal-to-Noise (SNR) 25°C III 59 dBc

Total Harmonic Distortion (THD) 25°C III −67.2 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise and Distortion (SINAD) Full IV 58 59 dBc

Total Harmonic Distortion (THD) Full IV −66 −62.9 dBc

Rx PATH COMPOSITE AC PERFORMANCE @ fADC = 80 MSPS3

RxPGA Gain = 48 dB (Full-Scale = 8.0 mV p-p)

Signal-to-Noise (SNR) 25°C III 41.8 dBc

Total Harmonic Distortion (THD) 25°C III −67 dBc

RxPGA Gain = 24 dB (Full-Scale = 126 mV p-p)

Signal-to-Noise (SNR) 25°C III 58.6 dBc

Total Harmonic Distortion (THD) 25°C III −62.9 dBc

RxPGA Gain = 0 dB (Full-Scale = 2.0 V p-p)

Signal-to-Noise (SNR) 25°C II 58.9 59.6 dBc

Total Harmonic Distortion (THD) 25°C II −69.7 −59.8 dBc

Rx-to-Tx PATH FULL-DUPLEX ISOLATION

(1 V p-p, 10 MHz Sine Wave Tx Output)

RxPGA Gain = 40 dB

IOUTP± Pins to RX± Pins 25°C III 83 dBc

IOUTG± Pins to RX± Pins 25°C III 37 dBc

RxPGA Gain = 0 dB

IOUTP± Pins to RX± Pins 25°C III 123 dBc

IOUTG± Pins to RX± Pins 25°C III 77 dBc

1Includes RxPGA, ADC pipeline, and ADIO bus delay relative to fADC.

2fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 15.5 MHz with Reg. 0x08 = 0x80.

3fIN = 5 MHz, AIN = −1.0 dBFS , LPF cutoff frequency set to 26 MHz with Reg. 0x08 = 0x80.

POWER SUPPLY SPECIFICATIONS

AVDD = 3.3 V, DVDD = CLKVDD = DRVDD = 3.3 V; RSET = 2 kΩ, full-duplex operation with fDATA = 80 MSPS,1unless otherwise noted.

Table 3.

Parameter Temp Test Level Min Typ Max Unit

SUPPLY VOLTAGES

AVDD Full V 3.135 3.3 3.465 V

CLKVDD Full V 3.0 3.3 3.6 V

DVDD Full V 3.0 3.3 3.6 V

DRVDD Full V 3.0 3.3 3.6 V

IS_TOTAL (Total Supply Current) Full II 406 475 mA

POWER CONSUMPTION

IAVDD + ICLKVDD (Analog Supply Current) IV 311 342 mA

IDVDD + IDRVDD (Digital Supply Current) Full IV 95 133 mA

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AD9865

Rev. A | Page 6 of 48

Parameter Temp Test Level Min Typ Max Unit

POWER CONSUMPTION (Half-Duplex Operation with fDATA = 50 MSPS)2

Tx Mode

IAVDD + ICLKVDD 25°C IV 112 130 mA

IDVDD + IDRVDD 25°C IV 46 49.5 mA

Rx Mode

IAVDD + ICLKVDD 25°C IV 225 253 mA

IDVDD + IDRVDD 25°C IV 36.5 39 mA

POWER CONSUMPTION OF FUNCTIONAL BLOCKS1(IAVDD + ICLKVDD)

RxPGA and LPF 25°C III 87 mA

ADC 25°C III 108 mA

TxDAC 25°C III 38 mA

IAMP (Programmable) 25°C III 10 120 mA

Reference 25°C III 170 mA

CLK PLL and Synthesizer 25°C III 107 mA

MAXIMUM ALLOWABLE POWER DISSIPATION Full IV 1.66 W

STANDBY POWER CONSUMPTION

IS_TOTAL (Total Supply Current) Full 13 mA

POWER DOWN DELAY (USING PWR_DWN PIN)

RxPGA and LPF 25°C III 440 ns

ADC 25°C III 12 ns

TxDAC 25°C III 20 ns

IAMP 25°C III 20 ns

CLK PLL and synthesizer 25°C III 27 ns

POWER UP DELAY (USING PWR_DWN PIN)

RxPGA and LPF 25°C III 7.8 µs

ADC 25°C III 88 ns

TxDAC 25°C III 13 µs

IAMP 25°C III 20 ns

CLK PLL and Synthesizer 25°C III 20 µs

1Default power-up settings for MODE = HIGH and CONFIG = LOW, IOUTP_FS = 20 mA, does not include IAMP’s current consumption, which is application dependent.

2Default power-up settings for MODE = LOW and CONFIG = LOW.

DIGITAL SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%; RSET = 2 kΩ, unless otherwise noted.

Table 4.

Parameter Temp Test Level Min Typ Max Unit

CMOS LOGIC INPUTS

High Level Input Voltage Full VI DRVDD – 0.7 V

Low Level Input Voltage Full VI 0.4 V

Input Leakage Current 12 µA

Input Capacitance Full VI 3 pF

CMOS LOGIC OUTPUTS (CLOAD = 5 pF)

High Level Output Voltage (IOH = 1 mA) Full VI DRVDD – 0.7 V

Low Level Output Voltage (IOH = 1 mA) Full VI 0.4 V

Output Rise/Fall Time (High Strength Mode and CLOAD = 15 pF) Full VI 1.5/2.3 ns

Output Rise/Fall Time (Low Strength Mode and CLOAD = 15 pF) Full VI 1.9/2.7 ns

Output Rise/Fall Time (High Strength Mode and CLOAD = 5 pF) Full VI 0.7/0.7 ns

Output Rise/Fall Time (Low Strength Mode and CLOAD = 5 pF) Full VI 1.0/1.0 ns

RESET

Minimum Low Pulse Width (Relative to fADC) 1

Clock

cycles

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AD9865

Rev. A | Page 7 of 48

SERIAL PORT TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 5.

Parameter Temp Test Level Min Typ Max Unit

WRITE OPERATION (See Figure 46)

SCLK Clock Rate (fSCLK)Full IV 32 MHz

SCLK Clock High (tHI)Full IV 14 ns

SCLK Clock Low (tLOW)Full IV 14 ns

SDIO to SCLK Setup Time (tDS)Full IV 14 ns

SCLK to SDIO Hold Time (tDH)Full IV 0 ns

SEN to SCLK Setup Time (tS)Full IV 14 ns

SCLK to SEN Hold Time (tH)Full IV 0 ns

READ OPERATION (See Figure 47 and Figure 48)

SCLK Clock Rate (fSCLK)Full IV 32 MHz

SCLK Clock High (tHI)Full IV 14 ns

SCLK Clock Low (tLOW)Full IV 14 ns

SDIO to SCLK Setup Time (tDS)Full IV 14 ns

SCLK to SDIO Hold Time (tDH)Full IV 0 ns

SCLK to SDIO (or SDO) Data Valid Time (tDV)Full IV 14 ns

SEN to SDIO Output Valid to Hi-Z (tEZ)Full IV 2 ns

HALF-DUPLEX DATA INTERFACE (ADIO PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 6.

Parameter Temp Test Level Min Typ Max Unit

READ OPERATION1 (See Figure 50)

Output Data Rate Full II 5 80 MSPS

Three-State Output Enable Time (tPZL)Full II 3 ns

Three-State Output Disable Time (tPLZ)Full II 3

ns

Rx Data Valid Time (tVT)Full II 1.5 ns

Rx Data Output Delay (tOD)Full II 4 ns

WRITE OPERATION (See Figure 49)

Input Data Rate (1× Interpolation) Full II 20 80 MSPS

Input Data Rate (2× Interpolation) Full II 10 80 MSPS

Input Data Rate (4× Interpolation) Full II 5 50 MSPS

Tx Data Setup Time (tDS)Full II 1 ns

Tx Data Hold Time (tDH)Full II 2.5 ns

Latch Enable Time (tEN)Full II 3 ns

Latch Disable Time (tDIS)Full II 3 ns

1CLOAD = 5 pF for digital data outputs.

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AD9865

Rev. A | Page 8 of 48

FULL-DUPLEX DATA INTERFACE (Tx AND Rx PORT) TIMING SPECIFICATIONS

AVDD = 3.3 V ± 5%, DVDD = CLKVDD = DRVDD = 3.3 V ± 10%, unless otherwise noted.

Table 7.

Parameter Temp Test Level Min Typ Max Unit

Tx PATH INTERFACE (See Figure 53)

Input Nibble Rate (2× Interpolation) Full II 20 160 MSPS

Input Nibble Rate (4× Interpolation) Full II 10 100 MSPS

Tx Data Setup Time (tDS)Full II 2.5 ns

Tx Data Hold Time (tDH)Full II 1.5 ns

Rx PATH INTERFACE1(See Figure 54)

Output Nibble Rate Full II 10 160 MSPS

Rx Data Valid Time (tDV)Full II 3 ns

Rx Data Hold Time (tDH)Full II 0 ns

1CLOAD =5 pF for digital data outputs.

EXPLANATION OF TEST LEVELS

I 100% production tested.

II 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures.

III Sample tested only.

IV Parameter is guaranteed by design and characterization testing.

V Parameter is a typical value only.

VI 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range.

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AD9865

Rev. A | Page 9 of 48

ABSOLUTE MAXIMUM RATINGS

Table 8.

Parameter Rating

ELECTRICAL

AVDD, CLKVDD Voltage 3.9 V maximum

DVDD, DRVDD Voltage 3.9 V maximum

RX+, RX−, REFT, REFB −0.3 V to AVDD + 0.3 V

IOUTP+, IOUTP− −1.5 V to AVDD + 0.3 V

IOUTN+, IOUTN−, IOUTG+,

IOUTG−

−0.3 V to +7 V

OSCIN, XTAL −0.3 V to CLVDD + 0.3 V

REFIO, REFADJ −0.3 V to AVDD + 0.3 V

Digital Input and Output Voltage −0.3 V to DRVDD + 0.3 V

Digital Output Current 5 mA maximum

ENVIRONMENTAL

Operating Temperature Range

(Ambient)

−40°C to +85°C

Maximum Junction Temperature 125°C

Lead Temperature (Soldering, 10 s) 150°C

Storage Temperature Range

(Ambient)

−65°C to +150°C

Stresses above those listed under the Absolute Maximum

Ratings may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL CHARACTERISTICS

Thermal Resistance: 64-lead LFCSP (4-layer board).

θJA = 24°C/W (paddle soldered to ground plane, 0 LPM air).

θJA = 30.8°C/W (paddle not soldered to ground plane,

0 LPM air).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

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AD9865

Rev. A | Page 10 of 48

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

4493-0-002

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

3217 18 19 20 21 22 23 24 25 26 27 28 29 30 31

33

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

49

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50

ADIO9/Tx[5]

ADIO8/Tx[4]

ADIO7/Tx[3]

ADIO6/Tx[2]

ADIO5/Tx[1]

ADIO4/Tx[0]

ADIO3/Rx[5]

ADIO2/Rx[4]

ADIO1/Rx[3]

ADIO0/Rx[2]

NC/Rx[1]

NC/Rx[0]

RXCLK

T

XCLK/TXQUIET

TXEN/TXSYNC

RXEN/RXSYNC

DRVDD

DRVSS

CLKOUT1

SDIO

SDO

SCLK

SEN

GAIN/PGA[5]

PGA[4]

PGA[3]

PGA[2]

PGA[1]

REFB

AVSS

RESET

PGA[0]

AVSS

IOUT_N–

IOUT_G–

AVSS

AVDD

REFIO

REFADJ

AVDD

AVSS

RX+

RX–

REFT

AVSS

AVDD

AVSS

DRVDD

DRVSS

PWR_DWN

CLKOUT2

DVDD

DVSS

CLKVDD

OSCIN

XTAL

CLKVSS

CONFIG

MODE

IOUT_G+

IOUT_N+

IOUT_P–

IOUT_P+

AD9865

TOP VIEW

(Not to Scale)

PIN 1

IDENTIFIER

Figure 2. Pin Configuration

Table 9. Pin Function Descriptions

Pin No. Mnemonic Mode1Description

1 ADIO9 HD MSB of ADIO Buffer

Tx[5] FD MSB of Tx Nibble Input

2 to 5 ADIO8 to 5 HD Bits 8 to 5 of ADIO Buffer

Tx[4 to 1] FD Bits 4 to 1 of Tx Nibble Input

6 ADIO4 HD Bit 4 of ADIO Buffer

Tx[0] FD LSB of Tx Nibble Input

7 ADIO3 HD Bit 3 of ADIO Buffer

Rx[5] FD MSB of Rx Nibble Output

8, 9 ADIO2, 1 HD Bits 2 to 1 of ADIO Buffer

Rx[4, 3] FD Bits 4 to 3 of Rx Nibble Output

10 ADIO0 HD LSB of ADIO Buffer

Rx[2] FD Bit 2 of Rx Nibble Output

11 NC HD No Connect

Rx[1] FD Bit 1 of Rx Nibble Output

12 NC HD No Connect

Rx[0] FD LSB of Rx Nibble Output

13 RXEN HD ADIO Buffer Control Input

RXSYNC FD Rx Data Synchronization Output

14 TXEN HD Tx Path Enable Input

TXSYNC FD Tx Data Synchronization Input

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AD9865

Rev. A | Page 11 of 48

Pin No. Mnemonic Mode1Description

15 TXCLK HD ADIO Sample Clock Input

TXQUIET FD Fast TxDAC/IAMP Power-Down

16 RXCLK HD ADIO Request Clock Input

FD Rx and Tx Clock Output at 2 x fADC

17, 64 DRVDD Digital Output Driver Supply Input

18, 63 DRVSS Digital Output Driver Supply Return

19 CLKOUT1 fADC/N Clock Output (L = 1, 2, 4, or 8)

20 SDIO Serial Port Data Input/Output

21 SDO Serial Port Data Output

22 SCLK Serial Port Clock Input

23 SEN Serial Port Enable Input

24 GAIN FD Tx Data Port (Tx[5:0]) Mode Select

PGA[5] HD or FD MSB of PGA Input Data Port

25 to 29 PGA[4 to 0] HD or FD Bits 4 to 0 of PGA Input Data Port

30 RESET Reset Input (Active Low)

31, 34, 36, 39, 44, 47, 48 AVSS Analog Ground

32, 33 REFB, REFT ADC Reference Decoupling Nodes

35, 40, 43 AVDD Analog Power Supply Input

37, 38 RX−, RX+ Receive Path − and + Analog Inputs

41 REFADJ TxDAC Full-Scale Current Adjust

42 REFIO TxDAC Reference Input/Output

45 IOUT_G− −Tx Amp Current Output_Sink

46 IOUT_N− −Tx Mirror Current Output_Sink

49 IOUT_G+ +Tx Amp Current Output_Sink

50 IOUT_N+ +Tx Mirror Current Output_Sink

51 IOUT_P− −TxDAC Current Output_Source

52 IOUT_P+ +TxDAC Current Output_Source

53 MODE Digital Interface Mode Select Input

LOW = HD, HIGH = FD

54 CONFIG Power-Up SPI Register Default Setting Input

55 CLKVSS Clock Oscillator/Synthesizer Supply Return

56 XTAL Crystal Oscillator Inverter Output

57 OSCIN Crystal Oscillator Inverter Input

58 CLKVDD Clock Oscillator/Synthesizer Supply

59 DVSS Digital Supply Return

60 DVDD Digital Supply Input

61 CLKOUT2 fOSCIN/L Clock Output, (L = 1, 2, or 4)

62 PWR_DWN Power-Down Input

1HD = half-duplex mode; FD = full-duplex mode.

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AD9865

Rev. A | Page 12 of 48

TYPICAL PERFORMANCE CHARACTERISTICS

Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = fADC = 50 MSPS, low-pass filter’s f−3 dB = 22 MHz, AIN = −1 dBFS,

RIN = 50 Ω, half- or full-duplex interface, default power bias settings.

04493-0-040

FREQUENCY (MHz)

INPUT REFERRED SPECTRUM (dBm)

0 6.25 12.50 18.75 25.00

10

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0FUND = –1dBFS

SINAD = 59.1dBFS

ENOB = 9.53 BITS

SNR = 60.2dBFS

THD = –65.2dBFS

SFDR = –64.9dBc (THIRD HARMONIC)

RBW = 12.21kHz

Figure 3. Spectral Plot with 4 k FFT of Input Sinusoid with

RxPGA = 0 dB and PIN = 9 dBm

04493-0-041

FREQUENCY (MHz)

INPUT REFERRED SPECTRUM (dBm)

0 5 10 15 20 25

–30

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40 RBW = 12.2kHz

Figure 4. Spectral Plot with 4 k FFT of 84-Carrier DMT Signal

with PAR = 10.2 dB, PIN = −33.7 dBm, and RxPGA = 36 dB

04493-0-042

INPUT AMPLITUDE (dBFS)

0dBFS = 2V p-p

SINAD (dBFS)

THD (dBFS)

–21 –18 –15 –12 –9 –6 –3 0

66

45

48

51

54

57

60

63

–50

–92

–86

–80

–74

–68

–62

–56

SINAD @ 3.14V

SINAD @ 3.3V

SINAD @ 3.46V

THD @ 3.14V

THD @ 3.3V

THD @ 3.46V

Figure 5. SINAD and THD vs. Input Amplitude and Supply

(fIN = 8 MHz, LPF f−3 dB = 26 MHz; Rx PGA = 0 dB)

04493-0-043

RxPGA GAIN (dB)

SINAD (dBFS)

ENOB (Bits)

–6 0 6 12 18 24 30 36 42 48

62

41

44

47

50

53

56

59

10.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

1MHz

5MHz

10MHz

15MHz

20MHz

Figure 6. SINAD/ENOB vs. RxPGA Gain and Frequency

04493-0-044

RxPGA GAIN (dB)

THD (dBFC)

–6 0 6 12 18 24 30 36 42 48

–55

–85

–80

–75

–70

–65

–60

1MHz

5MHz

10MHz

15MHz

20MHz

Figure 7. THD vs. RxPGA Gain and Frequency

04493-0-045

RxPGA GAIN (dB)

SINAD (dBFS)

THD (dBc)

–6 0 6 12 18 24 30 36 42 48

62

41

44

47

50

53

56

59

–45

–80

–75

–70

–65

–60

–55

–50

SINAD @ +25°C

SINAD @ +85°C

SINAD @ –40°C

THD @ +25°C

THD @ +85°C

THD @ –40°C

Figure 8. SINAD/THD Performance vs. RxPGA Gain

and Temperature ( fIN = 5 MHz)

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AD9865

Rev. A | Page 13 of 48

0

Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = fADC = 80 MSPS, low-pass filter’s f−3 dB = 30 MHz, AIN = −1 dBFS,

RIN = 50 Ω, half- or full-duplex interface, default power bias settings.

04493-0-046

FREQUENCY (MHz)

INPUT REFERRED SPECTRUM (dBm)

0 1020304

10

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0FUND = –1dBFS

SINAD = 59.3dBFS

ENOB = 9.56 BITS

SNR = 59.8dBFS

THD = –69.1dBFS

SFDR = –70.3dBc (THIRD HARMONIC)

RBW = 19.53kHz

Figure 9. Spectral Plot with 4k FFT of Input Sinusoid

with RxPGA = 0 dB and PIN = 9 dBm

04493-0-047

FREQUENCY (MHz)

INPUT REFERRED SPECTRUM (dBm)

0 1020304

–30

–130

–120

–110

–100

–90

–80

–70

–60

–50

–40 RBW = 19.53kHz

0

Figure 10. Spectral Plot with 4k FFT of 111-Carrier DMT Signal with

PAR = 11 dB, PIN = −33.7 dBm, LPF f−3 dB = 32 MHz, and RxPGA = 36 dB

04493-0-048

INPUT AMPLITUDE (dBFS)

0dBFS = 2V p-p

SINAD (dBFS)

THD (dBFS)

–21 –18 –15 –12 –9 –6 –3 0

66

45

48

51

54

57

60

63

–50

–92

–86

–80

–74

–68

–62

–56

SINAD @ 3.14V

SINAD @ 3.3V

SINAD @ 3.46V

THD @ 3.14V

THD @ 3.3V

THD @ 3.46V

Figure 11. SINAD and THD vs. Input Amplitude and Supply

(fIN = 8 MHz, LPF f−3 dB = 26 MHz; RxPGA = 0 dB)

04493-0-049

RxPGA GAIN (dB)

SINAD (dBFS)

ENOB (Bits)

–6 0 6 12 18 24 30 36 42 48

62

41

44

47

50

53

56

59

10.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

5MHz

10MHz

15MHz

20MHz

30MHz

Figure 12. SINAD/ENOB vs. RxPGA Gain and Frequency

04493-0-050

RxPGA GAIN (dB)

THD (dBc)

–6 0 6 12 18 24 30 36 42 48

–

55

–85

–80

–75

–70

–65

–60

5MHz

10MHz

15MHz

20MHz

30MHz

Figure 13. THD vs. RxPGA Gain and Frequency

04493-0-051

RxPGA GAIN (dB)

SINAD (dBFS)

THD (dBc)

–6 0 6 12 18 24 30 36 42 48

62

41

44

47

50

53

56

59

–

40

–75

–70

–65

–60

–55

–50

–45

SINAD @ +25°C

SINAD @ +85°C

SINAD @ –40°C

THD @ +25°C

THD @ +85°C

THD @ –40°C

Figure 14. SINAD/THD Performance vs. RxPGA Gain and Temperature

( fIN = 10 MHz)

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AD9865

Rev. A | Page 14 of 48

04493-0-052

INPUT FREQUENCY (MHz)

SNR (dBFS)

THD (dBc)

–6 0 6 12 18 24 30 36 42 48

61.0

60.5

60.0

59.5

59.0

58.5

58.0

57.5

57.0

56.5

56.0

–

52

–54

–56

–58

–60

–62

–64

–66

–68

–70

–72

SNR @ 3.13V

SNR @ 3.3V

SNR @ 3.47V

THD @ 3.13V

THD @ 3.3V

THD @ 3.47V

Figure 15. SNR and THD vs. Input Frequency and Supply

( LPF f−3 dB = 26 MHz; RxPGA = 0 dB)

04493-0-053

RxPGA GAIN (dB)

INTEGRATED NOISE (µV rms)

NOISE SPECTRAL DENSITY (nV/ Hz)

–6 0 6 12 18 24 30 36 42 48

109.4

98.5

87.5

76.6

65.6

54.7

43.8

32.8

21.9

10.9

0

20

18

16

14

12

10

8

6

4

2

0

AD9865: +25°C

AD9865: +85°C

AD9865: –40°C

Figure 16. Input Referred Integrated Noise and Noise Spectral Density vs.

RxPGA Gain (LPF f−3 dB = 26 MHz)

04493-0-054

GAIN (dB)

DC OFFSET (% of full-scale)

–6 0 6 12 18 24 30 36 42 48

5

–5

–4

–3

–2

–1

0

1

2

3

4

DEVICE 1

DEVICE 2

DEVICE 3

DEVICE 4

Figure 17. Rx DC Offset vs. RxPGA Gain

04493-0-055

INPUT FREQUENCY (MHz)

SNR (dBFS)

THD (dBc)

20 30 40 50 60 70 80

60.0

55.0

–20

–70

–60

–50

–40

–30

55.5

56.0

56.5

57.0

57.5

58.0

58.5

59.0

59.5

SNR @ 3.13V

SNR @ 3.3V

SNR @ 3.46V

THD @ 3.13V

THD @ 3.3V

THD @ 3.46V

Figure 18. SNR and THD vs. Sample Rate and Supply

(LPF Disabled; RxPGA = 0 dB; fIN = 8 MHz)

04493-0-056

CUTOFF FREQUENCY (MHz)

SNR (dBc)

0 1020304050607080

45

44

43

42

41

40

39

38

Figure 19. SNR vs. Filter Cutoff Frequency

(50 MSPS; fIN = 5 MHz; AIN = −1 dB; RxPGA = 48 dB)

04493-0-057

RxPGA GAIN (dB)

GAIN STEP ERROR (dB)

–6 0 6 12 18 24 30 36 42 48

0.5

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

AD9865: GAIN STEP ERROR @ +25

°

C

AD9865: GAIN STEP ERROR @ +85

°

C

AD9865: GAIN STEP ERROR @ –40

°

C

Figure 20. RxPGA Gain Step Error vs. Gain (fIN = 10 MHz)

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AD9865

Rev. A | Page 15 of 48

Rx PATH TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = fADC = 50 MSPS, low-pass filter disabled, RxPGA = 0 dB, AIN = −1 dBFS,

RIN = 50 Ω, half- or full-duplex interface, default power bias settings.

04493-0-058

TIME (ns)

CODE

0 80 160 240 320 400 480 560 640 720

512

64

128

192

256

320

384

448

Figure 21. RxPGA Settling Time −12 dB to +48 dB Transition for DC Input

(fADC = 50 MSPS, LPF Disabled)

04493-0-059

INPUT FREQUENCY (MHz)

AMPLITUDE RESPONSE (dB)

0 5 10 15 20 25 30 35 40 45 50

0

–18

–15

–12

–9

–6

–3

3.3V

3.0V

3.6V

Figure 22. Rx Low-Pass Filter Amplitude Response vs. Supply

(fADC = 50 MSPS,f−3 dB = 33 MHz, RxPGA = 0 dB)

04493-0-060

FREQUENCY (MHz)

ATTEN

@RxPGA = 0dB

(dB)

0 5 10 15 20 25 30 35

140

60

70

80

90

100

110

120

130 TxDAC ISOLATION @ 0dB

IAMP ISOLATION @ 0dB

Figure 23. Rx to Tx Full-Duplex Isolation @ 0 RxPGA Setting

(Note: ATTEN @ RxPGA = x dB = ATTEN @ RxPGA = 0 dB − RxPGA Gain)

04493-0-061

TIME (ns)

CODE

0 80 160 240 320 400 480 560 640 720

352

320

288

256

224

192

160

128

96

64

Figure 24. RxPGA Settling Time for 0 dB to +5 dB Transition for DC Input

(fADC = 50 MSPS, LPF Disabled)

04493-0-062

INPUT FREQUENCY (MHz)

FUNDAMENTAL (dB)

0 5 10 15 20 25 30 35 40 5045

0

–20

–16

–18

–14

–12

–10

–8

–6

–2

–4

–6dB GAIN

0dB GAIN

+6dB GAIN

+18dB GAIN

+30dB GAIN

+42dB GAIN

Figure 25. Rx Low-Pass Filter Amplitude Response vs. RxPGA Gain

(LPF's f−3 dB = 33 MHz)

04493-0-090

FREQUENCY (MHz)

RESISTANCE (

Ω

)

CAPACITANCE (pF)

5 105958575655545352515

420

320

10

0

1

2

3

4

5

6

7

8

9

330

340

350

360

370

380

390

400

410

R

IN

C

IN

Figure 26. Rx Input Impedance vs. Frequency

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AD9865

Rev. A | Page 16 of 48

TxDAC PATH TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS and 80 MSPS, RSET = 1.96 kΩ, 2:1 transformer coupled output

(see Figure 63) into 50 Ω load half- or full-duplex interface, default power bias settings.

04493-0-072

FREQUENCY (MHz)

dBm

0 5 10 15 20 30

10

–80

–70

–60

–50

–40

–30

–20

–10

0

Figure 27. Dual-Tone Spectral Plot of TxDAC's Output

(fDATA = 50 MSPS, 4× Interpolation, 10 dBm Peak Power,

F1 = 17 MHz, F2 = 18 MHz)

04493-0-073

2-TONE CENTER FREQUENCY (MHz)

IMD (dBFS)

(RELATIVE TO PEAK POWER)

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0

–65

–90

–85

–80

–75

–70

10dBm

7dBm

4dBm

Figure 28. 2-Tone IMD Frequency Sweep vs. Peak Power

with fDATA = 50 MSPS, 4× Interpolation

04493-0-074

2-TONE CENTER FREQUENCY (MHz)

SFDR (dBFS)

(RELATIVE TO PEAK POWER)

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0

–65

–90

–85

–80

–75

–70

10dBm 7dBm

4dBm

Figure 29. 2-Tone Worst Spur Frequency Sweep vs. Peak Power

with fDATA = 50 MSPS, 4× Interpolation

04493-0-075

FREQUENCY (MHz)

dBm

0 5 10 15 20 25 30 35 40

10

–80

–70

–60

–50

–40

–30

–20

–10

0

Figure 30. Dual-Tone Spectral Plot of TxDAC's Output

(fDATA = 80 MSPS, 2× Interpolation, 10 dBm Peak Power,

F1 = 27.1 MHz, F2 = 28.7 MHz)

04493-0-076

2-TONE CENTER FREQUENCY (MHz)

IMD (dBFS)

(RELATIVE TO PEAK POWER)

0 5 10 15 20 25 30

–65

–90

–85

–80

–75

–70

10dBm

7dBm

4dBm

Figure 31. 2-Tone IMD Frequency Sweep vs. Peak Power

with fDATA = 80 MSPS, 2× Interpolation

04493-0-077

2-TONE CENTER FREQUENCY (MHz)

SFDR (dBFS)

(RELATIVE TO PEAK POWER)

0 5 10 15 20 25 30

–65

–90

–85

–80

–75

–70

10dBm

7dBm

4dBm

Figure 32. 2-Tone Worst Spur Frequency Sweep vs. Peak Power

with fDATA = 80 MSPS, 2× Interpolation

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AD9865

Rev. A | Page 17 of 48

04493-0-078

FREQUENCY (MHz)

dBm

0 5 10 15 20 25

–20

–30

–40

–50

–60

–70

–80

–90

–100

PAR = 11.4

RMS = –1.4dBm

Figure 33. Spectral Plot of 84-Carrier OFDM Test Vector

(fDATA = 50 MSPS, 4× Interpolation)

04493-0-079

FREQUENCY (MHz)

dBm

0 25 50 75 100 125 150 175 200

–20

–30

–40

–50

–60

–70

–80

–90

–100

PAR = 11.4

RMS = –1.4dBm

Figure 34. Wideband Spectral Plot of 88-Subcarrier OFDM Test Vector

(fDATA = 50 MSPS, 4× Interpolation)

04493-0-080

AOUT (dBFS)

SNR AND 2-TONE IMD (dBFS)

(RELATIVE TO PEAK POWER)

–24 –21 –18 –15 –12 –9 –6 –3 0

100

55

60

65

70

75

80

85

90

95 2-TONE IMD

SNR

Figure 35. SNR and SFDR vs. POUT

(fOUT = 12.55 MHz, fDATA = 50 MSPS, 4× Interpolation)

04493-0-081

FREQUENCY (MHz)

dBm

0 5 10 15 20 25 30 35 40

–20

–100

–90

–80

–70

–60

–50

–40

–30

PAR = 11.4

RMS = –1.4dBm

Figure 36. Spectral Plot of 111-Carrier OFDM Test Vector

(fDATA = 80 MSPS, 2× Interpolation)

04493-0-082

FREQUENCY (MHz)

dBm

0 20 40 60 80 100 120 140 160

–20

–100

–90

–80

–70

–60

–50

–40

–30

PAR = 11.4

RMS = –1.4dBm

Figure 37. Wideband Spectral Plot of 111-Carrier OFDM Test Vector

(fDATA = 80 MSPS, 2× Interpolation)

04493-0-083

AOUT (dBFS)

SNR AND 2-TONE IMD (dBFS)

(RELATIVE TO PEAK POWER)

–24 –21 –18 –15 –12 –9 –6 –3 0

95

55

60

65

70

75

80

85

90

SNR

2-TONE IMD

Figure 38. SNR and SFDR vs. POUT

(fOUT = 20 MHz, fDATA = 80 MSPS, 2× Interpolation)

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AD9865

Rev. A | Page 18 of 48

IAMP PATH TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = CLKVDD = DVDD = DRVDD = 3.3 V, fOSCIN = 50 MSPS, RSET = 1.58 kΩ, 1:1 transformer coupled output (see Figure 64 and

Figure 65) into 50 Ω load, half- or full-duplex interface, default power bias settings.

04493-0-084

FREQUENCY (MHz)

dBm

0 5 10 15 20 25

20

–60

–55

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

5

10

15

RBW = 2.3kHz

Figure 39. Dual-Tone Spectral Plot of IAMPN Output

(IAMP Settings of I = 12.5 mA, N = 4, G = 0,

2:1 Transformer into 75 Ω Loader, VCM = 4.8 V)

04493-0-085

FREQUENCY (MHz)

dBm

0 5 10 15 20 25

0

–80

–70

–60

–50

–40

–30

–20

–10

PAR = 11.4

RMS = 10.3dBm

Figure 40. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMPN in

Current-Mode Configuration

(IAMP Settings of I = 10 mA, N = 4, G = 0; VCM = 4.8 V)

04493-0-086

FREQUENCY (MHz)

dBm

0 5 10 15 20 25

0

–80

–70

–60

–50

–40

–30

–20

–10

PAR = 11.4

RMS = 10.4dBm

Figure 41. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in

Voltage-Mode Configuration with AVDD = 5 V

(PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6)

04493-0-087

VCM (V)

OIP3 (dBm)

3.0 3.5 4.0 4.5 5.0

48

5MHz

10MHz

15MHz 20MHz

2.5MHz

30

46

44

42

40

38

36

34

32

Figure 42. IOUTN Third-Order Intercept vs. Common-Mode Voltage

(IAMP Settings of I = 12.5 mA, N = 4, G = 0, 2:1

Transformer into 75 Ω Load)

04493-0-088

VCM (V)

OIP3 (dBm)

3.0 3.5 4.0 4.5 5.0

42

5MHz

10MHz

15MHz

20MHz

2.5MHz

30

40

38

36

34

32

Figure 43. IOUTG Third-Order Intercept vs. Common-Mode Voltage

(IAMP Settings of I = 4.25 mA, N = 0, G = 6,

2:1 Transformer into 75 Ω Load)

04493-0-089

FREQUENCY (MHz)

dBm

0 5 10 15 20 25

0

–80

–70

–60

–50

–40

–30

–20

–10

PAR = 11.4

RMS = 9.8dBm

RBW = 10kHz

Figure 44. Spectral Plot of 84-Carrier OFDM Test Vector Using IAMP in

Voltage-Mode Configuration with AVDD = 3.3 V

(PBR951 Transistors, IAMP Settings of I = 6 mA, N = 2, G = 6)

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AD9865

Rev. A | Page 19 of 48

SERIAL PORT

Table 10. SPI Register Mapping

Power-Up Default Value

MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex)

Address

(Hex)1

Bit

Break-

down Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 Comments

SPI PORT CONFIGURATION AND SOFTWARE RESET

0x00 (7) 4-Wire SPI 1 0 0 0 0

(6) LSB First 1 0 0 0 0

(5) S/W Reset 1 0 0 0 0

Default SPI configuration is

3-wire, MSB first.

POWER CONTROL REGISTERS (via PWR_DWN pin)

0x01 (7) Clock Syn. 1 0 0 0 0

(6) TxDAC/IAMP 1 0 0 0 0

(5) Tx Digital 1 0 0 0 0

(4) REF 1 0 0 0 0

(3) ADC CML 1 0 0 0 0

(2) ADC 1 0 0 0 0

(1) PGA Bias 1 0 0 0 0

(0) RxPGA 1 0 0 0 0

PWR_DWN = 0.

Default setting is for all

blocks powered on.

0x02 (7) CLK Syn. 1 0 0 0 1*

(6) TxDAC/IAMP 1 1 1 1 1

(5) Tx Digital 1 1 1 1 1

(4) REF 1 1 1 1 1

(3) ADC CML 1 1 1 1 1

(2) ADC 1 1 1 1 1

(1) PGA Bias 1 1 1 1 1

(0) RxPGA 1 1 1 1 1

PWR_DWN = 1.

Default setting* is for all

functional blocks powered

down except PLL.

*MODE = CONFIG = 1.

Setting has PLL powered

down with OSCIN input

routed to RXCLK output.

HALF-DUPLEX POWER CONTROL

0x03 (7:3) Tx OFF Delay 5

(2) Rx _TXEN 1

(1) Tx PWRDN 1

(0) Rx PWRDN 1

0xFF 0xFF N/A N/A

Default setting is for TXEN

input to control power

on/off of Tx/Rx path.

Tx driver delayed by 31

1/fDATA clock cycles.

PLL CLOCK MULTIPLIER/SYNTHESIZER CONTROL

0x04 (5) Duty Cycle Enable 1 0 0 0 0

(4) fADC from PLL 1 0 0 0 0

(3:2) PLL Divide-N 2 00 00 00 00

(1:0) PLL Multiplier-M 2 01 10* 01 01

Default setting is Duty Cycle

Restore disabled, ADC CLK

from OSCIN input, and PLL

multiplier × 2 setting.

*PLL multiplier × 4 setting.

0x05 (2) OSCIN to RXCLK 1 0 0 0 1*

(1) Invert RXCLK 1 0 0 0 0

(0) Disabled RXCLK 1 0 0 0 0

Full-duplex RXCLK normally

at nibble rate.

*Exception on power-up.

0x06 (7:6) CLKOUT2 Divide 2 01 01 01 01

(5) CLKOUT2 Invert 1 0 0 0 0

(4) CLKOUT2 Disable 1 0 0 0 1*

(3:2) CLKOUT1 Divide 2 01 01 01 01

(1) CLKOUT1 Invert 1 0 0 0 0

(0) CLKOUT1 Disable 1 0 0 0 1*

Default setting is CLKOUT2

and CLKOUT1 enabled with

divide-by-2.

*CLKOUT1 and CLKOUT2

disabled.

Rx PATH CONTROL

0x07 (5) Initiate Offset Cal. 1 0 0 0 0

(4) Rx Low Power 1 0 1* 0 1*

(0) Rx Filter ON 1 1 1 1 1

Default setting has LPF ON

and Rx path at nominal

power bias setting.

*Rx path to low power.

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AD9865

Rev. A | Page 20 of 48

Power-Up Default Value

MODE = 0 (Half-Duplex) MODE = 1 (Full-Duplex)

Address

(Hex)1

Bit

Break-

down Description Width CONFIG = 0 CONFIG = 1 CONFIG = 0 CONFIG = 1 Comments

0x08 (7:0) Rx Filter Tuning

Cut-off Frequency

80x80 0x61 0x80 0x80 Refer to Low-Pass Filter

section.

Tx/Rx PATH GAIN CONTROL

0x09 (6) Use SPI Rx Gain 1

(5:0) Rx Gain Code 6 0x00 0x00 0x00 0x00 Default setting is for

hardware Rx gain code via

PGA or Tx data port.

0x0A (6) Use SPI Tx Gain 1

(5:0) Tx Gain Code 6 0x7F 0x7F 0x7F 0x7F Default setting is for Tx gain

code via SPI control.

Tx AND Rx PGA CONTROL

0x0B (6) PGA Code for Tx 1 0 0 0 0

(5) PGA Code for Rx 1 1 1 1 1

(3) Force GAIN strobe 1 0 0 0 0

(2) Rx Gain on Tx Port 1 0 0 1* 1*

(1) 3-Bit RxPGA Port 1 0 1** 0 0

Default setting is RxPGA

control active.

*Tx port with GAIN strobe

(AD9875/AD9876-compatible).

** 3-bit RxPGA gain map

(AD9975-compatible).

Tx DIGITAL FILTER AND INTERFACE

0x0C (7:6) Interpolation

Factor

2 01 00 01 01

(4)

Invert

TXEN/TXSYNC

1 0 0 0 0

(3) Tx 5/5 Nibble* 1 N/A N/A 0 0

(2) LS Nibble First* 1 N/A N/A 0 0

(1) TXCLK neg. edge 1 0 0 0 0

(0) Twos complement 1 0 0 1 1

Default setting is 2×

interpolation with LPF

response. Data format is

straight binary for half-

duplex and twos

complement for full-duplex

interface.

*Full-duplex only.

Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK

0x0D (7) Analog Loopback 1 0 0 0 0

(6) Digital Loopback* 1 0 0 0 0

(5) Rx Port 3-State 1 N/A N/A 0 0

(4)

Invert

RXEN/RXSYNC

1 0 0 0 0

(3) RX 5/5 Nibble 1 N/A N/A 0 0

(2) LS Nibble First* 1 N/A N/A 0 0

(1) RXCLK neg. edge 1 0 0 0 0

(0) Twos complement 1 0 0 1 1

Data format is straight

binary for half-duplex and

twos complement for full-

duplex interface.

Analog loopback: ADC Rx

data fed back to TxDAC.

Digital loopback: Tx input

data to Rx output port.

*Full-duplex only.

DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID

0x0E (7) Low Drive

Strength

1 0 0 0 0

(0) TxDAC Output 1 0 0 0 0

0x0F (3:0) REV ID Number 4 0x00 0x00 0x00 0x00

Default setting is for high

drive strength and IAMP

enabled.

Tx IAMP GAIN AND BIAS CONTROL

0x10 (7) Select Tx Gain 1

(6:4) G1 3

(2:0) N 3

0x44 0x44 0x44 0x44

Secondary path G1 = 0, 1, 2,

3, 4.

Primary path N = 0, 1, 2, 3, 4.

0x11 (6:4) G2 3

(2:0) G3 3

0x62 0x62 0x62 0x62

Secondary path stages:

G2 = 0 to 1.50 in 0.25 steps

and G3 = 0 to 6.

0x12 (6:4) Stand_Secondary 3

(2:0) Stand_Primary 3 0x01 0x01 0x01 0x01 Standing current of primary

and secondary path.

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Analog Devices AD9865 User manual

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