Analog Devices ADV7511W Installation manual

Page 1 of 45 Rev A
ADV7511W
Low-Power HDMI 1.4a Transmitter
HARDWARE USER’S
GUIDE
- Revision A –
July 2011

ADV7511W HARDWARE USER’S GUIDE
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Page 2 of 45 Rev A
REVISION HISTORY
Rev. 0:
Initial Release 4/11
Rev A:
Section Change Description
Section ▶6.1.2 Corrected register bit information for the “Input ID” bits
Figure 17 Corrected Mux select bit table

ADV7511W HARDWARE USER’S GUIDE
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TABLE OF CONTENTS
Section 1: Introduction.........................................................................................................................................................................................7
1.1Scope and Organization.......................................................................................................................................................................7
1.1.1Links ................................................................................................................................................................................................7
1.1.2Symbols ...........................................................................................................................................................................................7
1.1.3Format Standards...........................................................................................................................................................................7
1.2Overview ................................................................................................................................................................................................8
1.3Hardware Features................................................................................................................................................................................8
1.4Supported Input Formats ....................................................................................................................................................................8
1.5Supported Output Formats .................................................................................................................................................................8
Section 2: Reference Documents.........................................................................................................................................................................9
2.1ADI Documents....................................................................................................................................................................................9
2.2Industry Specifications.........................................................................................................................................................................9
Section 3: Block diagram ....................................................................................................................................................................................10
Section 4: Specifications......................................................................................................................................................................................11
4.1Explanation of Test Levels.................................................................................................................................................................15
4.2ESD Caution........................................................................................................................................................................................15
Section 5: Pin and package information...........................................................................................................................................................16
5.1Mechanical Drawings and Outline Dimensions ............................................................................................................................19
Section 6: Functional Description.....................................................................................................................................................................20
6.1Input Connections..............................................................................................................................................................................20
6.1.1Unused Inputs..............................................................................................................................................................................20
6.1.2Video Data Capture Block..........................................................................................................................................................20
6.1.2.1Video Input Connections ...................................................................................................................................................20
6.1.3Audio Data Capture Block .........................................................................................................................................................26
6.1.3.1Supported Audio Input Format and Implementation....................................................................................................26
6.1.3.2Inter-IC Sound (I2S) Audio ...............................................................................................................................................28
6.1.3.3Sony/Philips Digital Interface (S/PDIF) ...........................................................................................................................30
6.1.3.4HBR Audio............................................................................................................................................................................30
6.1.4Hot Plug Detect (HPD) pin........................................................................................................................................................30
6.1.5Power Down / I2C Address (PD/AD) ......................................................................................................................................30
6.1.6Input Voltage Tolerance .............................................................................................................................................................31
6.2Output Connections...........................................................................................................................................................................31
6.2.1Output Formats Supported ........................................................................................................................................................31
6.2.2TMDS Outputs.............................................................................................................................................................................31
6.2.2.1ESD Protection.....................................................................................................................................................................31
6.2.2.2EMI Prevention....................................................................................................................................................................31
6.2.3Display Data Channel (DDC) pins............................................................................................................................................31
6.2.4Interrupt Output (INT) ..............................................................................................................................................................32
6.2.5PLL Circuit....................................................................................................................................................................................32
6.3Consumer Electronic Control (CEC) ..............................................................................................................................................32
6.3.1Unused Inputs..............................................................................................................................................................................32
6.3.2CEC Function...............................................................................................................................................................................32
6.4Video Data Formatting......................................................................................................................................................................33
6.4.1Supported 3D Formats................................................................................................................................................................33
6.4.2DE, Hsync and Vsync Generation.............................................................................................................................................33
6.4.3Color Space Conversion (CSC) Matrix.....................................................................................................................................34

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6.4.44:2:2 to 4:4:4 and 4:4:4 to 4:2:2 Conversion Block...................................................................................................................36
6.5DDC Controller ..................................................................................................................................................................................36
6.6Inter-IC Communications (I2C)......................................................................................................................................................36
6.6.1Two-Wire Serial Control Port ...................................................................................................................................................36
6.6.2Data Transfer via I2C..................................................................................................................................................................37
6.6.3Serial Interface Read/Write Examples ......................................................................................................................................38
6.7Power Domains...................................................................................................................................................................................39
6.7.1Power Supply Sequencing ..........................................................................................................................................................40
6.7.2Power Consumption ...................................................................................................................................................................40
Section 7: PCB Layout Recommendations ......................................................................................................................................................41
7.1Power Supply filtering........................................................................................................................................................................41
7.2Video Clock and Data Inputs............................................................................................................................................................42
7.3Audio Clock and Data Inputs ...........................................................................................................................................................42
7.4SDA and SCL.......................................................................................................................................................................................42
7.5DDCSDA and DDCSCL....................................................................................................................................................................42
7.6Current Reference Pin: R_EXT.........................................................................................................................................................43
7.7CEC Implementation .........................................................................................................................................................................43
Section 8: Glossary ..............................................................................................................................................................................................45

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TABLE OF FIGURES
Figure 1ADV7511W Functional Block Diagram.......................................................................................................................................10
Figure 2Timing for Video Data Interface ...................................................................................................................................................13
Figure 3Timing for I2S Audio Interface .....................................................................................................................................................13
Figure 4Timing for S/PDIF Audio Interface..............................................................................................................................................14
Figure 564-lead LQFP configuration (top view - not to scale) ................................................................................................................16
Figure 664-lead Low-Profile Quad Flat Pack [LQFP-SW64-2]...............................................................................................................19
Figure 72X Clock timing ...............................................................................................................................................................................23
Figure 8DDR DE timing - Register 0x16[1] = 1.........................................................................................................................................26
Figure 9DDR DE timing - Register 0x16[1] = 0.........................................................................................................................................26
Figure 10I2S Standard Audio – Data width 16 to 24 bits per channel..................................................................................................28
Figure 11I2S Standard Audio – 16-bit samples only...............................................................................................................................29
Figure 12Serial Audio – Right-Justified ....................................................................................................................................................29
Figure 13Serial Audio – Left-Justified.......................................................................................................................................................29
Figure 14AES3 Direct Audio ......................................................................................................................................................................30
Figure 15S/PDIF Data Timing....................................................................................................................................................................30
Figure 16Typical All-HDMI Home Theatre.............................................................................................................................................32
Figure 17Sync Processing Block Diagram ................................................................................................................................................34
Figure 18Single Channel of CSC (In_A)...................................................................................................................................................35
Figure 19Serial Port Read/Write Timing ..................................................................................................................................................38
Figure 20Serial Interface—Typical Byte Transfer....................................................................................................................................39
Figure 21Power Supply Domains...............................................................................................................................................................39
Figure 22AVDD and PVDD Max Noise vs. Frequency..........................................................................................................................41
Figure 23LC Filter Transfer Curve............................................................................................................................................................42
Figure 24CEC external connection............................................................................................................................................................43
Figure 25Example Schematic......................................................................................................................................................................44

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TABLE OF TABLES
Table 1Electrical Specifications ..................................................................................................................................................................11
Table 2Absolute Maximum Ratings ..........................................................................................................................................................14
Table 3Complete Pinout List ADV7511W ...............................................................................................................................................17
Table 4Input ID Selection ...........................................................................................................................................................................20
Table 5Normal RGB or YCbCr 4:4:4 (24 bits) with Separate Syncs; Input ID = 0..............................................................................21
Table 6YCbCr 4:2:2 Formats (24, 20, or 16 bits) Input Data Mapping: 0x48[4:3]=‘00’ (evenly distributed) Input ID=1 or 2 ...22
Table 7YCbCr 4:2:2 Formats (12, 10, or 8 bits) Input Data Mapping: 0x48[4:3]=‘00’ (evenly distributed) Input ID = 3,4,7,8..23
Table 8YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, right justified (R0x48[4:3] = ‘01’).......................................24
Table 9YCbCr 4:2:2 (8 bits) DDR with Separate Syncs: Input ID = 6, left justified (R0x48[4:3] = ‘10’)..........................................24
Table 10YCbCr 4:2:2 (12, 10, 8 bits) DDR with Separate Syncs:Input ID = 6, evenly distributed (R0x48[4:3] = ‘00’)................25
Table 11Audio input format summary....................................................................................................................................................27
Table 12SCLK Duty Cycle .........................................................................................................................................................................28
Table 13Some useful “End-User” CEC Features:...................................................................................................................................33
Table 14Supported 3D Formats................................................................................................................................................................33
Table 15Channel Assignment for Color Space Converter (CSC)........................................................................................................35
Table 16Serial Port Addresses...................................................................................................................................................................37
Table 17Maximum Power Consumption by Circuit – note these values will change after characterization................................40

ADV7511W HARDWARE USER’S GUIDE
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SECTION 1: INTRODUCTION
1.1 Scope and Organization
This document is intended to help the hardware designer understand what is necessary to design for the ADV7511W
and maintain the highest levels of performance. The ADV7511W Hardware User's Guide (HUG) provides guidelines to
design the schematics and board layout. Included are sections on the 64-lead LQFP package and an overview of the
functional blocks (including a brief description for each block) to provide an understanding of the ADV7511W
functional and performance capabilities. The ADV7511 Programming Guide (PG) is available as a separate document
and should be used to gain a complete understanding on how to configure the ADV7511W within a system
application.
It is divided into the following sections:
Section 2:Reference Documents is a list of other references, which will be helpful when designing with the
ADV7511W HDMI Transmitter.
Section 3:Block Diagram gives an overall functional view of the HDMI transmitter.
Section 4:Specifications give all pertinent data such as: timing, power and testing.
Section 5:Pin and Package Information give the mechanical details of the interface.
Section 6:Functional Description serves to elaborate on input, output and internal operations.
Section 7:PCB Layout Recommendations are an aid to low noise operation.
1.1.1 Links
There are many links in this document to help with navigation. Use a mouse click to follow a link, and use the Alt key +
left arrow key to return. Active links can be identified by the dotted blue underline.
1.1.2 Symbols
Symbols are used to indicate internal and external document references as follows:
▶Indicates a linked reference to another section of this document.
▷Indicates a reference to another document, either an ADI document or an external specification.
1.1.3 Format Standards
In this document, ADI has chosen to represent data in the following ways:
0xNN Hexadecimal (base-16) numbers are represented using the “C” language notation, preceded by 0x.
0bNN Binary (base-2) numbers are represented using “C” language notation, preceded by 0b.
NN Decimal (base-10) numbers are represented using no additional prefixes or suffixes.
Bit Bits are numbered in little-endian format; i.e., the least-significant bit of a byte or word is referred to
as bit 0.

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1.2 Overview
The ADV7511W is a high speed High Definition Multimedia Interface (HDMI) transmitter that is capable of
supporting an input data rate up to 165MHz (1080p @ 60Hz, UXGA @ 60Hz). Careful hardware design (schematics
and PCB layout) is recommended to optimize the performance and to ensure HDMI compliance.
▷The ADV7511W Programming Guide and ADV7511W Software Driver User Guide are also available if required.
1.3 Hardware Features
■HDMI v1.4 features supported
3D video
Advanced Colorimetry
•sYCC601
•Adobe RGB
•Adobe YCC601
■Operation up to 165MHz (TMDS link frequency)
■Integrated CEC support with 3 message buffers
■Supports x.v.Color™ (Gamut Metadata)
■Internal HDCP key storage
■Interrupt (INT) output pin eliminates constant I2C monitoring
■Supports I2S, S/PDIF and HBR audio input formats
■No audio Master Clock (MCLK) required for audio
■Requires 1.8V and 3.3V supply
■EDID buffered on chip
■Color Space Converter (CSC) with video range clipping
■64-lead LQFP package
■-40°C to +105°C temperature range
1.4 Supported Input Formats
■24 bit RGB 4:4:4 (separate syncs)
■24 bit YCbCr 4:4:4 (separate syncs)
■24, 20, or 16 bit YCbCr 4:2:2 (embedded or separate syncs)
■12, 10, or 8 bit YCbCr 4:2:2 (2x pixel clock with embedded or separate syncs)
■12, 10, or 8 bit YCbCr 4:2:2 (DDR with embedded or separate syncs)
1.5 Supported Output Formats
■24 bit RGB 4:4:4
■24 bit YCbCr 4:4:4
■24 bit YCbCr 4:2:2

ADV7511W HARDWARE USER’S GUIDE
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SECTION 2: REFERENCE DOCUMENTS
2.1 ADI Documents
ADV7511W Data Sheet
ADV7511W Programming Guide
AN-810 - EDID/HDCP Controller Application Note
2.2 Industry Specifications
EIA/CEA-861-E
HDMI Specification 1.4a
HDCP 1.4

ADV7511W HARDWARE USER’S GUIDE
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SECTION 3: BLOCK DIAGRAM
Figure 1 ADV7511W Functional Block Diagram
I2C
SLAVE
I2C
MASTER
SDA
SCL
INT
HPD
TX0+/TX0–
TX1+/TX1–
TX2+/TX2–
TXC+/TXC–
DDCSDA
DDCSCL
ADV7511W
TMDS
OUTPUTS
CEC
CEC CONTROLLER/
BUFFER
SPDIF
I2S[3:0]
MCLK
LRCLK
SCLK
AUDIO
DATA
CAPTURE
D[23:0]
VSYNC
HSYNC
DE
CLK
VIDEO
DATA
CAPTURE
REGISTERS
AND
CONFIG.
LOGIC
4:2:2
4:4:4
AND
COLOR
SPACE
CONVERTER
HDCP
AND EDID
MICROCONTROLLER
HDCP KEYS
HDCP
ENCRYPTION
CEC_CLK

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SECTION 4: SPECIFICATIONS
Table 1 Electrical Specifications
Parameter Conditions ADV7511W
Temp Test Level1Min Typ Max Unit
DIGITAL INPUTS
Data Inputs – Video, Audio and
CEC_CLK
Input Voltage, High (VIH) Full VI 1.35 3.5 V
Input Voltage, Low (VIL) Full VI -0.3 0.7 V
Input Capacitance 25°C VIII 1.0 1.5 pF
I2C Lines (DDCSDA, DDCSCL, SDA,
SCL)
Input Voltage, High (VIH) Full VI 1.19 5.5 V
Input Voltage, Low (VIL) Full VI -0.3 0.8 V
CEC
Input Voltage, High (VIH) Full VI 2.0 5.5 V
Input Voltage, Low (VIL) Full VI -0.3 0.8 V
Output Voltage, High (VIH) Full VI 2.5 3.63 V
Output Voltage, Low (VIL) Full VI -0.3 0.6 V
HPD
Input Voltage, High (VIH) Full VI 1.3 5.5 V
Input Voltage, Low (VIL) Full VI -0.3 0.8 V
THERMAL CHARACTERISTICS
Thermal Resistance
θJC Junction-to-Case Full V 20 °C/W
θJA Junction-to-Ambient Full V 43 °C/W
Ambient Temperature Full V -40 +25 +105 °C
DC SPECIFICATIONS
Input Leakage Current, IIL 25°C VI −1 +1 μA
POWER SUPPLY
1.8V Supply Voltage (DVdd, AVdd,
PVdd, BGVdd)
Full IV 1.71 1.8 1.90 V
1.8V Supply Voltage Noise Limit
DVdd – HDMI Digital Core Full V 64 mV RMS
AVdd – HDMI Analog Core Refer to ▶Section 7.1 Full V mV RMS
PLVdd – HDMI PLL – Analog Refer to ▶Section 7.1 Full V mV RMS
PVdd – HDMI PLL - Digital Full V 64 mV RMS
BGVdd - Band-gap Full V 64 mV RMS
3.3V Supply Voltage (DVdd_3V) Full 3.15 3.3 3.45 V
Power-Down Current – level 1 Refer to the ADV7511
Programming Guide
25°C IV 20 mA
Power-Down Current – level 2 Refer to the ADV7511
Programming Guide
25°C IV 300 μA
Transmitter Total Power
1.8V power = 325mW
3.3V power = 1mW
1080p, 24 bit, typical
random pattern
Full VI 326 mW

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Parameter Conditions ADV7511W
Temp Test Level1Min Typ Max Unit
AC SPECIFICATIONS
TMDS Output Clock Frequency 25°C IV 20 165 MHz
TMDS Output Clock Duty Cycle 25°C IV 48 52 %
Input Video Clock Frequency Full 165 MHz
Input Video Data Setup Time – tVSU2Full IV 1.8 nS
Input Video Data Hold Time – tVHLD2Full IV 1.3 nS
TMDS Differential Swing 25°C VII 900 1100 1200 mV
Differential Output Timing
Low-to-High Transition Time 25°C VII 75 95 pS
High-to-Low Transition Time 25°C VII 75 95 pS
VSYNC and HSYNC Delay from DE Falling
Edge
25°C IV 1 UI3
VSYNC and HSYNC Delay to DE Rising
Edge
25°C IV 1 UI
AUDIO AC TIMING (see ▶ Figure 3 to
▶ Figure 4
SCLK Duty Cycle See ▶ Table 12
When N/2 = even number Full IV 40 50 60 %
When N/2 = odd number Full IV 49 50 51 %
I2S[3:0], S/PDIF, LRCLK Setup – tASU Full IV 2 nS
I2S[3:0], S/PDIF, LRCLK Hold Time –
tAHLD
Full IV 2 nS
CEC
CEC_CLK Frequency Full VIII 3 124100 MHz
CEC_CLK Accuracy Full VIII -2 +2 %
I2C Interface (see ▶Figure 19)
SCL Clock Frequency Full 400 kHz
SDA Setup Time - tDSU Full 100 nS
SDA Hold Time – tDHO Full 100 nS
Setup for Start – tSTASU Full 0.6 uS
Hold Time for Start – tSTAH Full 0.6 uS
Setup for Stop – tSTOSU Full 0.6 uS
1. See Explanation of Test Levels section.
2. This is measured at 0.9V. The relationship between clock and data is programmable in 400ps steps
3. UI = unit interval.
4. 12MHz crystal oscillator for default register settings.
I2C data rates of 100KHz and 400KHz supported.

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Figure 2 Timing for Video Data Interface
Figure 3 Timing for I2S Audio Interface
tVSU
Input data:
CLK
Rising Edge tVHLD
VHLD
tVHLD
t
tVSU
CLK
Dual Edge
Input DDR data:
tVSU
Valid Data
Valid Data Valid Data
D(23:0), DE,
HSYNC, VSYNC
D(23:0), DE,
HSYNC, VSYNC
tASU
Audio data:
I2S[3:0],
LRCLK
SCLK
Rising Edge tAHLD
Valid data
R0x0B[6] = 0
tASU
SCLK
Falling Edge
Valid data
R0x0B[6] = 1
tAHLD
Audio data:
I2S[3:0],
LRCLK

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Figure 4 Timing for S/PDIF Audio Interface
Table 2 Absolute Maximum Ratings
Parameter Rating
Digital Inputs (SDA, SCL, DDCSDA, DDCSCL, HPD, PD, CEC) −0.3 V to +5.5 V
Audio/Video Digital Inputs (MCLK, SPDIF, I2S[3:0], SCLK, HSYNC, DE, VSYNC, CEC_CLK) −0.3 V to +3.63 V
Digital Output Current 20 mA
Operating Temperature Range -40°C to +105°C
Storage Temperature Range -65°C to +150°C
Maximum Junction Temperature 150°C
Maximum Case Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other conditions above those indicated in the operational section of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Voltage ratings assume that all power supplies are at nominal levels.
tASU
Audio data:
S/PDIF
MCLK
Rising Edge tAHLD
Valid data
R0x0B[6] = 0
tASU
MCLK
Falling Edge
Valid data
R0x0B[6] = 1
tAHLD
Audio data:
S/PDIF

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4.1 Explanation of Test Levels
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and characterization testing.
VII. Limits defined by HDMI specification; guaranteed by design and characterization testing.
VIII. Parameter is guaranteed by design.
4.2 ESD Caution

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SECTION 5: PIN AND PACKAGE INFORMATION
This section shows the pinout of the ADV7511W 64-lead LQFP package. This section also contains a brief description of the
different pins as well as the mechanical drawings
Figure 5 64-lead LQFP configuration (top view - not to scale)
2
VSYNC
3
SPDIF
4
MCLK
7
I2S2
6
I2S1
5
I2S0
1
DVDD
8
I2S3
9
SCLK
10
LRCLK
12
PVDD
13
BGVDD
14
R_EXT
15
AVDD
16
HPD
11
DVDD
47
46
45
42
43
44
48
41
40
D13
D14
D15
D18
D17
D16
D12
D19
D20
39 D21
37 D23
36 SDA
35 SCL
34 DDCSDA
33 DDCSCL
38 D22
17
TXC-
18
TXC+
19
AVDD
20
TX0-
21
TX0+
22
PD
23
TX1-
24
TX1+
25
AVDD
26
TX2-
27
TX2+
28
INT
29
DVDD_3V
30
CEC
31
DVDD
32
CEC_CLK
64
HSYNC
63
DE
62
D0
61
D1
60
D2
59
D3
58
D4
57
D5
56
D6
55
D7
54
D8
53
CLK
52
D9
51
DVDD
50
D10
49
D11
PIN 1
TOP VIEW
ADV7511W

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Table 3 Complete Pinout List ADV7511W
Pin No. Mnemonic Type1Description
37 to 44,
45 to 50, 52, 54
55 to 62
D[23:0] I Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic
levels from1.8V up to 3.3V. See ▶Figure 2 for timing details.
53 CLK I Video Clock Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
63 DE I
Data Enable signal input for Digital Video. Supports typical CMOS logic levels from
1.8V up to 3.3V.
64 HSYNC I Horizontal Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
2 VSYNC I Vertical Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
14 R_EXT I
Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this
pin and ground.
30 HPD I
Hot Plug Detect signal input. This indicates to the interface whether the sink is
connected. 1.8V to 5.0 V CMOS logic level.
3 S/PDIF I
S/PDIF (Sony/Philips Digital Interface) Audio Input. This pin is typically used as
the audio input from a Sony/Philips digital interface. Supports typical CMOS logic
levels from 1.8V up to 3.3V. See ▶Figure 4 for timing details.
4 MCLK I
MCLK input for SPDIF and I2S audio. (See ▷ADV7511 Programming Guide for
details on the register bit that controls this). .Supports typical CMOS logic levels
from 1.8V up to 3.3V.
8-5 I2S[3:0] I I2S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I2S. Supports typical CMOS logic levels from 1.8V up to
3.3V. See Figure 3 for timing details.
9 SCLK I I2S Audio Clock input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
10 LRCLK I
Left/Right Channel signal input. Supports typical CMOS logic levels from1.8V up to
3.3V.
22 PD/AD I
Power-Down Control and I2C Address Selection. The I2C address and the PD
polarity are set by the PD/AD pin state when the supplies are applied to the
ADV7511W. Supports typical CMOS logic levels from 1.8V up to 3.3V.
17, 18 TxC−/TxC+ O Differential TMDS Clock Output. Differential clock output at pixel clock rate;
TMDS logic level.
26, 27 Tx2−/Tx2+ O Differential TMDS Output Channel 2. Differential output of the red data at 10×
the pixel clock rate; TMDS logic level.
23, 24 Tx1−/Tx1+ O Differential TMDS Output Channel 1. Differential output of the green data at 10×
the pixel clock rate; TMDS logic level.
20, 21 Tx0−/Tx0+ O Differential TMDS Output Channel 0. Differential output of the blue data at 10×
the pixel clock rate; TMDS logic level.
28 INT O
Interrupt signal output. CMOS logic level. A 2 kΩ pull-up resistor (10%) to
interrupt the microcontroller IO supply is recommended.
15, 19, 25 AVDD P 1.8V Power Supply for TMDS Outputs.
1, 11, 31, 51 DVDD P 1.8V Power Supply for Digital and I/O Power Supply. These pins supply power to
the digital logic and I/Os. They should be filtered and as quiet as possible.
12 PVDD P
1.8V PLL Power Supply. The most sensitive portion of the ADV7511W is the clock
generation circuitry. This pin provide power to the PLL clock. The designer
should provide quiet, noise-free power to these pins.
13 BGVDD P Band Gap Vdd.
29 DVDD_3V P 3.3V Power Supply.
PAD GND P
Ground. The ground return for all circuitry on-chip. It is recommended that the
ADV7511W be assembled on a single, solid ground plane with careful attention
given to ground current paths.

ADV7511W HARDWARE USER’S GUIDE
Rev.A
Page 18 of 45 Rev A
36 SDA C
Serial Port Data I/O. This pin serves as the serial port data I/O slave for register
access. Supports CMOS logic levels from 1.8V to 3.3V.
35 SCL C
Serial Port Data Clock input. This pin serves as the serial port data clock slave for
register access. Supports CMOS logic levels from 1.8V to 3.3V.
34 DDCSDA C
Serial Port Data I/O to Sink. This pin serves as the master to the DDC bus. Tolerant
of 5 V CMOS logic levels.
33 DDCSCL C
Serial Port Data Clock to Sink. This pin serves as the master clock for the DDC
bus. Tolerant of 5 V CMOS logic levels.
32 CEC_CLK I CEC clock. From 3MHz to 100Mhz. Supports CMOS logic levels from 1.8V to 5V.
30 CEC I/O CEC data signal. Supports CMOS logic levels from 1.8V to 5V.
1. I = input, O = output, P = power supply, C = control

ADV7511W HARDWARE USER’S GUIDE
Rev. A
Page 19 of 45 Rev A
5.1 Mechanical Drawings and Outline Dimensions
Figure 6 64-lead Low-Profile Quad Flat Pack [LQFP-SW64-2]
COMPLIANT TO JEDEC STANDARDS MS-026-BCD-HD
1
16
17 32 32
49
64 48
33
12.20
12.00 SQ
11.80 10.20
10.00 SQ
9.80
1
16
17
49 64
48
33
PIN 1
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
EXPOSED
PAD
03-16-2010-A
VIEW A
1.60
MAX
SEATING
PLANE
0.75
0.60
0.45
1.00 REF
0.15
0.05 0.08
COPLANARITY
7°
0°
0.20
0.09
VIEW A
ROTATED 90° CCW
1.45
1.40
1.35
0.27
0.22
0.17
0.50
LEAD PITCH
7.50
REF SQ
5.10
5.00 SQ
4.90

ADV7511W HARDWARE USER’S GUIDE
Rev.A
Page 20 of 45 Rev A
SECTION 6: FUNCTIONAL DESCRIPTION
6.1 Input Connections
6.1.1 Unused Inputs
Any input data signals which are not used should be connected to ground.
6.1.2 Video Data Capture Block
The ADV7511W can accept video data from as few as eight pins (either YCbCr 4:2:2 double data rate [DDR] or YCbCr
4:2:2 with 2x pixel clock) to as many as 24 pins (RGB 4:4:4 or YCbCr 4:4:4). In addition it can accept HSYNC, VSYNC
and DE (Data Enable). The ADV7511W can detect all of the 59 video formats defined in the EIA/CEA-861E
specification. Either separate HSYNC, VSYNC, and DE, or embedded syncs in the style of the ITU BT.656, SMPTE
274M, and SMPTE 296M specifications are accepted. The alignment of the data can be defined as left or right justified
or as evenly distribution. In the case of even distribution, the channel data is left-justified in their respective 8-bit
fields. For timing details for video capture, see Figure 2. For complete details on how to set these, refer to the
ADV7511W Programming Guide.
The ADV7511W can accept HSYNC, VSYNC and DE (Data Enable) signals separately or as an embedded data (ITU
656 based) on the data inputs. If using separate syncs and DE is not available, the DE signal can be generated internally
in the ADV7511W.
The tables in section 6.1.2.1 define how the many different formats are accepted on the input data lines.
6.1.2.1 Video Input Connections
The following table is a summary of the input options which are shown in detail in Table 5 through Table 10.
Table 4 Input ID Selection
Input
ID
Bits per
Color
Pin Assignment Table Maximum
Input Clock
Format Name Sync Type
0 8 ▶Table 5 165.0 MHz RGB 4:4:4, YCbCr 4:4:4 Separate syncs
1 8, 10, 12 ▶Table 6 165.0 MHz YCbCr 4:2:2 (even dist.) Separate syncs
2 8, 10, 12 165.0 MHz YCbCr 4:2:2 (even dist.) Embedded syncs
3 8, 10, 12 ▶Table 7 82.5 MHz YCbCr 4:2:2 2X cloc
k
(even
dist.)
Separate syncs
4 8, 10, 12 82.5 MHz YCbCr 4:2:2 2X cloc
k
(even
dist.)
Embedded syncs
6 8 ▶Table 8 82.5 MHz YCbCr 4:2:2 DD
R
(right just.) Separate syncs
6 8 ▶082.5 MHz YCbCr 4:2:2 DDR (left just.) Separate syncs
6 8, 10, 12 ▶Table 10 82.5 MHz YCbCr 4:2:2 DDR (even dist.) Separate syncs
7 8, 10, 12 ▶Table 7 82.5 MHz YCbCr 4:2:2 DDR (even dist.) Separate syncs
8 8, 10, 12 82.5 MHz YCbCr 4:2:2 DD
R
(even dist.) Embedded syncs