ARP 1601 User manual

ARP INSTRUMENTS, INC.
320 Needham Street,
Newton, MA, 02164
617 96&4700
Document Number 9001901
©September 1976, ARP INSTRUMENTS, INC.
The INFORMATION CONTAINED HEREIN IS CONFIDENTIAL AMD PROPRIETARY TO ARP INSTRUMENTS, INC. IT JS
DISCLOSED TO YOU SOLELY FOR PURPOSES OF INSTRUCTION AS TO OPERATION OF THE EQUIPMENT AND
MAINTENANCE AS APPROPRIATE. IT IS NOT TO BE USED BY YOU FOR ANY OTHER PURPOSE, NOR IS IT TO BE
DISCLOSED TO OTHERS WITHOUT THE EXPRESS PERMISSION OF flfip INSTRUMENTS, INC,

TABLE OF CONTENTS
1. INTRODUCTION
1.1 Product Description
1.2 Specifications -.....
1.3 Function Description .........
2rTHEORY OF OPERATION
2. 1Sequencer
22 Quantizer „...
3. CIRCUIT DESCRIPTIONS
SEQUENCER
3.1 Clock On/Off.
3.2 One Shot
3.3 Clock Oscillator
3.4 Randomizer, Skip &Reset
2.6 M-ask Circuit
3.6 Step
3.7 Foci Switch Jack
3.8 Countsr/Latch
3J0 Decoder
3JQ Gate Output ProK&sirtfl .......
QUANTIZER
3.1 1Current Source fit Semitone Shift.
3.12 CV Generator &Scanner ......
2.13 Counter
3.14 Comparator
31 5Sample Control
3,16 External CV Input
4. SEQUENCER TEST POINTS
2
2
3
4
4
.5
.5
,5
.6
.6
.6
.6
.6
.6
.7
7
1
7
7
7
S,9
5. CALIBRATIONS ^.10,11
6, ASSEMBLY^DISASSEMBLY 11
7. BLOCK DIAGRAM 12
8. GENERAL INFORMATION tCOS/MQS Integrated CircuteO ... 13
9rSCHEMATICS &LAYOUTS 7.14,1 5,1 6/1
7
P18,19
10. PARTS LIST 22

SECTION 1INTRODUCTION
1.1 Product Description
The ARP Sequencer, model 1601, is a16 step se-
quential voltage generator, Avoltage jewel slides is
provided for each of the 16 steps to adjust the volt-
age output from 0to +1 0volts. The sequencer may
be used in a"8 X2J1 mode so that outputs 1through
8(bank A) and 3through 16 (bank B] sequence in
parallel. The outputs of bank* Aand Bars prewired
to avoltage quantizer which effectively "rounds
off" the sequencer's voltage to the nearest whole
twelfth of avolt rThis allows precise tuning since all
ARP products are tuned to a1volt per octave stand-
ard (1/12 volt per semitone).
Alow frequency voltage controlled clock governs the
stepping spaod of the sequencer and can be started,
stopped, gated, or speeded up eitner manually or
externally.
Position gates provide aconstant vultagw output1
(+10 v-a<!ts) for as long as the sequencer Is on a
selected position. The position gate outputs are
bused to one cf the position gate outputs (Gate 1,
2. °r 3).
T,2 Specifications
SEQUENCER
Number ofpositions 16
Maximum {unquantized} control
voltage output +12 V
Maximum output votings +14 V
16 X1Mode . . Channels Aand Bare common
8X2 Mode T,.Channels Aarid Bare separate
FlGr1.1 CONNECTIONS TO SYNTHESIZER
Cftw cfnfjfl control to "tune"etdi positten.
I
Step, Reset Start.- Stop and Start/Stop
Jack inputs. .T...Accepts +3 Vto +10 VGate
CLOCK
Type, Voltage Controlled
Puhss Width ,...,10% to 100% (lass Emsec.)
PWM {Putes Width Modulation}
input jack Accepts Dto+IOvofts
Frequency Range .r..... 0.2 Hz. to 100 Hzr
FM Input Sensitivity .2V/QCT me:?,
Chck Output +1 AVpulse wave
Wbrm Up Drift 0
QUANTIZER
Function "Rounds off" voltages to
nearest 1/12 V(semitone)
Maximum input Voitage (A &B) +1 0 V
Maximum Quantized CV
Output (A A8) +2V
Range ,.P..,...... 7octaves
POWER REQUIREMENTS
Line Voltage 100 to 130 VAC
Uns Frequency. .T,.t..+.,.,L . &0--60 Hz,
Power 20 Watts

1.3 Function Description
^
f[Xarp Sequencer i+
.n^=nd^rn=n=n=[]=R=Rin=r:=3==r^g5
n^:-r.: -r: -d-z-d-b G-z-b-z-u-G-ii-ds
Lr- -:J-
1iiii ii I) i- d- II-
•r. -n. .[|-
'•! 'I
-0- I-I,
©©©©
>'• i+5E -X
I—I*
fe1
-T-ilt t:
'll
18 15 .14 \12 11
13
1Position G*ta Atsignmen rSwitch*!-:
Supplies a+14 Wilt gatE to Orte of ihrte
(bused ioutputs.
2Foot Swfit/F iftput: (Poar Panel) sop-
pli =4 a+14 Vfljt gal* to tfo "Poet Switch
Out" jack ©n the front panel.
3Fojitiori Gtte t\ts Outputs: +14vofa. gate
output* whhch are usually connected to
external envelope h; nerJtCin;.
4Pwippn JOutput: Supplies 3+14 volt
gaa? on position 1(only) to synchronize
additional sequencers or synthesizers,
5Clocked Gate Out
:
Allcws the seledioft
of particular position gates (Gate Bin 1)
with control of the pub width Ickcf).
6CitKk Out: S^jpIki.L a+14 vail clock
pulse which can trigger external enwbpe
genererton.
7Qyuntized CV Cru(fwtr.Prou,iriei acen-
tred voltage in 1^12 volt increments (0 to
+2 vult rangjij which controls the pitch
of external oscillator;. The Aand 6out'
purs i~e Common in th; 16 X1mode,
bur separate in tfie BX2mode,
8Cl/ /n: Allows external control vcftages
(from akeyboard for example] to be
summed with the sequWHMf'i voyage to
shift the key in which the sequencer
plays.
9Ouflnria*T inputs: Allows voltages lo be
i<t|ijantizBtfr+ {rounded to neaptist lit?
veil], Prtpitchad to the sequencer out-
puts.
10 Se^iWNtfi] Outpufy: Provkfiis i0to +10
volt anQ-iog control voltage,
11 Common CQRVBffieftcff jtckn.
12 Putsb Width: Verbs the pulse width of
the clock.
13 GoCJk FKt: Alkaws OHlHmal Control veft'
agts tq increase the speed of the dock
(prewired Ip Gota Buq 1J.
14 Clock Frequency: Miruslly varies the
clock rate from _2Ha toapprux. lOG Hz.
15 SfartJStop: Alternately starts and stops
the sequencer.
16 Trig/Gate Switch: Trigger mode ejTIows
the sequencer lo tie triggered" co. In
tho Caii? mode, the sequencer it or
white the stort button Is held.
17Fxtanjjffy sOvtt UrewpaflEffir,
IS ErternoMy ttsps f?V stpuencer.
19 Step: Advances die sequencer to the
next positMm.
20 flAtr; RhjpHthe p(|uMtrr tq position
1IsaquontiaJ mode only I
.
S&ipiVttsrt: AlkHH particular p.-ositVpns
(from gate bus 3| to either skip past or
reset on petkular positions.
\jUftk: AIBow&clock
to advance to eacto successive position or
advance toe random poutkm.
Uodt Switch; Steps the sequencer 16
tJmasrOr step* bedy Aend B3time; in
pwilhri.
tfDr,1(Light Emitting DiodSii) Indicates
wfcich position ij ok
Pmftiun Tuning Sinters; TurM individual
position; (pdj Lists CV level].
3

SECTION 2THEORY OF OPERATION
2.1 Sequencer
The heart gf the sequencer is the Counter/Latch
circuit which produces a four bit binary number.
When initially reset, the output of the counter
is 0000 (Position 1code), or zero. Each time the
counter receives apulse from the Masfc circuit, the
counter advances to the next binary number (0001
„
0010, 0011, 0100 ..1111). The highest binary
number, 1111, corresponds tn position T6.
This code &ttjpplied to the Decoder circuit which
decodes the binary numbsr to one of 16 outputs. For
example, when the code 0000 is present on the
output of the counter, the decoder will turn on the
position 1output (only); when tha code 0001 is
present on the output of the counter, the decoder
will turn on only the position 2output, etc*
When in the "8 X2" mode, athree bit code is
supplied fmm the counter instead of four. Positions
1through 3and 9through 16 in the Decoder circuit
simultaneously decode ;that bant A(1-8) and
B(9-16) sequence in paraileL
The Voltage CortroLled Low Frequency Clock
determines whan the counter is advanced to
the next position by pulsing aone shot circuit.
The one shot in turn supplies aputae to the Mask
circuit which advances the counted and disables
(masks) the gate outputs during the count advance.
When the sequencer is in the random mode, the
Randomizer circuit advances ihe counter at an
extremely high frequency. For each cycle of the
low frequency clock, aposition number on the
output of the counter is memorized and held until
the next clock pulse. Since the counter is being
advanced so fast, the position numbers which are
memorized will be random.
2.2 Quantizer
Vantages whidi are to be quantized to the nearest
whole twelfth of avolt are applied to the "A" or
JH 8" input of the quantizer.1One quantizer circuit
is multiplexed by switching between one of the two
inputs (A and B) to provide two independent quan-
tized control voltage outputs. The voltages ere
quantized and stored extremely quickFy, s# that
two different voltages are quantized (one atatime)
faster than can be detected by the ear. As £n a
standard keyboard, aresistor chain of equai value
registers make up avoitage divider to generate a
voltage reference. The voltages produced by this
reference CV generator are 0volts, 1/1 2V, 2/1 2V,
3f12V.„2V (2 octave range). Ahigh frequency
OidH-ator step's acounter which enables the CV
generator voltages to be "scanned" one at a time
(0 volts to 2volts).
The input ugftage which is to be "quantized" is
compared to the reference CV on the scanner output;
if the scanner output is lower ihan the Input voltage,
the counter advances until the scanner voltage Is just
higher than ihe input voltage^ The counter ethen
stopped (by the Comparator circuit) end the voltage
pn the output of the scanner is memorized. The
counter is then reset to zero so that the voltage on
other input may be quantized next.
SEQ/RA^D, SWITCH
{IN SEQUENTIAL
PosmoN)
FIG. 2. 1SIGNAL FLOW
aac
DECODER
OOOOOOO
zaase“i
"
t'
ABC Q
DECODER
1C 11 IS 13 14 IS 16
POSITION OUTPUTS (DRIVES LEDS ACV SLIDERS)

FIG, 2.2 SEQUENCER OUTPUTS
SECTION 3CIRCUIT DESCRIPTIONS
3.1
Ctarit Od/Ofif
Gate signals applied to the start jack set the Qoutput
of Z2B to logi:: 1(+15 vqlts) end Qbar to logic 0
(0 volts). Gate signals applied to the stop jack set
the Qoutput of Z2B to logic 0and tho Qbar to logic
1rEach tirne agate signal is applied to the start/stop
jack or when the start/stop button Is depressed, the
Ooutput of Z2B assumes the logic tevel of the Qbar
output so that the Qand Qbar outputs reverse state.
Wien the Gate/Trigger switch (52) is in the gate
position, the Qoutput will assume alogic 1state for
*5 Jong as &gate hi present on the start/stop jack.
Summary: For sdock 'JonJ'state, the Qoutput of
Z2B {B point) will be alogic 1, For aclock "off"
state rthe Qoutput is alogic 0.
3.2 One Shot
A4millisecond pu>sO occurs on the Goutput of
Z11A when pulsed on the Ainput (pin 5). The
pulse on tiiB output of the on* shot is supplied to:
1} thi* Clock Oscillator to reset the sawtooth: 2) the
Reset circuit to lengthen the external reset pulsa (If
appJisdJ the Epoint is at alogic t; end 3}
the Randomizer circuit to momentarily disable the
high frequency oscillator |random mode only).
3.3 Clock Osdiltator
Three circuits comprise the Clock Oscillator: the
Voltage Controlled Oscillator, Sawtooth to Pulse
Converter, and Comparator.
-
Sawtooth Oscillator: Voltages from the dock FM
input jack and the dock rate siider are summed on

the base of Q4. G4 and Q5 are alinear voltage to
exponential current converter. Capacitor C7 is
inftiaily charged to -I- 15 volts and discharges toward
ground through 05rZ3A and Q7 follow the voltage
level on C7 and supply it to the comparator and the
sawtooth to pulse converter. The output of tha
comparator {pin 13, 8) will switch to +15 volts (logic
1) when the sawtooth voltage falls below +7,5 volts.
The comparator output is supplied to the one shot
which reset capacitor C7 to +15 volts.
Sawtooth To Pulse Converter: Voltages from the
Pulse Width Modulation jack and the Pulse Width
slider are applied to ZAA and Z4B to set the dock
pulse width. The collector of 08 will be apulse wave
with apulse width from 20% to 100% depending on
the position of the pulse width slider. The pulse
output of the c&oc< oscillator te routed to the Gate
Output Processing circuit (schematic 2 L
3.4 Randomizer, Skip &Reset
ZHB is ahigh speed oscillator (approx. 5microsecj.
Whan Z16A pin 3is aIggk: 1, Z1IB produces ahigh
frequency pulse chain &n pin 9. When Z16Z pin 3is
at a logic 0(ground) Z11B stops oscillating. With
slide switch S21 in the Random pcsftkm, Z1QC pir>
10 will enable (turn on) the high speed oscillator
(Z1 1B) through Z16A. Z11B will then provide a
pulse chain to Mask circuit. When pulsed by the
clock oscillator, the one shot will moflnentariiy turn
off the high speed oscillator through ZtOC (pin 12 &
13) to allow the lertch in the Counter/Latch circuit to
memorize a(random) position, Dur ng this mode,
Z7B generates random voltage levels to 'iary tha fre-
quency of ZllB to insure arandom sampling of
positions. With S21 in the Sequential moderZlGC
will not affect the frequency of the high speed
oscillator* When S22 Is in the skip position, pin B
of Z9C is at logic G. When the Jpoint is also at a
logic 0, Z9C pin 10 then turns an the hqh speed
oscillator which quickly advances rhs sequencer
to the next position (via £16C),
In the reset position, the gate signal on the Jpoint
is supplied through S22 to Z9D. When tha Jpoint
is at logic 0, Z9D supplies alogic 1which resets the
counter to position Ivia Z16B. External reset gates
may be applied to Q27 and hy deposing the reset
push button (S23).
3.5 Mask Circui t
Z15A pin 3is bogie 1when the sequencer is In the
"sequential" mode which allows the latch (ZB) in
the Counter/Latch circuit to transmit data con*
tirmously. When pin 3of Z15A ss logic 0, (random
mode only) ZB in the Counter/Latch circuit holds or
stores the data on the counter output.
The one shot pulse will cause the Qand Gbar out-
puts of Z2A to momentarily reverse state. The
output of the high speed oscillator (Z11B) and the
Gbar output of Z2A are then combined on Z10C
which advances the oounter in the Counter/ Latch
circuit. A"mask" pulse is generated by combining
the one shot putaa (4 msec, duration) and the pulse
from Z2A (8 mEcrosac, duration) or the output of
Z1&B (pin 4) to turn off all the gate outputs during
the time the counter is advanced from one position
to the next.
3.6
Step
When gate signals are applied to the step jack or frem
the step push button, 26A pin 3provides apulse to
the One Shot circuit and the Gats Output Processing
circuit.
3*7 Foot Switch Jack
The foot switch jack on the front panel provides a
+1Q volts gate for as long as the foot switch is held
and can be patched to any of the input jacks on the
front panel
3,8 Counter/Latch
Z7A kadivide by 16 counter providing a4bit coda
to ZE. Z8 Is alatch circuit but normally transmits
data to the Decoder circuit unaffected, Z9B and Z9A
are connected to the Qand Qbar outputs of ZB to
enable Z13 and Z14 in the Decoder circuit one at a
time (sequentially).
3.9 Decoder
Z13 and Z14 decode the binary number from the
Latch circuit tc one of 10 positions, WhenS4B is in
the 16 X1mode, Q1 1through 26 will turn on one at
atime sequentially (1 through IB). In the 8X2
mode, Z)3 and Z14 decode in parallel (position
1-3 and 9-16). in the random mode, the counter
advances at th-s rate erf the high Speed Oscillator
(ZltB, schematic 1) but in this mode, Z8 holds
the code which Is supplied to the decoders constant.
The strobe input of the Z8 allows arandom binary
number to be memorized on each dock pulse which
is supplied to the decoder.
Ql 1and Q26 are turned on one at a time and supply
voltages to one of the three gate bus lines through the
three posrtlao gate switches. At the same time, the
LED is lit indicating which position is on. The three
position slide switches provide the path to ground
for the LEDs,
S

The voltages from the decoder chips are also supplied
to 10QK Sliders (R57 through R103) til provide a
variable voltage level (Q to -MOV) for each position.
Voltages -from the Abank sliders and the Bbank
sliders are summed in the output amplifier circuit
21 9A and ZlSA. When ihe sequencer is in the 16 X
1position, the Output of the Aand 6channels are
summed together so that the cutputs of Z19B and
21 SB will be tlw same. The Sequencer output
voltages supplied by the output amplifiers are routed
to the quantizer (schematic 3|.
3.10 Gate Output Processing
Gate Output Processing circuit provides 6outputs:
Gate Bus 1, Gate Bus 2, Gate Bus 3, Clocked Gate
TrClock Output, and Position 1Output,
The Gate Bus 1,2, and 3outputs are driven from the
3position slide switches in the Decoder circuit.
Z15C and Z15D are aflip-flop which supplies the
Clocked Gate 1Output and turns on the clock
indicator fCR22). The position Toutput
obtains fts signal from Position 1(01 7base) in the
Decoder circuit so that more than gno- sequencer
can he synchro nized.
QUANTIZER
3J 1Current Source &Semitone Shift
Z29A supplies constant current through 13 equal
vafue resistors (lOOohm) located in resistor pack
220. The voltage drop across aach resistor is 2/12
of a volt Itwo semitones, or one whole tone). 036
supplies an offset voltage to pin 3of 229A to "shift"
qr raise the Output of the current source (and thete-
fore pins 1ihrcugh 14 of 2201 up T/T2 of a volt.
3/12 CV Generator &Scanner
Z2t and Z22 sre digitally controlled analog switches
which are connected to the CV generator outputs
(220), The three binary inputs (A, Band C) select
ono of eight switches to be turned on and connect an
input (pins 13, 14, IB, T2 r1, 5, 2, or 4) to the output
(pin 3). All of the switches are off when alogic 1is
on pin 6(inhibit). The ArBand Cinputs of 221
are driven by 225,
3.13 COUNTER
225 generates abinary number which "counts'1from
OOOOO to 11111, The first hit (MSB) inhibits either
221 or 222 so that only cne voltage from Z2Q is ewr
on at tho jams time. The next three bits (pins 6, 9,
and 11 of 220) turn on channels 13, 14, 15, 12, 1
etc. ore at atime sequentially. The remaining
bit (L5B> on the Counter output (pin 12) is supplied
to tfcfi Current Source to shift the resistor chain level
up 1/72 of avalt to qbta. ntwo voltage levels per
resistor in Z2Q,
3.14 Comparator
The scanner output (Z29B pin 7} is supplied to the
inverting input of the Comparator (223). An
external control voltage which is to be quantized
is supplied to the nrminverting input of ths Compara-
tor via the Input Channel Sriector,
Initially, the Comparator output is logic 1(+15 volts)
which permits the counter to be advanced by the
Clock through Z240. As the Counter advances, the
voltage on pin 2 of 223 "steps" in t/12 volt incre-
ments until it exceeds the voltage level on pin 3of
223. The output of the Comparator then changes
to logic 0which immediately stops the Counter, The
voltage on the Scanner output (now constant) is the
nearest 1/12 of avolt level to the input control volt-
age; therefore, it is supplied to the Channel Memory
via Z30C to be stoned.
3*15 Sample Control
Z30C ls enabled when the Sample Control provide.;
alogic 1to the clock input of Z2SA then
turns on one of the transmission gates (either channel
Aor B) for atime period of half aclock cycle, Afte*J
the quint zed control voltage from Z29C has been
supplied to one of the memory circuits, Z27C resets
both the Sample Control and the Counter. Addi-
tionally, the outputs of Z2SA reverse state to switch
from one channel to the other (A to B for example).
The Quantizer is now reidy to quantize the voltage
wailing on the other input.
3*16 External CV Input
The External CV input allows acontrol voltage from
another synthesizer to be summed wfch the output of
the two Quantizer circuits. The keyboard CV of
other instruments can be added to the sequencer's
voltage to change the key in which the saquencer
plays simply by playing an external keyboard.
77to points on the f
offowing two pages fifusfrete
tfw operation of tfre circuit in the sequencer in
rotation to one another.

SECTION 4SEQUENCER TEST POINTS
FUNCTION SET UP
TP-1 HIGH FRECL
OSC.
1. Put the SEQ/RAND switch in
the RANDOM mode.
2. Put the SEQ/RANO switch in
the SEQUENTIAL mode.
TP-2
i
CLOCK
ON/OFF
1, Put the TRIG/GATE switch in
the GATE position. Depress the
START/STOP button.
2+Put the TRIG/GATE switch in
the TRIGGER position. Depress
the START/STOP button.
TP-3 ONE SHOT 1.Put the CLOCK FREG. slider at 34.
2. Put all other sliders fully DOWN,
3. Start the Sequencer.
TP-4 CLOCK
SAWTOOTH 1. Put the CLOCK FREQ, slider at %.
2. Put all other slicers fully DOWN.
3. Start the Sequencer.
TP-5 COMPAR
ATOR 1.Put the CLOCK FREQ. slider at %.
2.Put all other sliders fully DOWN.
3. Start the Sequencer.
TP-6 CLOCK
I
!
1. Put the CLOCK FREQ, slider at 34.
2. Put all other sliders fully DOWN.
3. Start the Sequencer.
4. Put the PULSE WIDTH slider
fully up.
TP-7 ONE SHOT LPut the CLOCK FREQ, slider et*.
2. Put all other sliders fully DOWN.
3. Start the Sequencer,
TP-8 MASK
ADVANCE 1.Put the CLOCK FREQ, slider at 34. 2.Put at! other sliders fully DOWN,
3. Start the Sequencer.
TP-9 MASK 1,Put tho CLOC KFREQrsi id*r at 31.
2, Put all other sliders fully DOWN,
3, Start the Sequencer.
Alternates between +15 Vand 0Vwhen START/STOP
is depressed
.
TP-10 ADVANCE 1, Put the CLOCK FREQ, slidar at
2,Put all other sliders fully DOWN.
3, Start the Sequencer.

Th& following test paints ill (Jffi (fre same panel settings:
QUANTIZER
TP-11 02
CLOCK
JZ(1
CLOCK
TP-13 SEM.
SHIFT
SCANNER
A
TP-15 SCANNER
8
TP-16 SCANNER
C
TP-17 SCANNER
TP-18 SCANNER
OUTPUT
NO E: THJt po Inti 11-17 Rid 19-20
are +15 VpuJs* wavB5 r
1.Put thfl SEQ/RAND switch in the SEQUENTIAL position.
2. Put tha GATE/TRIG switch in tbs GATE
3. Put the mode switch in the 6X2position.
4. Depress tne RESET button (position 1LED should be Irt).
E, Put the POSITION 1slider about 1/3 up.
6, Put liie POSITION 9sltier about 2/3 uph
FUNCTION SPECIFICATIONS
120 (Jisc. parlod typlur (f KMz.)
BCV l« (EXAMPLE)
FROM SEQUENCER "
—•A CV IN {EXAMPLE]
.FROM SEQUENCER
TP 19 COMPAR
ATOR
9

SECTION 5CALIBRATIONS
5.1 Sequencer &Quantizer
206 &
207
R226 &
R222
AOFFSET St
GOFFSET
ADJUST
QUANTIZER
CV V/OCT
AMOO ADJUST
BMOD ADJUST
1. Contact apatch cord from INPUT Ajack to INPUT Bjack (Isolates
quantiser inputs).
2. Adjust trimmer R2D6 for 0volts ±.005 Von QUANTIZED AOUTPUT.
3+Adjust trimmer R2G7 for 0volts +.00E Voh QUANTIZED BOUTPUT.
1.Put ell sliders on the sequencer fully DOWN.
2. Put the TRIG/GATE switch In the GATE mode.
3. Put the sequencer mode switch in the T6 X1POSITION.
4. Put the SEC^RAND switch in the SEQUENTIAL position.
&. Depress the RESET button (position 1LED should be lit I
.
6. Put the POSITION 1SLIDER fully UP.
7. Adjust trimmer R26& for +2.00 vote? on the QUANTIZED OUTPUT AJack.
8. Adjust trimmer R222 for +2.00 vofta on the QUANTIZED OUTPUT Bjack.
1„Put all the sliders on the sequencer fully DOWN.
2. Put the GATE/TRIG switch in the GATE made.
3. Put the mode switch im the 16 XfPOSITION.
4. Put the SEQ/HAND switch in the SEQUENTIAL position.
5rDepress the RESET button (position 1LED should be IrtL
6. Connect apatch cord from INPUT A-:acfr: to INPUT BJack (isolates
quantizer inputs}.
7+Monitor Ihe ASEQUENCER OUTPUT with a DVM.
3. Raise the POSITION 1SLIDER to A.
9. Measure and record the EXACT VOLTAGE level on the Asequencer output
(should be near +5 volts).
1
0
rConnect a patch cord from thii ASEQUENCER OUTPUT jack to the
CV iNjack.
11.Monitor the QUANTIZER OUTPUT Awith e DVW.
12. Adjust trimmer R217 for EXACTLY the same voltage as measured in
step 9(unity gain).
13. Monitor the QUANTIZED OUTPUT Bwith aDVM.
14. Adjust trimmer R2T8 for EXACTLY the same voltage as measured In
step 9(unity gain).
10

6,2 Powar Supply
TRIMMER
+5 VOLT SET
15 VOLT SET
trjm procedure
1 „ Monitor the power supply's +15 volt output with adigital voltmeter.
2, Adjust R5 for exactly +15,00 volts.
1.Set R5 (+15 volts) first,
2. Put the digital vctflnneter's ground lead on the power supply's -1 Bvolt output
and put the meter's plus lead on -ha power supply's ground output,
3. Adjust Rll for exactly +15.00 volts (reversed polarity).
SECTION 6ASSEMBLY/DISASSEMBLY
1, To Prevent shock when trouble shooting, unplug
the sequencer and mount the power supply on the
ourtslde rear panel {tee shove //MratfbnJ.
2, To remove the main printed circuit board, remove
11bolts ffitustrat&d above), remove afl slitter knobs
on the front panel, and gently push on the shafts of
the sliders until the board pops loose,
3, To remove the lower jeck board assembly, remove
the jack nuts an tha lower front panel. Then pull the
bottom of the power switch out so that the jack
board clears the power switch (see il/uxtration to
right}.
11

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