the base of Q4. G4 and Q5 are alinear voltage to
exponential current converter. Capacitor C7 is
inftiaily charged to -I- 15 volts and discharges toward
ground through 05rZ3A and Q7 follow the voltage
level on C7 and supply it to the comparator and the
sawtooth to pulse converter. The output of tha
comparator {pin 13, 8) will switch to +15 volts (logic
1) when the sawtooth voltage falls below +7,5 volts.
The comparator output is supplied to the one shot
which reset capacitor C7 to +15 volts.
Sawtooth To Pulse Converter: Voltages from the
Pulse Width Modulation jack and the Pulse Width
slider are applied to ZAA and Z4B to set the dock
pulse width. The collector of 08 will be apulse wave
with apulse width from 20% to 100% depending on
the position of the pulse width slider. The pulse
output of the c&oc< oscillator te routed to the Gate
Output Processing circuit (schematic 2 L
3.4 Randomizer, Skip &Reset
ZHB is ahigh speed oscillator (approx. 5microsecj.
Whan Z16A pin 3is aIggk: 1, Z1IB produces ahigh
frequency pulse chain &n pin 9. When Z16Z pin 3is
at a logic 0(ground) Z11B stops oscillating. With
slide switch S21 in the Random pcsftkm, Z1QC pir>
10 will enable (turn on) the high speed oscillator
(Z1 1B) through Z16A. Z11B will then provide a
pulse chain to Mask circuit. When pulsed by the
clock oscillator, the one shot will moflnentariiy turn
off the high speed oscillator through ZtOC (pin 12 &
13) to allow the lertch in the Counter/Latch circuit to
memorize a(random) position, Dur ng this mode,
Z7B generates random voltage levels to 'iary tha fre-
quency of ZllB to insure arandom sampling of
positions. With S21 in the Sequential moderZlGC
will not affect the frequency of the high speed
oscillator* When S22 Is in the skip position, pin B
of Z9C is at logic G. When the Jpoint is also at a
logic 0, Z9C pin 10 then turns an the hqh speed
oscillator which quickly advances rhs sequencer
to the next position (via £16C),
In the reset position, the gate signal on the Jpoint
is supplied through S22 to Z9D. When tha Jpoint
is at logic 0, Z9D supplies alogic 1which resets the
counter to position Ivia Z16B. External reset gates
may be applied to Q27 and hy deposing the reset
push button (S23).
3.5 Mask Circui t
Z15A pin 3is bogie 1when the sequencer is In the
"sequential" mode which allows the latch (ZB) in
the Counter/Latch circuit to transmit data con*
tirmously. When pin 3of Z15A ss logic 0, (random
mode only) ZB in the Counter/Latch circuit holds or
stores the data on the counter output.
The one shot pulse will cause the Qand Gbar out-
puts of Z2A to momentarily reverse state. The
output of the high speed oscillator (Z11B) and the
Gbar output of Z2A are then combined on Z10C
which advances the oounter in the Counter/ Latch
circuit. A"mask" pulse is generated by combining
the one shot putaa (4 msec, duration) and the pulse
from Z2A (8 mEcrosac, duration) or the output of
Z1&B (pin 4) to turn off all the gate outputs during
the time the counter is advanced from one position
to the next.
3.6
Step
When gate signals are applied to the step jack or frem
the step push button, 26A pin 3provides apulse to
the One Shot circuit and the Gats Output Processing
circuit.
3*7 Foot Switch Jack
The foot switch jack on the front panel provides a
+1Q volts gate for as long as the foot switch is held
and can be patched to any of the input jacks on the
front panel
3,8 Counter/Latch
Z7A kadivide by 16 counter providing a4bit coda
to ZE. Z8 Is alatch circuit but normally transmits
data to the Decoder circuit unaffected, Z9B and Z9A
are connected to the Qand Qbar outputs of ZB to
enable Z13 and Z14 in the Decoder circuit one at a
time (sequentially).
3.9 Decoder
Z13 and Z14 decode the binary number from the
Latch circuit tc one of 10 positions, WhenS4B is in
the 16 X1mode, Q1 1through 26 will turn on one at
atime sequentially (1 through IB). In the 8X2
mode, Z)3 and Z14 decode in parallel (position
1-3 and 9-16). in the random mode, the counter
advances at th-s rate erf the high Speed Oscillator
(ZltB, schematic 1) but in this mode, Z8 holds
the code which Is supplied to the decoders constant.
The strobe input of the Z8 allows arandom binary
number to be memorized on each dock pulse which
is supplied to the decoder.
Ql 1and Q26 are turned on one at a time and supply
voltages to one of the three gate bus lines through the
three posrtlao gate switches. At the same time, the
LED is lit indicating which position is on. The three
position slide switches provide the path to ground
for the LEDs,
S
