Atari SM194 User manual

SMI 94
Technical Manual
Februari 199

TABLE OF CONTENTS
Subi ect Section
Scope 1
General Description '2
Electrical Characteristics 3
Display Performance 4
Controls 5
Options 6
Mechanical Description 7
Environmental Performance 8
Agency Compliance 9
Interface 10
Theory of Operation 11
Appendix:
Figures
Block Diagram
Trouble Shooting Chart
Schematics
\
-^

VCX SERIES MONITORS
)
1.0 SCOPE
This document describes amonitor series that covers arange
of horizontal scan frequencies and includes options to
satisfy requirements in awide variety of applications.
2.0GENERAL DESCRIPTION
The monitor series is supplied with a20-inch diagonal tube
with a114 degree deflection. (15", 17" and 24" CRT's are
available.
)
The monitor can be custom configured for any horizontal scan
frequency from 32 KHz to 128 KHz, and for vertical field
frequencies from 49 Hz to 120 Hz.
The specific values included in this document are for a
typical monitor operating at a66 KHz horizontal scan rate.
Other scan rate information can be obtained by consulting
OEM sales or application engineering.
3.
0
ELECTRICAL CHARACTERISTICS
90 to 137 VAC or 180 to 264 VAC
47-63 Hz
64 Watts
40 Amps peak at 120 VAC
60 Amps peak at 220 VAC
3.1
Power Supply:
Input Voltage
Power Frequency
Power
Inrush Current
C
)
3

3.2.1 Horizontal Sync:
Polarity Negative, edge
(Positive Optional)
Signal Level TTL
Signal rise/fall TTL
Pulse Width. 0.5uSec (min) to 50% of
total horizontal scan
time
Input Impedance typical 100 Ohms
Frequency 32 KHz to 128 KHz
Blanking 3.0uSec (min)
TYPICAL: Vertical Timing
4

3.2.2 Vertical Sync:
Polarity
Signal Level
Signal Rise/Fall
Pulse Width
Input Impedance
Frequency
Blanking
3.2.3 Video Signal Input
Polarity
Signal
Input Impedance
Negative edge (Positive
Optional)
TTL
TTL
40-400 uSec
typical 100 Ohms
49 Hz to 120 'Hz (Inter
lace Optional)
450 uSec(min)
Requirements
Positive is white
(Negative Optional)
1Bit ECL Differential
Typical 75 or 100 Ohms
4.
0
DISPLAY PERFORMANCE
4.1
Input Conditions:
Character
Brightness
Contrast
Viewing Direction
Viewing Distance
Ambient Temp.
Supply Voltage
Warm up time
Display size
4.
2
Video
:
Rise/Fall times
<«§»
At raster cutoff
White level input video
should be set to result in 30
Foot-Lamberts in P4 or equiva-
lent setting.
Along the CRT neck axis
18 inches
25 degrees C
120 VAC
20 minutes max.
14 x11 inches +/- 0.1"
3.5 nsec Max. (10% -90%)
4.3 Horizontal: '
Video blanking 3.0 uSec Horizontal (Min.
)
Horizontal Scan Delay 0-4 uSec Adjustable Phase
Control
4.4 Vertical:
Video blanking
5
450 uSec Vertical (Min.)

A--B =0.07 inches max
4.5.5 Center Bow:
0.07 inches max

4.5.6 Linearity
Using the above pattern, the linearity shall be
better than 7% vertically and better that 9%
horizontally.
Resolution: 1300 Lines min. at 10 Ft-L
P104 phosphor and standard 48%
Transmission glass
4.7 Light Output: 30Ft-L min. with max settings
4.8 Display Stability:
4.8.1 Jitter:
4.8.2
Jitter and Swim resulting from Monitor
Generated Sources: Radiated power line
interference of 0.005 inch max., down to a
frequency of 47 Hz.
Interference from other nonsynchronous
sources shall not produce more than 0.003
inches of jitter on the display.
Turn on Drift:
Aft$r a 10 minute warm-up, the periphery of
the -display shall not drift more than 0.10
inches in any direction. During the 10
minute warm-up, the display shall not "wrap
around" the raster.

4-8.3 High Voltage Regulation:
With an all white active display-, dimensions
shall not change by more than 0.5%, when
going from 2Ft-L to 30Ft-L light output
(ref. P104 phosphor)
.
4.8.4 Black Level Stability:
When changing the data pattern from 5%
Average Picture Level (APL) to 100% APL, the
reference black level will stay constant with
2%.
5.0CONTROLS
5.1 User:
Brightness
Power Switch
Contrast (Available on Grey Scale Units)
5.2Internal
:
Contrast
Brightness
Horizontal Centering (Phase)
Horizontal Size
Horizontal Linearity
Vertical Size
Vertical Linearity
G2 Bias
Static Focus
Vertical Dynamic Focus
Horizontal Dynamic Focus
6.0OPTIONS
6.1Video
:
TTL 1to 3Bits
ECL 1to 3Bits
Analog Composite Video, RS343A
6.2Phosphors
:
P104 standard
All phosphors available as options

6.3 Anti-Reflection Treatment:
Fine Etch or Polished is standard
Bonded quarter wavelength optical coated panel
available as options
6.4 Orientation Format:
Landscape and portrait with horizontal scan in Long or
Short dimension
6.5 Controls:
Remote contrast
LED Power indicator
6.6 Power:
ECL Supply: -10.0VDC nominal §500 ma
)10

7.0 MECHANICAL DESCRIPTION OF OPTIONAL CABINET WITH TILT-SWIVEL
BASE:
Overall Height
Overall Width
Overall Depth
Rear Panel Dimensions
Weight
14.5"
17.8"
15.0"
13.0 X9.5"
'36 Lbs.
(368mm)
(452mm)
(381mm)
(330 x241mm)
(16.4 Kilograms)
8.0
ENVIRONMENTAL PERFORMANCE i
5to 55 degrees C
-40 to 65 degrees C
5% to 95% noncondensing
10.000 Ft. max.
40.000 Ft. max.
Vibration:
Operating Temperature (in box)
Storage Temperature
Humidity
Operating Altitude
Nonoperating Altitude
Sweep 5-500-5Hz: 0.5g max from 0to 200 Hz, 0.33g max
from 200 to 500 Hz. Duration of sweep is 15 minutes;
then 15 minute dwell on peak resonant at 0.55g.
Shock:
20g vertically, longitudinally and laterally, half-sine
wave with pulse width ll-15mSec.
9.
0
AGENCY COMPLIANCE
The unit is designed to meet the following requirements:
TJL478 Fourth Edition Listed/Recognized
CSA C22.2 No. 154
IEC 380, VDE 0806 GS Mark, and VDE 0871 Class Bin
cabinet
DKHS 21 CFR, Subchapter J, X-Ray Certified
*
FCC Class B,‘Part 15 in cabinet
11

10.0 INTERFACE
AC Power In: CEE-22 Receptacle or AC Safety
Interlock
10.1 Input Signals:
Connector: 9Pin Subminiature D
Typical Pin Assignments
ECL TTL
1. ECL Video TTL Video
2. ECL Video Return (GND) N/C
3.HSync HSync
4. VSync VSync
5. N/C N/C
6. ECL (Not) Video TTL Video Return (GND)
7. ECL (Not) Video Return (GND) HSync Return (GND)
8.Sync Return (GND) VSync Return (GND)
9. N/C N/C
NOTE :Other Pin Assignments readily accommodated
.
10.2 Analog Input:
Analog Input: BNC -RS343A Levels

.0THEORY OF OPERATION
11.1 Deflection Board
The deflection board does several tasks;
i) processes sync
ii) provides horizontal yoke deflection
iii) provides vertical yoke deflection
iv) provides async pulse to the power supply
v) provides the required focus voltage
vi) provides spot burn protection
i. Sync Processing
The 74LS221 U4 is adual non-retriggerable one shot with
Schmitt trigger inputs. Noise is reduced by the hysteresis
in the inputs and the non-retriggered action. Jumper blocks
JR1/JR2 are provided to select the active edge.
The TLC555 U1 is alevel triggered timing device used in
the same mode as U4
.
The leading edge of horizontal sync triggers the one shot
U4 .The end of time out triggers the TLC555 Ul. The second
delay is needed to delay the signal afull line. The end of
time out of Ul triggers Q1 for aduration determined by C18
and R12. The PLL then centers this pulse on flyback. The
data centering potentiometer V10, should be set to center
the video in the raster. The amount and range of delay is
set by R37 ,R68 and V10.
Vertical sync is fed through the one shot Ul to get better
noise immunity, to offer the option of inversion and to
allow some delay for interlace requirements.
ii. Horizontal Deflection
The phase locked loop is used to synchronize the horizontal
switch to the timing pulses from the computer or signal
generator.
The delayed sync 'from Ul is buffered through Q1 with its
pulse width set '(by R12 and C18) and is capacitively
coupled to the PLL, U2. The sync is fed into pin 3of the
MC13 91. This sync pulse determines when U2 (MC1391/PLL)
samples the ramp waveform generated by the yoke and
available to pin 4of U2. The ramp waveform is capacitive-
ly coupled to U2. If the sampling occurs at different
positions on the ramp at pin 4, an ’error voltage is
generated at pin 5. The error voltage is connected to pin 7

through alow pass filter. Pin 7is the timing input of U2
,
therefore the error voltage created by the phase or
frequency difference between the flyback and sync signals
controls the oscillator. See figure 1for waveform details.
The free run frequency of U2 is determined by VI, R19 and
Cl. The duty cycle of U2 is determined by R16. and R17
.
The output is pin 1which determines the drive of the FET
Q3 .The FET Q3 is normally on until U2 pulls the gate low
and shuts off Q3
.
The switching of Q3 drives the horizontal output transistor
Q7 through acurrent transformer. When Q3 is turned on, Q7
turns off. The Baker's clamp D23 is an optional component.
On the right hand half of the screen, transistor Q7 is
conducting current through the deflection yoke to -ground.
This current is provided by the "S" correction capacitor (s)
C25 (C44 ),which has acharge approximately equal to the
supply voltage. The damper diode DIO allows current to
flow from ground through the deflection yoke to C2 5giving
the left hand half of the screen.
The flyback capacitor (s) C2 4(C43)
,
connects the hot side of
the yoke to ground. This component determines the size and
length of the flyback pulse.
The "S" shaping capacitor(s) C25 (C44) is used to correct
linearity since the CRT face has alarger radius of
curvature than does the deflecting electron beam. The
capacitor (s) corrects the outside versus center of screen
linearity. There is aDC voltage equal to the supply
voltage plus aparabolic voltage with apeak to peak value
of 35 to 90 volts depending on the setup. If the value of
C25 is reduced this parabola will increase, reducing the
size of the outside characters with respect to the center
characters
.
Left versus right linearity is controlled with the linearity
coil L2. This is a saturable coil in the path of the yoke
current. Like the size coil, any inductance in series with
the yoke will reduce the size of the picture. This
saturable coil will change inductance with amplitude and
direction of current flow through it. In this case at the
start of atrace 'the linearity coil has an inductance of
20% of the yoke. By the center of the trace, the linearity
coil inductance has decreased to about 5% of the yoke where
it remains for the rest of the trace. This variable
inductor should be adjusted so the right and left sides of
the picture are the same size.
14

Horizontal centering is done with the dual variable coil
LI. These two 'variable inductors are in one unit and are
connected from the supply voltage to the cold side of the
yoke. In conjunction with Dll and D12 one inductor is
connected for the right half of atrace and the other
serves the left half. If the two inductors are equal (when
the slug is in the center, or removed completely) ,then the
average current flow is zero and the picture is not shifted.
If there is an imbalance in inductance then there will be a
net flow causing the picture (raster included) to shift
position on the screen.
iii. Vertical Deflection
The TDA1670 incorporates all the necessary functions for
providing the yoke with the current required for vertical
deflection. Incorporated in silicon is asynchronizable
oscillator, ramp generator, voltage regulator, voltage
doubler and power amplifier.
The oscillator is an integrator (pins 4to 3) and atwo
threshold comparator which switches pin 6high or low to
allow the charging of C8. D3 allows the charge and
discharge ramps to have adjustable slopes. Vertical sync
pulses come in on pin 5. See figure 2.
The ramp generator is made up of acurrent generator,
controlled by current .through pin 7, and the capacitor C12
from pin 9to ground. The slope and thus the size of the
linear ramp is adjustable by setting the current pulled from
pin 7through V3 .This ramp also appears buffered on pin 10
at amuch lower impedance.
The power amplifier, with input on pin 12, sums the ramp on
pin 10 with the current ramp through the yoke. R31 and C14
stabilize the high gain power amplifier. Yoke current flows
from pin 1, through the yoke, the DC blocking capacitor
CIS, and the current sampling resistor R33 to ground.
Voltage which represents yoke current is then fed back to
the input of the amplifier to be compared with the referen-
ce.
The output stage of the power amplifier is supplied by the
25 volt supply during the trace, and by the flyback
generator circuit during the retrace. The internal clock
turns off the lower output stage to start flyback. The power
output stage is thermally protected by sensing the junction
temperature and shutting off the current source of the power
stage.
15

The DC bias point is maintained by the divider R34, R32 and
R33. Capacitors C16 and C15 find the average output
voltage. This voltage is then fed back into the input of
the buffer amplifier where it is compared to areference.
Any difference in these two voltages causes the DC bias
-point of the power amplifier to self-adjust.
In order to obtain sufficiently short flyback times, a
voltage greater than that required during scan must be
applied to the yoke. The flyback generator, during
flyback only, supplies (to the power amplifier) avoltage
equal to double the supply voltage. Pin 15 charges a
capacitor C9, up to the supply voltage during trace and
then sets this capacitor on top of the power supply during
retrace, thus doubling the available voltage.
Vertical linearity adjustments interact with size adjust-
ments. The ramp from pin 10 is subtracted from the ramp
across R33 and the results are fed back to the size input,
pin 7of the TDA1670.
Vertical "S" shaping is done by using the TL43T (U9) and C21
with R3 8as an integrator.- The vertical ramp across R3 3
integrated becomes the vertical parabola on the output of
U9 .This parabola is fed back to the vertical size input,
pin 7of the TDA1670 and compensates for "S" distortion.
The parabola is also used to drive the vertical focus
modulator. Diode D6, resistors R38, R39, R40 and capacitor
C17 develop abias voltage.
Vertical centering is accomplished with acurrent source
or sink. If V5 is adjusted so that it is acurrent sink,
then the picture (raster included) will move up the screen.
If V5 is adjusted so that it provides current, then the
picture will move down the screen. Potentiometer V5 should
be set to center the data, not the raster ,on the screen.
-iv. Power Supply Sync
The power supply is synchronous with the horizontal
deflection in order to reduce the switching noise. This is
accomplished by sending astepped down version of the
horizontal flyback pulse by sampling the pulse on the
blocking inductor T2.
v. Focus Modulation
Each section of the CRT screen focuses at adifferent
voltage. The center of the screen may require several
16

Horizontal centering is done with the dual variable coil
LI. These two variable inductors are in one unit and are
connected from the supply voltage to the cold side of the
yoke. In conjunction with Dll and D12 one inductor is
connected for the right half of atrace and the other
serves the left half. If the two inductors are equal (when
the slug is in the center, or removed completely) ,then the
average current flow is zero and the picture is not shifted.
If there is an imbalance in inductance then there will be a
net flow causing the picture (raster included) to shift
position on the screen.
iii. Vertical Deflection
The TDA1670 incorporates all the necessary functions for
providing the yoke with the current required for vertical
deflection. Incorporated in silicon is asynchronizable
oscillator, ramp generator, voltage regulator, voltage
doubler and power amplifier.
The oscillator is an integrator (pins 4to 3) and atwo
threshold comparator which switches pin 6high or low to
allow the charging of C8. D3 allows the charge and
discharge ramps to have adjustable slopes. Vertical sync
pulses come in on pin 5. See figure 2.
The ramp generator is made up of acurrent generator,
controlled by current .through pin 7, and the capacitor C12
from pin 9to ground. The slope and thus the size of the
linear ramp is adjustable by setting the current pulled from
pin 7through V3 .This ramp also appears buffered on pin 10
at amuch lower impedance.
The power amplifier, with input on pin 12, sums the ramp on
pin 10 with the current ramp through the yoke. R31 and C14
stabilize the high gain power amplifier. Yoke current flows
from pin 1, through the yoke, the DC blocking capacitor
C16 ,and the current sampling resistor R33 to ground.
Voltage which represents yoke current is then fed back to
the input of the amplifier to be compared with the referen-
ce.
The output stage of the power amplifier is supplied by the
25 volt supply during the trace, and by the flyback
generator circuit during the retrace. The internal clock
turns off the lower output stage to start flyback. The power
output stage is thermally protected by sensing the junction
temperature and shutting off the current source of the power
stage.
15

hundred volts less than the top or bottom of the screen,
while the left and right require more.
To achieve the best focus over all, the focus voltage is
modulated with both avertical and horizontal signals. The
vertical parabola developed at U9 drives the emitter of the
common base configured Q5 which is ahigh voltage amplifier.
The collector of Q5 then has ahigh voltage parabola of
vertical frequency.
The horizontal focus parabola is developed from the voltage
on "S" capacitor C25. The parabola developed from the yoke
deflection current at C25 is stepped up through T3 and
added to the vertical parabola at Q5 to provide the focus
voltage.
The autotransformer T3 ,is amultitapped transformer to
accommodate different "S" capacitor waveforms and CRTs. The
focus potentiometer V6, sets the DC focus voltage.
vi. High Voltage Shut Down/Spotbum Protection
If the deflection circuitry, horizontal or vertical, stops
functioning at required frequencies, the- high voltage
supply will be shut down. If Q9 does not receive- asignal
at the horizontal rate, C3 9will charge up and turn Q10 on
which will provide apositive voltage to the remote shut
down pin on the power supply causing the high voltage to
shut down. Likewise, if Q8 does not receive asignal at the
vertical rate C3 8will charge up and turn on Q10 resulting
in high voltage shut down.
11 .2Power Supply
11.2.1 Low Voltage Supply
The design utilizes adiscontinuous flyback topology
operating in current-mode resulting in amultiple output
switcher with outputs which track well. Small or no
output filter chokes are needed and slower diodes can be
used. The fast transient response of the control loop
maintains picture integrity. Very fast current limiting
protects the switeher against short circuit.
The input rectifier section converts the AC line voltage
into acrudely filtered and unregulated DC voltage,
which powers the switching regulator. The input section
is configured as afullwave bridge when operated from
220V line, and as avoltage doubler when .operating from
110V. There is aheader available to select either mode
of operation.

To reduce noise transmission to and from the power line, a
low pass filter isolates the switcher. The conducted noise
is reduced by Xand Ycapacitors and acommon mode
transformer.
3842 (Ul) ,is an integrated current mode pulse width
modulator. It consists of an oscillator, error
amplifier, current sense comparator, under-voltage
lockout and an output MOSFET driver stage. The
under-voltage lockout circuit insures that Vcc is
adequate to make the 3842 fully operational before
enabling the oscillator, voltage reference or output
stage. Turn-on turn-off are fixed internally at 16V
and. 10V respectively. The 6V hysteresis prevents Vcc
oscillations 'during power sequencing.
The oscillator consists of apull up resistor Rll, from
the 5V reference to pin 4and atiming capacitor to
ground. When the voltage ramps up to 2.8V on pin 4, an
internal current sink pulls down, discharging the timing
capacitor to a1.0V level. This level releases the current
sink and starts the next cycle. The free running oscillator
frequency is approximately equal to 1/.55RC.
3842 can also be synchronized to an external clock. This is
achieved by capacitively coupling astepped down signal of
the horizontal flyback pulse through C33 to the timing
capacitor CIO. Noise immunity is enhanced if the free
running frequency of the oscillator is set to be about 20%
less than the clock frequency.
The output stage of the 3842 has asingle totem-pole
output capable of operating to 1A peaks and a200 mA
average current.
3842 utilizes acurrent sense comparator. Current mode
controllers inherently keep .close watch over the pass
transistor's current Ql. Pin 3is connected to avoltage
comparator which shuts off the output when the current in
the primary winding of the power transformer reaches the
desired level, as prescribed by the error amplifier. This
way the controller will only allow the needed amount of
power to be stored in the output transformer.
Current mode control differs from most pulse width
controllers which compare the error amplifier's output
against the oscillator's voltage ramp. This results in
control of on-time, which does not necessarily mirror the
power stared in the transformer.

The current sense comparator also serves the dual purpose of
monitoring current limit. If pin 3rises above IV the
output is terminated. Therefore, output short-circuits and
core saturations should be detected before destroying Ql.
The error amplifier of the 3842 has the inverting input
on pin 2, non-inverting input tied to an internal 2.5 V
reference and an output on pin 1. The voltage on pin 2
is compared to the 2.5V. Errors in output voltage are
amplified and fed to pin 1where they are frequency
compensated by an RC back to pin 2. This error voltage is
internally dropped by 1.4V and divided by 3before being
fed to the current comparator. At the current comparator,
the error amplifier output sets the level at which the
current sensed at pin 3will ramp up to, thereby setting the
amount of energy stored in the power transformer and
therefore, the power at the output.
In this application, an operational amplifier U4, located on
the secondary side of the switcher, compares asingle output
voltage to aregulated reference voltage. Any error in
output voltage is amplified by U4 .The output is frequency
compensated by R24 and C24. Error current is fed through the
optocoupler to the error amplifier of the 3842.
3842 draws very little current in start-up mode. There is
enough power from the line bleeders R2 and R3 to slowly
charge C8 to the '16V needed to start the switcher. When
switching begins, Vcc falls quickly but before it reaches
the 10V shut-off level the auxiliary winding on the power
transformer provides the required power.
As the 3842 starts acycle, it turns on transistor Ql.
This allows current to flow in the primary of Tl. As
current ramps up with time, the voltage .across the current
sense resistor R7 also ramps to apoint where U1 determines
enough power has been stored via the comparator, and turns
off Ql. As the voltage on Ql flies upward, power is dumped
from the main power transformer Tl through diodes into the
different outputs. Primary ringing which could over
voltage Ql, is clamped by D2. Currents from the secondary
windings are rectified and filtered to create the desired
output voltages.
11.2.2 High Voltage Supply
The high voltage power supply is aresonant mode regulator.
The input supply voltage is 25V DC. The 25V input is
regulated down to 15V by U3 .This regulated 15V is divided
down and used as the reference voltage input of the
operational amplifier U4 .The inverting input is the
19