Atmel AT89C5132 User manual

Features
•Programmable Audio Output for Interfacing with Common Audio DAC
– PCM Format Compatible
–I
2S Format Compatible
•8-bit MCU C51 Core-based (FMAX = 20 MHz)
•2304 Bytes of Internal RAM
•64K Bytes of Code Memory
– AT89C5132: Flash (100K Write/Erase Cycles)
•4K Bytes of Boot Flash Memory (AT89C5132)
– ISP: Download from USB (standard) or UART (option)
•USB Rev 1.1 Device Controller
– “Full Speed” Data Transmission
•Built-in PLL
•MultiMedia Card®Interface Compatibility
•Atmel DataFlash®SPI Interface Compatibility
•IDE/ATAPI Interface
•2 Channels 10-bit ADC, 8 kHz (8 True Bits)
– Battery Voltage Monitoring
– Voice Recording Controlled by Software
•Up to 44 Bits of General-purpose I/Os
– 4-bit Interrupt Keyboard Port for a 4 x n Matrix
–SmartMedia
®Software Interface
•Two Standard 16-bit Timers/Counters
•Hardware Watchdog Timer
•Standard Full Duplex UART with Baud Rate Generator
•Two Wire Master and Slave Modes Controller
•SPI Master and Slave Modes Controller
•Power Management
– Power-on Reset
– Software Programmable MCU Clock
– Idle Mode, Power-down Mode
•Operating Conditions
–3V,±10%, 25 mA Typical Operating at 25°C
– Temperature Range: -40°C to +85°C
•Packages
– TQFP80, PLCC84 (Development Board Only)
–Dice
1. Description
The AT89C5132 is a mass storage device controlling data exchange between various
Flash modules, HDD and CD-ROM.
The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program-
ming through an embedded 4K Bytes of Boot Flash Memory.
The AT89C5132 include 2304 Bytes of RAM memory.
The AT89C5132 provides all the necessary features for man-machine interface
including, timers, keyboard port, serial or parallel interface (USB, SPI, IDE), ADC
input, I2S output, and all external memory interface (NAND or NOR Flash, SmartMe-
dia, MultiMedia, DataFlash cards).
2. Typical Applications
• Flash Recorder/Writer
• PDA, Camera, Mobile Phone
• PC Add-on
USB
Microcontroller
with 64K Bytes
Flash Memory
AT89C5132
4173ES–USB–09/07

2 4173ES–USB–09/07
AT89C5132
3. Block Diagram
Figure 3-1. AT89C5132 Block Diagram
Notes: 1. Alternate function of Port 3
2. Alternate function of Port 4
3. Alternate function of Port 1
8-BIT INTERNAL BUS
Clock and PLL
Unit
C51 (X2 CORE)
RAM
2304 Bytes
Flash
Interrupt
Handler Unit
FILT X2X1
MMC
Interface
I/O
MDAT P0 - P5
10-bit A-to-D
Converter
VSS VDD
Keyboard
Interface
KIN3:0
I2S/PCM
Audio Interface
AVSSAVDD AIN1:0
Ports
INT0 INT1 MOSIMISO
Timers 0/1
T1T0
SPI/DataFlash
Controller
MCLK MCMD
SCK
RST
AREF
DSELDCLK SCLKDOUT
64K Bytes
USB
Controller
D+ D-
UART
RXDTXD
IDE
Interface
SS
Watchdog
Flash Boot
4K Bytes
UVSSUVDD
and
BRG
11 11 112222
3
TWI
Controller
SCL SDA
11

3
4173ES–USB–09/07
AT89C5132
4. Pin Description
Figure 4-1. AT89C5132 80-pin TQFP Package
P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.0/RXD
1
2
3
4
5
6
7
8
13
11
10
P2.2/A1
0
P2.3/A1
1
P2.4/A1
2
P2.6/A1
4
P2.5/A1
3
P2.7/A1
5
MCLK
MDAT
MCMD
P0.2/AD2 P0.1/AD1 P0.0/AD0
PVSS
VSS
X2
X1
TST
VSS
9
12
14
15
16
P4.3/SS P4.2/SCK P4.1/MOSI P4.0/MISO
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AIN1 AIN0
AREFN
AREFP
AVSS
AVDD
P3.7/RD
P3.6/WR
P3.5/T1
VDD
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PVDD
VDD
P1.6/SCL
17
18
19
20
21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40
41
42
43
44
45
46
47
48
53
51
50
49
52
54
55
56
57
58
59
60
61 62 63 64 65 66 67 68 73 71 70 69 72 74 75 76 77 78 79 80
ALE
ISP
UVDD
UVSS
P5.0 P5.1 P4.7 P4.6
D-
D+
P5.3 P5.2
VSS
VDD
P4.5
P4.4
TQFP80

4 4173ES–USB–09/07
AT89C5132
Figure 4-2. AT89C5132 84-pin PLCC (1)
Note: 1. For development board only.
4.1 Signals
All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description
PLCC84
P0.3/AD3 P0.4/AD4 P0.5/AD5 VSS VDD P0.6/AD6 P0.7/AD7 P2.0/A8 P2.1/A9
P3.3/INT1
P3.4/T0 P3.5/T1
P3.6/WR
P3.2/INT0
65
64
63
62
61
60
59
58
55
56
57
12
13
14
15
16
17
22
20
19
33 34 35 36 37
4 3 2 1
84 83 82 81 80 79 78
NC
P2.3/A11
P2.4/A12
P2.6/A14
P2.5/A13
P2.7/A15
MCLK
MDAT
MCMD
P0.2/AD2 P0.1/AD1 P5.0
PAVSS
VSS
X2
NC
X1
P3.1/TXD
18
21
23
24
25
38 39 40 41 42
69
68
67
66
70
5 6 7 8 9
P4.3/SS
P4.2/SCK P4.1/MOSI P4.0/MISO
VSS
VDD
RST
SCLK
DSEL
DCLK
DOUT
AIN1 AIN0
AREFN
AREFP
AVSS
AVDD
VSS
VDD
P3.7/RD
P3.0/RXD
P1.0/KIN0
P1.1/KIN1
P1.2/KIN2
P1.3/KIN3
P1.4
P1.5
P1.7/SDA
FILT
PAVDD
VDD
P1.6/SCL
26
43
TST
P5.2
P0.0/AD0
77
P2.2/A10
54
ALE
ISP
NC P5.1 P4.7 P4.6
76 75 10
11
28
27
29
30
31
32
UVDD
UVSS
44 45 46 47 48 49 50 51 52 53
74
73
72
71 P4.4
P4.5
VDD
VSS
D-
D+
NC
P5.3
Signal
Name Type Description Alternate Function
P0.7:0 I/O
Port 0
P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can beused as high impedance inputs. To avoid any parasitic
current consumption, floating P0 inputs must be polarized to VDD or VSS.
AD7:0
P1.7:0 I/O Port 1
P1 is an 8-bit bidirectional I/O port with internal pull-ups.
KIN3:0
SCL
SDA

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AT89C5132
Table 2. Clock Signal Description
Table 3. Timer 0 and Timer 1 Signal Description
P2.7:0 I/O Port 2
P2 is an 8-bit bidirectional I/O port with internal pull-ups. A15:8
P3.7:0 I/O Port 3
P3 is an 8-bit bidirectional I/O port with internal pull-ups.
RXD
TXD
INT0
INT1
T0
T1
WR
RD
P4.7:0 I/O Port 4
P4 is an 8-bit bidirectional I/O port with internal pull-ups.
MISO
MOSI
SCK
SS
P5.3:0 I/O Port 5
P5 is a 4-bit bidirectional I/O port with internal pull-ups. -
Signal
Name Type Description Alternate Function
X1 I
Input to the on-chip inverting oscillator amplifier
To use the internal oscillator, a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, its output is connected to this pin. X1 is the
clock source for internal timing.
-
X2 O Output of the on-chip inverting oscillator amplifier To use the internal oscillator, a crystal/resonator circuit is connected to this pin.
If an external oscillator is used, leave X2 unconnected. -
FILT I PLL Low Pass Filter input
FILT receives the RC network of the PLL low pass filter. -
Signal
Name Type Description Alternate Function
INT0 I
Timer 0 Gate Input
INT0 serves as external run control for timer 0, when selected by GATE0 bit in
TCON register.
External Interrupt 0
INT0 input sets IE0 in the TCON register. If bit IT0 in this register is set, bit IE0
is set by a falling edge on INT0. If bit IT0 is cleared, bit IE0 is set by a low level
on INT0.
P3.2
INT1 I
Timer 1 Gate Input
INT1 serves as external run control for timer 1, when selected by GATE1 bit in
TCON register.
External Interrupt 1
INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1
is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level
on INT1.
P3.3
Signal
Name Type Description Alternate Function

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AT89C5132
Table 4. Audio Interface Signal Description
Table 5. USB Controller Signal Description
Table 6. MutiMediaCard Interface Signal Description
T0 I Timer 0 External Clock Input When timer 0 operates as a counter, a falling edge on the T0 pin increments
the count. P3.4
T1 I Timer 1 External Clock Input When timer 1 operates as a counter, a falling edge on the T1 pin increments
the count. P3.5
Signal
Name Type Description Alternate Function
DCLK O DAC Data Bit Clock -
DOUT O DAC Audio Data -
DSEL O DAC Channel Select Signal
DSEL is the sample rate clock output. -
SCLK O DAC System Clock SCLK is the oversampling clock synchronized to the digital audio data (DOUT)
and the channel selection signal (DSEL). -
Signal
Name Type Description Alternate Function
D+ I/O USB Positive Data Upstream Port
This pin requires an external 1.5 KΩpull-up to VDD for full speed operation. -
D- I/O USB Negative Data Upstream Port -
Signal
Name Type Description Alternate Function
MCLK O MMC Clock output
Data or command clock transfer. -
MCMD I/O
MMC Command line
Bidirectional command channel used for card initialization and data transfer
commands. To avoid any parasitic current consumption, unused MCMD input
must be polarized to VDD or VSS.
-
MDAT I/O MMC Data line Bidirectional data channel. To avoid any parasitic current consumption, unused
MDAT input must be polarized to VDD or VSS.-
Signal
Name Type Description Alternate Function

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AT89C5132
Table 7. UART Signal Description
Table 8. SPI Controller Signal Description
Table 9. TWI Controller Signal Description
Table 10. A/D Converter Signal Description
Signal
Name Type Description Alternate Function
RXD I/O Receive Serial Data RXD sends and receives data in serial I/O mode 0 and receives data in serial
I/O modes 1, 2 and 3. P3.0
TXD O Transmit Serial Data TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O
modes 1, 2 and 3. P3.1
Signal
Name Type Description Alternate Function
MISO I/O SPI Master Input Slave Output Data Line When in master mode, MISO receives data from the slave peripheral. When in
slave mode, MISO outputs data to the master controller. P4.0
MOSI I/O SPI Master Output Slave Input Data Line When in master mode, MOSI outputs data to the slave peripheral. When in
slave mode, MOSI receives data from the master controller. P4.1
SCK I/O SPI Clock Line When in master mode, SCK outputs clock to the slave peripheral. When in
slave mode, SCK receives clock from the master controller. P4.2
SS ISPI Slave Select Line
When in controlled slave mode, SS enables the slave mode. P4.3
Signal
Name Type Description Alternate Function
SCL I/O
TWI Serial Clock
When TWI controller is in master mode, SCL outputs the serial clock to the
slave peripherals. When TWI controller is in slave mode, SCL receives clock
from the master controller.
P1.6
SDA I/O TWI Serial Data
SDA is the bidirectional Two Wire data line. P1.7
Signal
Name Type Description Alternate Function
AIN1:0 I A/D Converter Analog Inputs -
AREFP I Analog Positive Voltage Reference Input -
AREFN I Analog Negative Voltage Reference Input
This pin is internally connected to AVSS. -

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AT89C5132
Table 11. Keypad Interface Signal Description
Table 12. External Access Signal Description
Table 13. System Signal Description
Signal
Name Type Description Alternate Function
KIN3:0 I Keypad Input Lines Holding one of these pins high or low for 24 oscillator periods triggers a
keypad interrupt. P1.3:0
Signal
Name Type Description Alternate Function
A15:8 I/O Address Lines Upper address lines for the external bus.
Multiplexed higher address and data lines for the IDE interface. P2.7:0
AD7:0 I/O Address/Data Lines Multiplexed lower address and data lines for the external memory or the IDE
interface. P0.7:0
ALE O
Address Latch Enable Output
ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A7:0. An external latch is used to demultiplex
the address from address/data bus.
-
ISP I/O ISP Enable Input
This signal must be held to GND through a pull-down resistor at the falling
reset to force execution of the internal bootloader. -
RD ORead Signal
Read signal asserted during external data memory read operation. P3.7
WR OWrite Signal
Write signal asserted during external data memory write operation. P3.6
Signal
Name Type Description Alternate Function
RST I
Reset Input
Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The Port pins are driven to their reset conditions when a
voltage lower than VIL is applied, whether or not the oscillator is running.
This pin has an internal pull-down resistor which allows the device to be reset
by connecting a capacitor between this pin and VDD.
Asserting RST when the chip is in Idle mode or Power-Down mode returns the
chip to normal operation.
-
TST I Test Input
Test mode entry signal. This pin must be set to VDD.-

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AT89C5132
Table 14. Power Signal Description
Signal
Name Type Description Alternate Function
VDD PWR Digital Supply Voltage
Connect these pins to +3V supply voltage. -
VSS GND Circuit Ground
Connect these pins to ground. -
AVDD PWR Analog Supply Voltage
Connect this pin to +3V supply voltage. -
AVSS GND Analog Ground
Connect this pin to ground. -
PVDD PWR PLL Supply voltage
Connect this pin to +3V supply voltage. -
PVSS GND PLL Circuit Ground
Connect this pin to ground. -
UVDD PWR USB Supply Voltage
Connect this pin to +3V supply voltage. -
UVSS GND USB Ground
Connect this pin to ground. -

10 4173ES–USB–09/07
AT89C5132
4.2 Internal Pin Structure
Table 15. Detailed Internal Pin Structure
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the
Section “DC Characteristics”, page 183.
2. When the Two Wire controller is enabled, P1, P2, and P3transistors are disabled allowing
pseudo open-drain structure.
3. In Port 2, P1transistor is continuously driven when outputting a high level bit address (A15:8).
Circuit(1) Type Pins
Input TST
Input/Output RST
Input/Output
P1(2)
P2(3)
P3
P4
P53:0
Input/Output
P0
MCMD
MDAT
ISP
PSEN
Output
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
Input/Output D+
D-
R
TST
VDD
R
RST
VSS
P
VDD
Watchdog Output
P3
VSS
N
P1
VDD VDD
2 osc
Latch Output periods P2
VDD
VSS
N
P
VDD
VSS
N
P
VDD
D+
D-