BBK DV113S User manual

SERVICE MANUAL
DV113S

CONTENTS
1. SAFETY PRECAUTIONS 1
2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES 1
4. PREVERTION OF STATIC ELECTRICITY DISCHARGE 3
5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT 4
5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST 4
5.2 BRACKET EXPLOSED VIEW AND PART LIST
6
6. ELECTRICAL CONFIRMATION 8
6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION 8
6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION 9
7. MPEG BOARD CHECK WAVEFORM 10
8. IC BLOCK DIAGRAM & DESCRIPTION 11
9. SCHEMATIC & PCB WIRING DIAGRAM
19
10. SPARE PARTS LIST 32
8.2 MT1389 19
8.3 U214 HY29F800 14
8.4 U203 SDRAM-HY57V1610D
17
3. CONTROL BUTTON LOCATIONS AND EXPLANATIONS 2
5.3 MISCELLANEOUS 7

1.1 GENERAL GUIDELINES
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it.(Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)

3.Control Button Locations and Explanations
Front Panel Illustration
POWER switch
2Disc tray
3
4
5
6
PLAY/ buttonPAUSE
STOP button
MIC VOLUME button
MIC jack
3
2
567
7
8
8
4
IR SENSOR button
OPEN/CLOSE button

The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body.Use due caution to electrostatic breakdown when servicing and handling the laser diode.
4.1.Grounding for electrostatic breakdown prevention
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
grounding works is completed.
4.1.1. Worktable grounding
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
safety_3 (1577x409x2 tiff)
sheet.

5.1 Optical pickup Unit Explosed View and Part List
Pic (1)

Materials to Pic (1)
No. PARTS CODE PARTS NAME Q ty
14692200 SF-HD60 1
1 1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2 1EA0M10A15500 ASSY, MOTOR, SLED 1
Or 1EA0M10A15501 ASSY, MOTOR, SLED 1
3 1EA2451A24700 HOLDER, SHAFT 3
4 1EA2511A29100 GEAR, RACK 1
5 1EA2511A29200 GEAR, DRIVE 1
6 1EA2511A29300 GEAR, MIDDLE, A 1
7 1EA2511A29400 GEAR, MIDDLE, B 1
8 1EA2744A03000 SHAFT, SLIDE 1
9 1EA2744A03100 SHAFT, SLIDE, SUB 1
10 1EA2812A15300 SPRING, COMP, TYOUSEI 3
11 1EA2812A15400 SPRING, COMP, RACK 1
21 1EA0B10B20100 ASSY, PWB 1
Or 1EA0B10B20200 ASSY, PWB 1
31 SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
32 SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33 SFBPN204R0SE- SCR S-TPG PAN 2X4 2
34 SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
35 SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2

Note : This parts list is not for service parts supply.

5.2 Bracket Explosed View and Part List
Pic (2)
Materials to Pic(2)
1.bracket 14.frontsiliconrubber
2.belt15.Backsiliconrubber
3.screw 16.Pick-up
4.beltwheel 17.Pick-up
5.gearwheel 18.switch
6.ironchip 19.Five-pinflatplug
7. Immobility mechanism equipment 20. screw
8.Magnet 21.PCB
9.Platen 22.motor
10.Bridgebracket 23.Motorwheel
11.screw 24.screw
12.screw 25.tray
13. Big bracket
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.

5.3 MISCELLANEOUS
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.

6.1. Video Output (Luminance Signal) Confirmation
DO this confirmation after replacing a P.C.B.
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
Measurement point
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Mode Disc
Measuring equipment,tools
200mV/dir,10 sec/dir 1000mVp-p±30mV
Confirmation value

Do the confirmation after replacing P.C.B.
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
Measurement point
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Mode Disc
Measuring equipment,tools Confirmation value
Screwdriver,Oscilloscope
200mV/dir,10 sec/dir 621mVp-p±30mV

MT1389
Progressive-Scan DVD Player SOC
Specifications are subject to change without notice
MediaTek MT1389 is a DVD player system-on-chip (SOC) which incorporates advanced features like high
quality TV encoder and state-of-art de-interlace processing. The MT1389 enables consumer electronics
manufacturers to build high quality, cost-effective DVD players, portable DVD players or any other home
entertainment audio/video devices.
Based on MediaTek’s world-leading DVD player SOC architecture, the MT1389 is the 3rd generation of the DVD
player SOC. It integrates the MediaTek 2nd generation front-end analog RF amplifier and the Servo/MPEG AV
decoder.
The progressive scan of the MT1389 utilized a proprietary advanced motion-adaptive de-interlace algorithm to
achieve the best movie/video playback. It can easily detect 3:2/2:2 pull down source and restore the correct
original pictures. It also supports a patent-pending edge-preserving algorithm to remove the saw-tooth effect.
MT1389L
DVD
PUH
Module
FLASH
DRAM
CVBS, Y/C,
Component
SDPIF
Front-panel
Remote
Audio DAC
DVD Player System Diagram Using MT1389
Key Features
 RF/Servo/MPEG Integration
 High Performance Audio Processor
 Motion-Adaptive, Edge-Preserving De-interlace
 108MHz/12-bit, 6 CH TV Encoder
Applications
 Standard DVD Players
 Portable DVD Players

MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE
General Feature List

Super Integration DVD player single chip
 High performance analog RF amplifier
 Servo controller and data channel processing
 MPEG-1/MPEG-2/JPEG video
 Dolby AC-3/DTS/DVD-Audio
 Unified memory architecture
 Versatile video scaling & quality
enhancement
 OSD & Sub-picture
 2-D graphic engine
 Built-in clock generator
 Built-in high quality TV encoder
 Built-in progressive video processor
 Audio effect post-processor
 Audio input port

High Performance Analog RF Amplifier
 Programmable fc
 Dual automatic laser power control
 Defect and blank detection
 RF level signal generator

Speed Performance on Servo/Channel Decoding
 DVD-ROM up to 4XS
 CD-ROM up to 24XS

Channel Data Processor
 Digital data slicer for small jitter capability
 Built-in high performance data PLL for
channel data demodulation
 EFM/EFM+ data demodulation
 Enhanced channel data frame sync protection
& DVD-ROM sector sync protection

Servo Control and Spindle Motor Control
 Programmable frequency error gain and
phase error gain of spindle PLL to control
spindle motor on CLV and CAV mode
 Built-in ADCs and DACs for digital servo
control
 Provide 2 general PWM
 Tray control can be PWM output or digital
output

Embedded Micro controller
 Built-in 8032 micro controller
 Built-in internal 373 and 8-bit programmable
lower address port
 1024-bytes on-chip RAM
 Up to 4M bytes FLASH-programming
interface
 Supports 5/3.3-Volt. FLASH interface
 Supports power-down mode
 Supports additional serial port

DVD-ROM/CD-ROM Decoding Logic
 High-speed ECC logic capable of correcting
one error per each P-codeword or
Q-codeword
 Automatic sector Mode and Form detection
 Automatic sector Header verification
 Decoder Error Notification Interrupt that
signals various decoder errors
 Provide error correction acceleration

Buffer Memory Controller
 Supports 16Mb/32Mb/64Mb/128Mb SDRAM
 Supports 16-bit SDRAM data bus
 Provide the self-refresh mode SDRAM
 Block-based sector addressing
 Support 3.3 Volt. DRAM Interface

Video Decode
 Decodes MPEG1 video and MPEG2 main level,
main profile video (720/480 and 720x576)
 Smooth digest view function with I, P and B
picture decoding
 Baseline, extended-sequential and
progressive JPEG image decoding
 Support CD-G titles

Video/OSD/SPU/HLI Processor
 Arbitrary ratio vertical/horizontal scaling of
video, from 0.25X to 256X
 65535/256/16/4/2-color bitmap format OSD,
 256/16 color RLC format OSD
 Automatic scrolling of OSD image
 Slide show transition as DVD-Audio
Specification

2-D Graphic Engine
 Support decode Text and Bitmap
 Support line, rectangle and gradient fill
 Support bitblt
 Chroma key copy operation
 Clip mask

MT1389
PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Audio Effect Processing
 Dolby Digital (AC-3)/EX decoding
 DTS/DTS-ES decoding
 MLP decoding for DVD-Audio
 MPEG-1 layer 1/layer 2 audio decoding
 MPEG-2 layer1/layer2 2-channel audio
 High Definition Compatible Digital (HDCD)
 Windows Media Audio (WMA)
 Advanced Audio Coding (AAC)
 Dolby ProLogic II
 Concurrent multi-channel and downmix out
 IEC 60958/61937 output
- PCM / bit stream / mute mode
- Custom IEC latency up to 2 frames
 Pink noise and white noise generator
 Karaoke functions
- Microphone echo
- Microphone tone control
- Vocal mute/vocal assistant
- Key shift up to +/- 8 keys
- Chorus/Flanger/Harmony/Reverb
 Channel equalizer
 3D surround processing include virtual
surround and speaker separation

TV Encoder
 Six 108MHz/12bit DACs
 Support NTSC, PAL-BDGHINM, PAL-60
 Support 525p, 625p progressive TV format
 Automatically turn off unconnected channels
 Support PC monitor (VGA)
 Support Macrovision 7.1 L1, Macrovision
525P and 625P
 CGMS-A/WSS
 Closed Caption

Progressive Output
 Automatic detect film or video source
 3:2 pull down source detection
 Advanced Motion adaptive de-interlace
 Edge Preserving
 Minimum external memory requirement

Audio Input
 Line-in/SPDIF-in for versatile audio
processing

Outline
 256-pin LQFP package
 3.3/1.8-Volt. Dual operating voltages

KEY FEATURES
n5 Volt Read, Program, and Erase
– Minimizes system-level power requirements
nHigh Performance
– Access times as fast as 55 ns
nLow Power Consumption
– 20 mA typical active read current in byte
mode, 28 mA typical in word mode
– 35 mA typical program/erase current
– 5 µA maximum CMOS standby current
nCompatible with JEDEC Standards
– Package, pinout and command-set
compatible with the single-supply Flash
device standard
– Provides superior inadvertent write
protection
nSector Erase Architecture
– Boot sector architecture with top and
bottom boot block options available
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte
and fifteen 64 Kbyte sectors in byte mode
– One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors in word mode
– A command can erase any combination of
sectors
– Supports full chip erase
nErase Suspend/Resume
– Temporarily suspends a sector erase
operation to allow data to be read from, or
programmed into, any sector not being
erased
nSector Protection
– Any combination of sectors may be
locked to prevent program or erase
operations within those sectors
nTemporary Sector Unprotect
– Allows changes in locked sectors
(requires high voltage on RESET# pin)
nInternal Erase Algorithm
– Automatically erases a sector, any
combination of sectors, or the entire chip
nInternal Programming Algorithm
– Automatically programs and verifies data
at a specified address
nFast Program and Erase Times
– Byte programming time: 7 µs typical
– Sector erase time: 1.0 sec typical
– Chip erase time: 19 sec typical
nData# Polling and Toggle Status Bits
– Provide software confirmation of
completion of program or erase
operations
nReady/Busy# Output (RY/BY#)
– Provides hardware confirmation of
completion of program and erase
operations
nMinimum 100,000 Program/Erase Cycles
nSpace Efficient Packaging
– Available in industry-standard 44-pin
PSOP and 48-pin TSOP and reverse
TSOP packages
A[18:0]
19
CE#
OE#
RESET#
BYTE#
WE#
8
7
DQ[7:0]
DQ[14:8]
DQ[15]/A-1
RY/BY#

BLOCK DIAGRAM
STATE
CONTROL
WE#
CE#
OE#
BYTE#
COMMAND
REGISTER
DQ[15:0]
A[18:0], A-1
V
CC
DETECTOR TIMER
ERASE VOLTAGE
GENERATOR AND
SECTOR SWITCHES
PROGRAM
VOLTAGE
GENERATOR
ADDRESS LATCH
X-DECODER
Y-DECODER
8 Mb FLASH
MEMORY
ARRAY
Y-GATING
DATA LATCH
I/O BUFFERS
I/O CONTROL
RESET#
DQ[15:0]
A[18:0], A-1
RY/BY#

PIN CONFIGURATIONS
Standard
TSOP48
DQ7
DQ14
44
43 DQ6
DQ13
42
41 DQ5
DQ12
40
39 DQ4
V
CC
38
37 DQ11
DQ3
36
35 DQ10
DQ2
34
33 DQ9
DQ1
32
31 DQ8
DQ0
30
29
A16
BYTE#
48
47 V
SS
DQ15/A-1
46
45
OE#
V
SS
28
27 CE#
A0
26
25
A11
A10 5 6
A9
A8 7 8
NC
NC 9 10
WE#
RESET# 11 12
NC
NC 13 14
RY/BY#
A18 15 16
A17
A7 17 18
A6
A5 19 20
A15
A14 1 2
A13
A12 3 4
A4
A3 21 22
A2
A1 23 24
Reverse
TSOP48
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
48
47
46
45
28
27
26
25
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
21
22
23
24
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A15
A14
A13
A12
A4
A3
A2
A1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
A16
BYTE#
V
SS
DQ15/A-1
OE#
V
SS
CE#
A0
A6
A5 5 6
A4
A3 7 8
A2
A1 9 10
A0
CE# 11 12
V
SS
OE# 13 14
DQ0
DQ8 15 16
DQ1
DQ9 17 18
DQ2
DQ10 19 20
DQ3
DQ11 21 22
RY/BY#
A18 1 2
A17
A7 3 4A10
A11
40
39 A12
A13
38
37 A14
A15
36
35 A16
BYTE#
34
33 V
SS
DQ15/A-1
32
31 DQ7
DQ14
30
29 DQ6
DQ13
28
27 DQ5
DQ12
26
25 DQ4
V
CC
24
23
RESET#
WE#
44
43 A8
A9
42
41
PSOP44

This document is a general product description and is subject to chage without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied
Rev. 0.2/Aug.01
DESCRIPTION
THE Hynix HY57V161610D is a 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and industrial temperature range. HY57V161610D is organized as 2banks of
524,288x16.
HY57V161610D is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are
synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high band-
width. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 1,2 or 3), the number of consecutive read or
write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipeline
design is not restricted by a `2N` rule.)
FEATURES
•Single 3.0V to 3.6V power supply Note1)
•All device pins are compatible with LVTTL interface
•JEDEC standard 400mil 50pin TSOP-II with 0.8mm
of pin pitch
•All inputs and outputs referenced to positive edge of
system clock
•Data mask function by UDQM/LDQM
•Internal two banks operation
•Auto refresh and self refresh
•4096 refresh cycles / 64ms
•Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequence Burst
- 1, 2, 4 and 8 for Interleave Burst
•Programmable CAS Latency ; 1, 2, 3 Clocks
ORDERING INFORMATION
Part No. Clock Frequency Organization Interface Package
HY57V161610DTC-55I 183MHz
2Banks x 512Kbits x 16 LVTTL 400mil
50pin TSOP II
HY57V161610DTC-6I 166MHz
HY57V161610DTC-7I 143MHz
HY57V161610DTC-10I 100MHz

PIN CONFIGURATION
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are referenced to the SDRAM on the
rising edge of CLK.
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh.
CS Chip Select Command input enable or mask except CLK, CKE and DQM
BA Bank Address Select either one of banks during both RAS andCAS activity.
A0 ~ A10 Address Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE Row Address Strobe, Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation.
Refer function truth table for details
LDQM, UDQM Data Input/Output Mask DQM control output buffer in read mode and mask input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuit and input buffer
VDDQ/VSSQ Data Output Power/Ground Power supply for DQ
NC No Connection No connection
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
A11
A10
A0
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
50pin TSOP-II
400mil x 825mil
0.8mm pin pitch
A2
A3
VDD
A5
A4
VSS
23
24
25
28
27
26