BBK DV966S User manual

SERVICE MANUAL
DV966S

CONTENTS
1. SAFETY PRECAUTIONS 1
2. PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO ELECTROSTATICALLY
SENSITIVE(ES)DEVICES 1
4. PREVERTION OF STATIC ELECTRICITY DISCHARGE 3
5. ASSEMBLING AND DISASSEMBLING THE MECHANISM UNIT 4
5.1 OPTICAL PICKUP UNIT EXPLOSED VIEW AND PART LIST 4
5.2 BRACKET EXPLOSED VIEW AND PART LIST
6
6. ELECTRICAL CONFIRMATION 8
6.1 VIDEO OUTPUT (LUMINANCE SIGNAL) CONFIRMATION 8
6.2 VIDEO OUTPUT(CHROMINANCE SIGNAL) CONFIRMATION 9
7. MPEG BOARD CHECK WAVEFORM 10
8. AM29LV160D 11
9. SCHEMATIC & PCB WIRING DIAGRAM
22
10. SPARE PARTS LIST
8.1 HY57V641620HG 16
3. CONTROL BUTTON LOCATIONS AND EXPLANATIONS 2
5.3 MISCELLANEOUS 7
8.2 MT1389
36
19

1.1 GENERAL GUIDELINES
1. When servicing, observe the original lead dress. if a short circuit is found, replace all parts which have
been overheated or damaged by the short circuit.
2. After servicing, see to it that all the protective devices such as insulation barrier, insulation papers
shields are properly installed.
3. After servicing, make the following leakage current checks to prevent the customer from being exposed
to shock hazards.
Some semiconductor(solid state)devices can be damaged easily by static electricity. Such components
commonly are called Electrostatically Sensitive(ES)Devices. Examples of typical ES devices are integrated
circuits and some field-effect transistors and semiconductor chip components. The following techniques
should be used to help reduce the incidence of component damage caused by electro static discharge(ESD).
1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain
off any ESD on your body by touching a known earth ground. Alternatively, obtain and wear a commercially
availabel discharging ESD wrist strap, which should be removed for potential shock reasons prior to
applying power to the unit under test.
2. After removing an electrical assembly equipped with ES devices,place the assembly on a conductive
surface such as alminum foil, to prevent electrostatic charge buildup or exposure of the assembly.
3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.
4. Use only an anti-static solder removal device. Some solder removal devices not classified as anti-static
(ESD protected)can generate electrical charge sufficient to damage ES devices.
5. Do not use freon-propelled chemicals. These can generate electrical charges sufficient to damage ES
devices.
6. Do not remove a replacement ES device from its protective package until immediately before you are
ready to install it.(Most replacement ES devices are packaged with leads electrically shorted together by
conductive foam, alminum foil or comparable conductive material).
7. Immediately before removing the protective material from the leads of a replacement ES device, touch
the protective material to the chassis or circuit assembly into which the device will be installed.
Caution
Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.
8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion
such as the brushing together of your clothes fabric or the lifting of your foot from a carpeted floor can
generate static electricity(ESD).
notice (1885x323x2 tiff)
1. SAFETY PREAUTIONS
2.PREVENTION OF ELECTRO STATIC DISCHARGE(ESD)TO 
ELECTROSTATICALLY SENSITIVE(ES)DEVICES
1

Front Panel Illustration
POWER switch
2
Disc tray
4
PLAY/PAUSE button
5
6STOP button
7IR SENSOR
Display window
3
OPEN/CLOSE button
3
2
4
7
6
5
2

The laser diode in the traverse unit (optical pickup)may brake down due to static electricity of clothes or human
body.Use due caution to electrostatic breakdown when servicing and handling the laser diode.
4.1.Grounding for electrostatic breakdown prevention
Some devices such as the DVD player use the optical pickup(laser diode)and the optical pickup will be damaged
by static electricity in the working environment.Proceed servicing works under the working environment where
grounding works is completed.
4.1.1. Worktable grounding
1. Put a conductive material(sheet)or iron sheet on the area where the optical pickup is placed,and ground the
4.1.2.Human body grounding
1 Use the anti-static wrist strap to discharge the static electricity from your body.
4.1.3.Handling of optical pickup
1. To keep the good quality of the optical pickup maintenance parts during transportation and before
installation, the both ends of the laser diode are short-circuited.After replacing the parts with new ones,
remove the short circuit according to the correct procedure. (See this Technical Guide).
2. Do not use a tester to check the laser diode for the optical pickup .Failure to do so willdamage the laser
diode due to the power supply in the tester.
4.2. Handling precautions for Traverse Unit (Optical Pickup)
1. Do not give a considerable shock to the traverse unit(optical pickup)as it has an extremely high-precise
structure.
2. When replacing the optical pickup, install the flexible cable and cut is short land with a nipper. See the
optical pickup replacement procedure in this Technical Guide. Before replacing the traverse unit, remove
the short pin for preventingstatic electricity and install a new unit.Connect the connector as short times as
possible.
3. The flexible cable may be cut off if an excessive force is applied to it.Use caution when handling the cable.
4. The half-fixed resistor for laser power adjustment cannot be adjusted. Do not turn the resistor.
safety_3 (1577x409x2 tiff)
sheet.
3
4.PREVENTION OF STATIC ELECTRICITY DISCHARGE

5.1 Optical pickup Unit Explosed View and Part List
Pic (1)
5. Assembling and disassembling the mechanism unit
4

Materials to Pic (1)
No. PARTS CODE PARTS NAME Q ty
14692200 SF-HD60 1
1 1EA0311A06300 ASSY, CHASSIS, COMPLETE 1
2 1EA0M10A15500 ASSY, MOTOR, SLED 1
Or 1EA0M10A15501 ASSY, MOTOR, SLED 1
3 1EA2451A24700 HOLDER, SHAFT 3
4 1EA2511A29100 GEAR, RACK 1
5 1EA2511A29200 GEAR, DRIVE 1
6 1EA2511A29300 GEAR, MIDDLE, A 1
7 1EA2511A29400 GEAR, MIDDLE, B 1
8 1EA2744A03000 SHAFT, SLIDE 1
9 1EA2744A03100 SHAFT, SLIDE, SUB 1
10 1EA2812A15300 SPRING, COMP, TYOUSEI 3
11 1EA2812A15400 SPRING, COMP, RACK 1
21 1EA0B10B20100 ASSY, PWB 1
Or 1EA0B10B20200 ASSY, PWB 1
31 SEXEA25700--- SPECIAL SCREW BIN+-M2X11 3
32 SEXEA25900--- SPECIAL SCREW M1.7X2.2 2
33 SFBPN204R0SE- SCR S-TPG PAN 2X4 2
34 SFSFN266R0SE- SCR S-TPG FLT 2.6X6 1
35 SWXEA15400--- SPECIAL WASHER 1.8X4 X0.25 2

Note : This parts list is not for service parts supply.
5

5.2 Bracket Explosed View and Part List
Pic (2)
Materials to Pic(2)
1.bracket 14.frontsiliconrubber
2.belt15.Backsiliconrubber
3.screw 16.Pick-up
4.beltwheel 17.Pick-up
5.gearwheel 18.switch
6.ironchip 19.Five-pinflatplug
7. Immobility mechanism equipment 20. screw
8.Magnet 21.PCB
9.Platen 22.motor
10.Bridgebracket 23.Motorwheel
11.screw 24.screw
12.screw 25.tray
13. Big bracket
Before going process with disassembly and installation, please carefully both
peruse the chart and confirm the materials.
6

5.3 MISCELLANEOUS
5.3.1 Protection of the LD(Laser diode)
Short the parts of LD circuit pattern by soldering.
5.3.2 Cautions on assembly and adjustment
Make sure that the workbenches,jigs,tips,tips of soldering irons and measuring instruments are
grounded,and that personnel wear wrist straps for ground.
Open the LD short lands quickly with a soldering iron after a circuit is connected.
Keep the power source of the pick-up protected from internal and external sources of electrical
noise.
Refrain from operation and storage in atmospheres containing corrosive gases (such as H2S,SO2,
NO2 and Cl2)or toxic gases or in locations containing substances(especially from the organic silicon,cyan,
formalin and phenol groups)which emit toxic gases.It is particularly important to ensure that none of the
above substances are present inside the unit.Otherwise,the motor may no longer run.
7

6.1. Video Output (Luminance Signal) Confirmation
DO this confirmation after replacing a P.C.B.
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohms.
2.Confirm that luminance signal(Y+S)level is 1000mVp-p±30mV
Measurement point
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Mode Disc
Measuring equipment,tools
200mV/dir,10 sec/dir 1000mVp-p±30mV
Confirmation value
6.Electrical Confirmation
8

Do the confirmation after replacing P.C.B.
Purpose:To maintain video signal output compatibility.
1.Connect the oscilloscope to the video output terminal and terminate at 75 ohme.
2.Confirm that the chrominance signal(C)level is 621 mVp-p±30mV
Measurement point
Video output terminal
Color bar 75%
PLAY(Title 46):DVDT-S15
PLAY(Title 12):DVDT-S01
DVDT-S15
or
DVDT-S01
Mode Disc
Measuring equipment,tools Confirmation value
Screwdriver,Oscilloscope
200mV/dir,10 sec/dir 621mVp-p±30mV
6.2 Video Output(Chrominance Signal) Confirmation

9

7.MPEG BOARD CHECK WAVEFORM
7.1 27MHz WAVEFORM 
DIAGRAM
7.2 IC VIPER22 PIN.5 WAVEFORM DIAGRAM
10

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22358 Rev: BAmendment/+3
Issue Date: November 10, 2000
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
■Manufactured on 0.23 µm process technology
— Fully compatible with 0.32 µm Am29LV160B device
■High performance
— Access times as fast as 70 ns
■Ultra low power consumption (typical values at
5MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 9 mA read current
— 20 mA program/erase current
■Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
thirty-one 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent
any program or erase operations within that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
■Top or bottom boot block configurations
available
■Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■Minimum 1,000,000 write cycle guarantee
per sector
■20-year data retention at 125°C
— Reliable operation for the life of the system
■Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
■CFI (Common Flash Interface) compliant
— Provides device-specific information to the
system, allowing host software to easily
reconfigure for different Flash devices
■Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■Data# Polling and toggle bits
— Providesasoftwaremethodofdetectingprogram
or erase operation completion
■Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion (notavailable
on 44-pin SO)
■Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
11
8. Am29LV160D

Am29LV160D
PRODUCT SELECTOR GUIDE
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
Family Part Number Am29LV160D
Speed Option Voltage Range: VCC = 2.7–3.6 V -70 -90 -120
Max access time, ns (tACC)7090120
Max CE# access time, ns (tCE)7090120
Max OE# access time, ns (tOE) 303550
Input/Output
Buffers
X-Decoder
Y-Decoder
Chip Enable
Output Enable
Logic
Erase Voltage
Generator
PGM Voltage
Generator
Timer
VCC Detector
State
Control
Command
Register
VCC
VSS
WE#
BYTE#
CE#
OE#
STB
STB
DQ0
– DQ15 (A-1)
Sector Switches
RY/BY#
RESET#
Data
Latch
Y-Gating
Cell Matrix
Address Latch
A0–A19
12

CONNECTION DIAGRAMS
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
A1
A15
A18
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
NC
RY/BY#
A17
A7
A6
A5
A4
A3
A2
1
16
2
3
4
5
6
7
8
17
18
19
20
21
22
23
24
9
10
11
12
13
14
15
A16
DQ2
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
48
33
47
46
45
44
43
42
41
40
39
38
37
36
35
34
25
32
31
30
29
28
27
26
Reverse TSOP
Standard TSOP
13

A
CONNECTION DIAGRAMS
Special Handling Instructions
Special handling is required for Flash Memory products
in FBGA packages.
Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
RESET#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
WE#
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
SO
A1 B1 C1 D1 E1 F1 G1 H1
A2 B2 C2 D2 E2 F2 G2 H2
A3 B3 C3 D3 E3 F3 G3 H3
A4 B4 C4 D4 E4 F4 G4 H4
A5 B5 C5 D5 E5 F5 G5 H5
A6 B6 C6 D6 E6 F6 G6 H6
DQ15/A-1 VSS
BYTE#A16A15A14A12A13
DQ13 DQ6DQ14DQ7A11A10A8A9
VCC DQ4DQ12DQ5A19NCRESET#WE#
DQ11 DQ3DQ10DQ2NCA18NCRY/BY#
DQ9 DQ1DQ8DQ0A5A6A17A7
OE# VSS
CE#A0A1A2A4A3
FBGA
Top View, Balls Facing Down
14

PIN CONFIGURATION
A0–A19 = 20 addresses
DQ0–DQ14 = 15 data inputs/outputs
DQ15/A-1 = DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE# = Selects 8-bit or 16-bit mode
CE# = Chip enable
OE# = Output enable
WE# = Write enable
RESET# = Hardware reset pin
RY/BY# = Ready/Busy output
(N/A SO 044)
VCC = 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS = Device ground
NC = Pin not connected internally
LOGIC SYMBOL
20 16 or 8
DQ0–DQ15
(A-1)
A0–A19
CE#
OE#
WE#
RESET#
BYTE# RY/BY#
(N/A SO 044)
15

HY57V641620HG
4 Banks x 1M x 16Bit Synchronous DRAM
.
DESCRIPTION
The Hyundai HY57V641620HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V641620HG is organized as 4banks of 1,048,576x16.
HY57V641620HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated
by a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of
read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst
read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
•Single 3.3±0.3V power supply Note)
•All device pins are compatible with LVTTL interface
•JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
•All inputs and outputs referenced to positive edge of
system clock
•Data mask function by UDQM or LDQM
•Internal four banks operation
•Auto refresh and self refresh
•4096 refresh cycles / 64ms
•Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
•Programmable CAS Latency ; 2, 3 Clocks
8.1 HY57V641620HG
16

HY57V641620HG
PIN CONFIGURATION
PIN DESCRIPTION
PIN PIN NAME DESCRIPTION
CLK Clock The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE Clock Enable Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS Chip Select Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1 Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11 Address Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE Row Address Strobe, Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
LDQM, UDQM Data Input/Output Mask Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ15 Data Input/Output Multiplexed data input / output pin
VDD/VSS Power Supply/Ground Power supply for internal circuits and input buffers
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers
NC No Connection No connection
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
17

HY57V641620HG
FUNCTIONAL BLOCK DIAGRAM
1Mbit x 4banks x 16 I/O Synchronous DRAM
X decoders
State Machine
A0
A1
A11
BA0
BA1
Address buffers
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
Internal Row
counter
DQ0
DQ1
DQ14
DQ15
refresh
Self refresh logic
& timer
Pipe Line Control
I/O Buffer & Logic
Bank Select
Sense AMP & I/O Gate
CLK
CKE
CS
RAS
CAS
WE
UDQM
LDQM
1Mx16 Bank 3
X decoders
X decoders
Memory
Cell
Array
Y decoders
X decoders
1Mx16 Bank 0
1Mx16 Bank 1
1Mx16 Bank 2
18