Broadcom PLX PCI 9052RDK-LITE Quick user guide

PCI 9052RDK-LITE
Hardware Reference Manual

PCI 9052RDK-LITE
Hardware Reference Manual
Version 1.3
October 2004
Website: http://www.plxtech.com
Technical Support: http://www.plxtech.com/support/
Phone: [phone]
800 759-3735
Fax: [phone]

© 2004 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PCI 9052/LITE-RDK-HRM-P1-1.3
Printed in the USA, October 2004

PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PCI 9052RDK-LITE, a Rapid Development Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a
reference for the creation of software for this product. This manual also includes complete schematics
and bill of materials.
REVISION HISTORY
Date Version Comments
June 2001 0.50 Yellow Book initial release.
November 2001 1.0 Hardware Reference Manual release
June 2002 1.1
Section 2.2: Clarified PCI 9052 feature set. Table 3-2: Changed offset
28h register value description and clarified offset 5Ch register value
description. Section 3.4.1: Added exceptions to ISA compatibility.
Section 4.1.2: Clarified how to enable a local address space. Section
4.2.4.1: Changed LASxBRD register settings for 8-bit and 16-bit ISA
operation. Section 4.2.4.2: Added CNTRL[18] value for PCI v2.1
compatible systems. Section 4.2.5: Added recommendation that
disabled LINTix pins should not be left floating. Section 6: Updated BOM
and changed schematic to reflect BOM update.
March 2003 1.2 Updated Schematic and Bill of Materials.
October 2004 1.3 Add Notes 2 and 3 at Table 3-4 Configuration Jumper Settings.
Add Note to Section 1.2 RDK Installation. Update Bill of Materials.
Add Section 4.4, ISA Interface AEN Signal
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved. iii

TABLE OF CONTENTS
1. GENERAL INFORMATION...................................................................................................1
1.1 FEATURES ....................................................................................................................................... 2
1.2 RDK INSTALLATION.......................................................................................................................... 2
2. PCI 9052 OVERVIEW ...........................................................................................................3
2.1 PCI 9052 INTRODUCTION ................................................................................................................. 3
2.2 PCI 9052 FEATURE SET................................................................................................................... 3
3. RDK HARDWARE ARCHITECTURE ...................................................................................5
3.1 ARCHITECTURE OVERVIEW............................................................................................................... 5
3.2 HARDWARE MEMORY MAP................................................................................................................ 6
3.3 SERIAL EEPROM............................................................................................................................ 6
3.4 LOCAL BUS OPERATING MODES........................................................................................................ 9
3.4.1 ISA Interface............................................................................................................................ 9
3.5 STATIC RAM (SRAM)...................................................................................................................... 9
3.6 ROM SOCKET.................................................................................................................................. 9
3.7 TEST HEADERS.............................................................................................................................. 10
3.8 CPLD FUNCTIONALITY ................................................................................................................... 10
3.9 PROTOTYPING AREA ...................................................................................................................... 11
3.9.1 BGA Prototyping.................................................................................................................... 12
3.10 RDK BOARD CONFIGURATION ........................................................................................................ 12
4. ISA TO PCI MIGRATION ....................................................................................................15
4.1 ISA REGISTER CONFIGURATION...................................................................................................... 15
4.1.1 Range Register...................................................................................................................... 15
4.1.2 Base Address Re-map Register............................................................................................ 15
4.1.3 Chip Select Register.............................................................................................................. 15
4.2 ISA REGISTER CONFIGURATION EXAMPLE....................................................................................... 16
4.2.1 ISA Memory Mapping............................................................................................................ 16
4.2.2 ISA I/O Mapping.................................................................................................................... 16
4.2.3 Chip Select Configuration...................................................................................................... 16
4.2.4 Other Local Settings.............................................................................................................. 16
4.2.4.1 Bus Region Descriptor .................................................................................................................16
4.2.4.2 Initialization Control Register........................................................................................................17
4.2.4.3 Interrupt Control/Status Register..................................................................................................17
4.2.5 Interrupts ............................................................................................................................... 17
4.2.6 Serial EEPROM..................................................................................................................... 17
4.2.7 PCI Access to Local ISA Bus................................................................................................ 17
4.3 ISA NOWS# DELAY OPTION.......................................................................................................... 18
4.4 ISA INTERFACE AEN SIGNAL.......................................................................................................... 18
5. CUSTOMER SUPPORT & REFERENCES.........................................................................20
5.1 CUSTOMER SUPPORT..................................................................................................................... 20
5.2 REFERENCES................................................................................................................................. 20
6. BILL OF MATERIALS / PLD & CIRCUIT SCHEMATICS...................................................21
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved. v

LIST OF FIGURES
Figure 1-1. PCI 9052RDK-LITE Layout Diagram.................................................................................. 1
Figure 3-1. PCI 9052RDK-LITE Hardware Block Diagram................................................................... 5
Figure 3-2. BGA to PGA Conversion .................................................................................................. 12
LIST OF TABLES
Table 3-1. PCI 9052RDK-LITE Default Memory Map........................................................................... 6
Table 3-2. Serial EEPROM Contents.................................................................................................... 7
Table 3-3. PCI 9052RDK-LITE Board Prototyping Area Footprints.................................................... 11
Table 3-4. Configuration Jumper Settings........................................................................................... 13
Table 6-1. Bill of Materials................................................................................................................... 21
PCI 9052RDK-LITE Hardware Reference Manual v1.3
vi © 2004 PLX Technology, Inc. All rights reserved.

1. General Information
5VCC
3.3V
GND 3.3V
GND
Serial
EEPROM
PCI 9052
ISA Connector
16 pin
SOIC 16 pin SOIC
16 pin
SOIC
16 pin
SOIC
20 pin
SSOIC
20 pin
SOIC
20 pin
SOIC
20 pin
SOIC
208/144/80
PQFP
footprints 44 pin
TQFP
20 pin
PLCC
54 pin TSOP
54 pin TSOP
84/68/44/28
PLCC
footprints
25x25 0.1" through hole
prototyping area
176/100/48
PQFP
footprints
48 pi
OS C
U17
Figure 1-1. PCI 9052RDK-LITE Layout Diagram
The PCI 9052RDK-LITE (RDK-LITE) is a flexible Rapid Development Kit for designs using the PLX PCI
9052 bus target device. It features 1 BGA and 28 surface-mount QFP/PLCC/SSOP/SOIC prototyping
footprints for hardware designers to easily add memory, FIFO, I/O devices etc. These allow designers to
test, simulate, and debug their designs without fabricating their own boards, saving considerable time and
money in the development process and shortening time to market. The RDK-LITE also contains an ISA
connector that connects directly to the PCI 9052 ISA bus interface, allowing designers to plug an ISA
board onto the RDK board to immediately test the data transfer between ISA and PCI buses. The RDK-
LITE kit comes with the PLX Software Development Kit CD-ROM that provides a complete Windows host
side software development environment.
n
P
SSO 48 pin SSOP
24 pin
SSOP
24 pin
SSOP
U5 FP1 for flash
memory
SRAM
U7
SRAM
U16
SRAM
U15
LA
H3
U1
DC/DC
Converter
16 pin
SSOP
16 pin
SSOP
OSC
U3
26x26 0.05"
pitch BGA
landscape
SRAM
U10 LA
H4
LA
H1 LA H2
LA
H5 LA H6
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.1

1.1 Features
The PCI 9052RDK-LITE Rapid Development Kit (RDK-LITE) board is a versatile PCI bus target
development platform. It contains a 12.28” L x 5.20” W, four-layer, assembled PC board with the
following features:
•PLX PCI 9052 PCI Target interface chip with direct ISA interface
•ISA bus interface connector
•Socketed serial EEPROM for PCI 9052 configuration
•Support for 16-bit ISA and 32-bit multiplexed and non-multiplexed local bus modes
•CPLD with spare capacity for additional prototyping logic
•Twenty-eight surface-mount QFP/PLCC footprints and one 0.05” pitch BGA landscape for
memory, FIFO, I/O devices, logic devices, etc.
•32-pin PLCC socket for expansion ROM
•On-board 128KB of SRAM and associated logic for PCI 9052 continuous burst read/write
accesses
•Socketed 32 MHz oscillator for local bus clock
•5V to 3.3V voltage regulator
•Six logic analyzer headers with standard HP footprint to allow easy probing of local bus signals
•25x25, 0.1” through-hole prototyping grid
1.2 RDK Installation
To install the RDK into your computer, please refer to your computer’s instruction manual for the
correct preparation and installation of add-in cards.
Note: The 9052RDK-Lite card edge connector is constructed using Universal keying (as shown in
PCI Specification r2.1, Figure 5-28) which allows insertion into either a 3.3V or 5V PCI slot, rather
than being keyed for use only in a 5V slot. Because the PCI 9052 generates 5V signaling,
operation in a 3.3V system could damage devices on the bus that are not 5V-tolerant. The RDK
will not damage systems that use 5V keyed or universal keyed slots but extreme care should be
taken if the RDK is plugged into a system that is only keyed for 3.3V operation.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
2© 2004 PLX Technology, Inc. All rights reserved.

2. PCI 9052 Overview
2.1 PCI 9052 Introduction
The PLX PCI 9052 provides a compact, high-performance PCI bus target (slave) interface for adapter
boards. It is designed to connect a wide variety of local bus designs to the PCI bus and allow them to
achieve high data rate burst transfers on the PCI bus.
The PCI 9052 can be programmed to connect directly to an 8- or 16-bit local ISA bus as well as to 8-, 16-,
or 32-bit multiplexed or non-multiplexed local busses.
The PCI 9052 contains read and write FIFOs to speed-match a 32-bit wide, 33 MHz PCI bus to a local
bus, which may be a different width and/or speed. Up to five local address spaces and up to four local
chip selects are supported.
2.2 PCI 9052 Feature Set
•PCI v2.1 compliance: The PCI 9052 is compliant with PCI Specification v2.1, supporting low
cost slave adapters. It facilitates the simple conversion of ISA adapters to PCI target adapters.
•Direct slave (Target) data transfer mode. The PCI 9052 supports burst memory-mapped and
single-cycle I/O mapped accesses from the PCI bus to the local bus. The read and write FIFOs
enable high performance bursting on the local and PCI bus. When the PCI bus is bursting, the
local bus can either perform burst accesses or multiple single-cycle accesses.
•Interrupt generator. The PCI 9052 can generate a PCI interrupt from two local bus interrupt
inputs or by software writing to an internal register bit.
•Clock. The PCI 9052 local bus runs from a local TTL clock and generates necessary internal
clocks. This clock runs asynchronously to the PCI clock allowing the local bus to be run at an
independent rate. The buffered PCI bus clock output (BCLKO) may be connected to the local
bus clock (LCLK) input through a 50-Ohm series resistor if desired.
•Programmable local bus configurations. The PCI 9052 supports 8-, 16-, or 32-bit local buses,
which may be multiplexed or non–multiplexed. The PCI 9052 has four byte enables (LBE[3:0]#),
26 address lines (LA[27:2]) and up to 32 data lines (LAD[31:0]).
•Read ahead mode. The PCI 9052 supports Read Ahead mode, where pre-fetched data can be
read from the PCI 9052 internal FIFO instead of from the local bus. Addresses must be
sequential and 32-bit aligned (next address = current address +4).
•Bus drivers. All control, address and data signals generated by the PCI 9052 drive the PCI and
local buses, without the need for external drivers.
•Serial EEPROM interface. The PCI 9052 contains a serial EEPROM interface, used to load
configuration information. This is useful for loading information unique to a particular adapter
(such as Device ID, Vendor ID, and local bus configuration information).
•Four local chip selects. The PCI 9052 provides up to four local bus chip selects (CS[3:0]#).
The base address and range of each are independently programmable from the serial EEPROM
or host.
•Five local address spaces. The base address, range, bus width and timing of each local
address space are independently programmable from the serial EEPROM or host.
•Big/Little Endian byte swapping. The PCI 9052 supports local bus Big and Little Endian byte
ordering. The PCI 9052 also supports Big Endian byte lane mode to redirect the current
word/byte lane during 16- or 8-bit local bus operation.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.3

•Read/write strobe delay and write cycle hold. Read and Write (RD# and WR#) signals can be
delayed from the beginning of a local bus cycle to allow the local bus timing to be tailored to the
requirements of specific peripherals. The Write Cycle Hold option extends the data valid time for
additional clock cycles beyond WR# strobe de-assertion.
•Local bus wait states. In addition to the LRDY# (local ready input) handshake signal for
variable wait state generation, the PCI 9052 has an internal wait state generator to allow the
local bus timing to be tailored to the requirements of specific peripherals. Wait states may be
inserted to adjust the R/W address to data, R/W data to data and R/W data to address times.
•Programmable pre-fetch counter. The local bus pre-fetch counter can be programmed for 0
(no pre-fetch), 4, 8, 16 or Continuous Pre-fetch Mode (pre-fetch counter turned off). The pre-
fetched data can be used as cached data if consecutive long-word aligned addresses are read.
•PCI Read/Write request timeout timer. The PCI 9052 has a programmable PCI Target Retry
Delay Timer, which when expired, generates a RETRY to the PCI bus.
•On-chip ISA interface logic. The PCI 9052 local bus supports single cycle reads/writes for 8- or
16-bit Memory and I/O access cycles on the ISA bus. Local Address Space 0 is used for ISA
Memory space accesses and Local Address Space 1 is used for ISA I/O space accesses.
•PCI LOCK mechanism. The PCI 9052 supports PCI target LOCK sequences. A PCI master can
obtain exclusive access to the PCI 9052 device by locking to the PCI 9052.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
4© 2004 PLX Technology, Inc. All rights reserved.

3. RDK Hardware Architecture
3.1 Architecture Overview
A block diagram of the PCI 9052RDK-LITE board is shown in Figure 3-1. The board is designed to
support the product development of 32-bit, 33 MHz PCI target adapters. It features a PLX PCI 9052
device that interfaces user logic to a 32-bit, 33 MHz PCI bus. An on-board serial EEPROM contains the
data that is loaded into the PCI 9052 configuration registers during board boot-up. A socketed 32 MHz
oscillator drives the local bus side of the RDK. The local bus can be programmed to operate as an 8- or
16-bit ISA bus, or as an 8-, 16-, or 32-bit multiplexed or non-multiplexed address/data bus. A glue-less
ISA bus connector is provided on the board to facilitate the rapid conversion of ISA bus designs to PCI
bus designs. An unpopulated 512KB 8-bit wide ROM socket is provided for memory expansion. The
board supports continuous PCI 9052 burst read/write accesses to 128 Kbytes of SRAM provided in a 32-
bit wide format. An inexpensive 64-macrocell CPLD is used to generate various control signals for the
RDK board. While not required to interface the PCI 9052 to the ISA bus, using a small CPLD makes the
RDK as flexible as possible as a development platform. Additional logic capacity is available in the CPLD
for prototyping. The local bus is brought out to test headers to facilitate the debugging of user designs. A
large prototyping area is provided as well.
PCI 9052
PCI Bus
32-bit, 33MHz
Control
Data
Address
Serial
EEPROM
Clock Div.
by 1,2,4
select
Local Bus
Clock Circuit
32 MHz
Programmable
Logic Device (PLD)
EPM3064ATC100
PC1-21
User connections to
PLD with 15 spare
Clock / 2
Clock / 4
Prototyping
Area &
Footprints
SRAM/ROM CS
config jumpers
ISA
Interface
Connector
Address
Data
Control
ROM
Socket SRAM 32K X 32 Test Headers
Local Bus
32-bit, up to 40MHz
Figure 3-1. PCI 9052RDK-LITE Hardware Block Diagram
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.5

3.2 Hardware Memory Map
Table 3-1. PCI 9052RDK-LITE Default Memory Map
Address Range Device Chip Select Comments
0FFF FFFF
0300 0000 Unused Unused Unused
020F FFFF
0200 0000 ROM Socket CS3#
0101 FFFF
0100 0000 SRAM CS2#
000F FFFF
0000 0000 ISA Memory space
0000 000F
0000 0000 ISA I/O space CS0# & CS1#
In ISA mode the
CS0# & CS1#
pins are
redefined as
MEMRD# and
MEMWR#,
respectively
The address range over which each CSn# is active can be changed by reprogramming the on-board
serial EEPROM. Refer to Table 3-2 Serial EEPROM Contents for a description of the PCI 9052 address
space registers. The SRAM and ROM chip selects can be driven by any PCI 9052 chip select signal.
Refer to Table 3-4 Configuration Jumper Settings to choose a different chip select signal for ROM and
SRAM accesses.
3.3 Serial EEPROM
A 1Kbit serial EEPROM is used for RDK board configuration and PCI 9052 initialization. The serial
EEPROM is connected to the PCI 9052 without any glue logic. The preprogrammed data in the EEPROM
is used to configure the RDK board during boot up. The data includes device and functional information
for plug-and-play (PnP), PCI memory resource allocation and initial values of PCI 9052 internal registers.
Once the RDK initialization is completed, designers can use PLXMon®to change the contents in the
serial EEPROM or reprogram it with user defined data files.
If the Local Clock (LCLK) frequency is set to 8 MHz (JP1[1:2]), rather than to 16-, 32-, or 33-MHz, a
programmed serial EEPROM is required in order to boot the system. If the serial EEPROM is either
missing or blank, PCI 9052 default register values are loaded, and these values enable Expansion ROM
memory and disable delayed reads. At boot time, the BIOS will access the Expansion ROM space;
however, with LCLK at 8 MHz, the PCI 9052RDK-Lite cannot complete the Expansion ROM access prior
to expiration of the Retry Delay Clocks counter. With the programmed EEPROM, the Expansion ROM
request is disabled and delayed reads are enabled to allow booting at reduced LCLK frequency.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
6© 2004 PLX Technology, Inc. All rights reserved.

Table 3-2. Serial EEPROM Contents
Serial
EEPROM
Offset
Register
Offset Register Description Register Bits
Affected Register Values Register Value Description
00h PCI 02h Device ID PCIIDR [31:16] 5201 Device ID for PCI 9052RDK-LITE
02h PCI 00h Vendor ID PCIIDR [15:0] 10B5 PLX Vendor ID
04h PCI 0Ah Class Code PCICCR [23:8] 0680 Other bridge type
06h PCI 08h Class Code / Revision PCICCR [7:0] /
PCIREV [7:0] 0002 PCIREV = current 9052 revision
08h PCI 2Eh Subsystem ID PCISID [15:0] 9050 Default 9052 Subsystem ID
0Ah PCI 2Ch Subsystem Vendor ID PCISVID [15:0] 10B5 PLX Subsystem Vendor ID
0Ch PCI 3Eh
(Maximum Latency and Minimum Grant
are not loadable) Reserved 0
0Eh PCI 3Ch Interrupt Pin /
(Interrupt Line Routing is not loadable) PCIIPR [7:0] /
PCIILR [7:0] 0100 Interrupt pin = INTA#
10h Local 02h MSW of Range for
PCI-to-Local Address Space 0 LAS0RR [31:16] FFF0
12h Local 00h LSW of Range for
PCI-to-Local Address Space 0 LAS0RR [15:0] 0000
1MB local address space for the ISA
Memory space access, mapped into
PCI memory space.
14h Local 06h MSW of Range for
PCI-to-Local Address Space 1 LAS1RR [31:16] FFFF
16h Local 04h LSW of Range for
PCI-to-Local Address Space 1 LAS1RR [15:0] FFF1
16-byte local address space for the ISA
I/O space access, mapped into PCI I/O
space.
18h Local 0Ah MSW of Range for
PCI-to-Local Address Space 2 LAS2RR [31:16] FFFE
1Ah Local 08h LSW of Range for
PCI-to-Local Address Space 2 LAS2RR [15:0] 0000
128KB local address space for the RDK
memory mapped SRAM, mapped into
PCI memory space.
1Ch Local 0Eh MSW of Range for
PCI-to-Local Address Space 3 LAS3RR [31:16] FFF0
1Eh Local 0Ch LSW of Range for
PCI-to-Local Address Space 3 LAS3RR [15:0] 0000
1MB local address space for the RDK
memory mapped ROM, mapped into
PCI memory space.
20h Local 12h MSW of Range for
PCI-to-Local Expansion ROM EROMRR [31:16] 0
22h Local 10h LSW of Range for
PCI-to-Local Expansion ROM EROMRR [15:0] 0 No Expansion ROM range set
24h Local 16h
MSW of Local Base Address (Remap)
for PCI-to-Local Address Space 0 LAS0BA [31:16] 0000
26h Local 14h
LSW of Local Base Address (Remap)
for PCI-to-Local Address Space 0 LAS0BA [15:0] 0001
This space is active from local address
0 for ISA Memory space accesses.
28h Local 1Ah
MSW of Local Base Address (Remap)
for PCI-to-Local Address Space 1 LAS1BA [31:16] 0000
2Ah Local 18h
LSW of Local Base Address (Remap)
for PCI-to-Local Address Space 1 LAS1BA [15:0] 0001
This space is active from local address
0 for ISA I/O space accesses.
2Ch Local 1Eh
MSW of Local Base Address (Remap)
for PCI-to-Local Address Space 2 LAS2BA [31:16] 0100
2Eh Local 1Ch
LSW of Local Base Address (Remap)
for PCI-to-Local Address Space 2 LAS2BA [15:0] 0001
This space is active from local address
01000000h for RDK SRAM accesses.
30h Local 22h
MSW of Local Base Address (Remap)
for PCI-to-Local Address Space 3 LAS3BA [31:16] 0200
32h Local 20h
LSW of Local Base Address (Remap)
for PCI-to-Local Address Space 3 LAS3BA [15:0] 0001
This space is active from local address
02000000h for RDK ROM accesses.
34h Local 26h
MSW of Local Base Address (Remap)
for PCI-to-Local Expansion ROM EROMBA [31:16] 0000
36h Local 24h
LSW of Local Base Address (Remap)
for PCI-to-Local Expansion ROM EROMBA [15:0] 0000
No Expansion ROM enabled – see
EROMRR
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.7

Serial
EEPROM Register Bits Register
Register Register Description Register Value Description
Offset Offset Affected Values
38h Local 2Ah
MSW of Bus Region Descriptors for
Local Address Space 0 LAS0BRD [31:16] 0040
3Ah Local 28h
LSW of Bus Region Descriptors for
Local Address Space 0 LAS0BRD [15:0] 0022
Sets bus width to 16 for ISA Memory
space accesses. No prefetching.
3Ch Local 2Eh
MSW of Bus Region Descriptors for
Local Address Space 1 LAS1BRD [31:16] 0000
3Eh Local 2Ch
LSW of Bus Region Descriptors for
Local Address Space 1 LAS1BRD [15:0] 0022
Sets bus width to 8 for ISA I/O space
accesses. No prefetching.
40h Local 32h
MSW of Bus Region Descriptors for
Local Address Space 2 LAS2BRD [31:16] 0080 Enables bursting & sets bus width to 32
for RDK SRAM. Prefetch enabled.
42h Local 30h
LSW of Bus Region Descriptors for
Local Address Space 2 LAS2BRD [15:0] 0001
44h Local 36h
MSW of Bus Region Descriptors for
Local Address Space 3 LAS3BRD [31:16] 5421
46h Local 34h
LSW of Bus Region Descriptors for
Local Address Space 3 LAS3BRD [15:0] 38E9
Sets timing & bus width to 8 for RDK
ROM. Burst enabled, Prefetch enabled,
Prefetch count=1, NRAD=3, NRDD=3,
NXDA=1, NWAD=2, NWDD=2, RSD=1,
WSD=1, WCH=1
48h Local 3Ah
MSW of Bus Region Descriptors for
Expansion ROM EROMBRD [31:16] 0
4Ah Local 38h
LSW of Bus Region Descriptors for
Expansion ROM EROMBRD [15:0] 0 No Expansion ROM enabled
4Ch Local 3Eh MSW of Chip Select (CS) 0
Base and Range CS0BASE [31:16] 0008
4Eh Local 3Ch LSW of Chip Select (CS) 0
Base and Range CS0BASE [15:0] 0001
As a default this CS is not active as its
pin is used as an ISA bus signal. The
local address range is set from
00000000 to 000FFFFFh to allow
correct ISA Memory space accesses.
50h Local 42h MSW of Chip Select (CS) 1
Base and Range CS1BASE [31:16] 0000
52h Local 40h LSW of Chip Select (CS) 1
Base and Range CS1BASE [15:0] 0009
As a default this CS is not active as its
pin is used as an ISA bus signal. The
local address range is set from
00000000 to 0000000Fh to allow
correct ISA I/O space accesses.
54h Local 46h MSW of Chip Select (CS) 2
Base and Range CS2BASE [31:16] 0101
56h Local 44h LSW of Chip Select (CS) 2
Base and Range CS2BASE [15:0] 0001
This CS is active from local address
01000000 to 0101FFFFh
for RDK SRAM
58h Local 4Ah MSW of Chip Select (CS) 3
Base and Range CS3BASE [31:16] 0208
5Ah Local 48h LSW of Chip Select (CS) 3
Base and Range CS3BASE [15:0] 0001
This CS is active from local address
02000000 to 020FFFFFh
for RDK ROM
5Ch Local 4Eh MSW of Interrupt Control/Status
Register INTCSR [31:16] 0000
5Eh Local 4Ch LSW of Interrupt Control/Status
Register INTCSR [15:0] 115B
Local interrupt 1 enabled, active high
level sensitive. Local interrupt 2
enabled, active high level sensitive.
ISA mode.
60h Local 52h
MSW of Serial EEPROM, control and
miscellaneous control register CNTRL [31:16] 007C
62h Local 50h
LSW of Serial EEPROM, control and
miscellaneous control register CNTRL [15:0] 4252
CS and User pin configuration, ISA I/O
pin configuration, CS2 & CS3 active,
RDK occupies PCI memory & I/O
space, PCI 2.1 features enabled,
PCI Write release enabled,
PCI Direct Slave Retry Delay = Fh.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
8© 2004 PLX Technology, Inc. All rights reserved.

3.4 Local Bus Operating Modes
The PCI 9052 local bus can be programmed to operate in 8- or 16-bit ISA bus mode, 8-,16-, or 32-bit
non-multiplexed address/data bus mode (C-Mode) or 8-, 16-, or 32-bit multiplexed address/data bus (J-
Mode). Programming of the PCI 9052 local bus operation is controlled by the value on the device’s
MODE pins and INTCSR[12] during power-up.
Byte and word local bus accesses are supported in ISA mode, allowing the bus to be populated with 8-
and 16-bit wide devices. Byte, word and long word access are supported in C-Mode and J-Mode, allowing
the bus to be populated with 8-, 16-, and 32-bit wide devices. The local bus ROM and SRAM can be
accessed in all operating modes.
The board ships in ISA mode, allowing customers to connect their own ISA cards to the PCI 9052RDK-
LITE. This facilitates the rapid conversion of ISA bus designs to PCI bus designs. Refer to Table 3-4
Configuration Jumper Settings to reconfigure the local bus operating mode. When operating in ISA mode,
Local Address Spaces 0 and 1 are used for ISA memory and ISA I/O accesses respectively and the local
bus control signals reflect this. However, any accesses to Local Address Spaces 2 and 3 will result in a
normal C mode transaction on the local bus. If Local Address Spaces 2 and 3 are disabled then only the
ISA interface is available on the local bus.
3.4.1 ISA Interface
The PCI 9052RDK-LITE board includes a single ISA socket to allow ISA cards to be accessed via the PCI
bus. The PCI 9052 is connected to this socket without any glue logic. If the designer has an existing ISA
card design that needs to be migrated to PCI, the designer can plug the existing ISA card into the ISA
socket on the RDK and immediately begin developing software on a familiar hardware platform.
The reader should note that there are a few minor exceptions to ISA compatibility. The PCI 9052RDK-
LITE board does not provide –5V to the ISA interface connector. Also, the PCI 9052 does not support ISA
mastering nor ISA DMA operations.
Later in the development cycle, when designing the new PCI card hardware, the designer can choose
whether to use the ‘ISA’ mode of the local bus or the multiplexed or non-multiplexed modes. The standard
multiplexed and non-multiplexed PCI 9052 local bus modes are very simple to interface to and may result
in a much simpler solution than using the ISA mode of the local bus and ISA interface logic from the
original ISA card.
3.5 Static RAM (SRAM)
Four 5V, 9ns, 32Kx8 Static RAMs (U7, U10, U15 and U16) are used on the RDK board. The SRAM is
accessible through the local bus. By default, CS2# is used to access the SRAM but the RDK can be
configured by JP2 to use any CS# for the SRAM socket. Refer to Table 3-4 Configuration Jumper
Settings to use another chip select signal to access the SRAM.
The SRAM can also be accessed by a local bus master by driving the XCSRAM# signal on the CPLD
(prototyping pad PC6) in conjunction with the local bus address, data, control and bus arbitration signals.
The PLXMon software can be used to read and write the SRAM. Refer to the PLXMon User’s Manual on
the SDK CD-ROM for more details. PLXMon allows the designer to view and modify data contents without
writing any code.
3.6 ROM Socket
A 32-pin PLCC socket is provided on the RDK. This can be used to install a 3.3V or 5V, 512Kx8 ROM or
Flash ROM memory device for storing code, either for an expansion ROM or to boot a microprocessor.
The socket is pre-connected to address, data and control lines, GND & VCC. By default, CS3# is used to
access the ROM socket but the RDK can be configured by JP2 to use any CS# for the ROM socket.
Refer to Table 3-4 Configuration Jumper Settings to use another chip select signal to access the SRAM.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.9

The ROM can also be accessed by a local bus master by driving the XCSROM# signal on the CPLD
(prototyping pad PC7) in conjunction with the local bus address, data, control and bus arbitration signals.
Note: When a 3.3V device is used in the ROM socket, please make sure it has 5V-tolerant I/O.
3.7 Test Headers
Six logic analyzer headers are implemented with the standard 0.1”, 2x10 Hewlett Packard configuration.
These headers can be used for signal probing or prototype area expansion. All PCI 9052 local bus,
configuration and status signals are well arranged within these headers. Headers LAH1 and LAH2
contain local bus address signals. Headers LAH3 and LAH4 contain local bus data signals (or multiplexed
address/data signals in the multiplexed mode). Headers LAH5 and LAH6 contain local bus control and
status signals. Designers can use these headers to connect to a standard prototyping board for additional
prototyping. The headers do not provide any power source; therefore, VCC must be connected separately
for prototyping daughter-boards.
3.8 CPLD Functionality
The PCI 9052RDK-LITE includes an Altera EPM3064ATC100 CPLD (U5). This CPLD is used to generate
various control signals for the RDK board. While not required to interface the PCI 9052 to the ISA bus,
using a small CPLD makes the RDK as flexible as possible as a development platform. It performs the
following functions:
•Clock division to generate 16 MHz and 8 MHz signals for LCLK
•Memory strobe generation
•ORing of multiple ISA IRQ lines to generate a single interrupt, minimizing the number of jumpers
that would be required to route multiple IRQ lines to the PCI 9052 LINTi1 local interrupt pin
•Logic to allow optional local bus masters to access the on-board memory
The rest of the device (over 50%) is available to the user for prototyping purposes. There are 15 spare
pins on the CPLD connected to prototyping pads PC1 and PC8-PC21 for linking to other components or
local bus signals.
The CPLD can easily be reprogrammed via the JTAG ISP header J7. The design is provided on the HDK
CD-ROM in the Altera®MAX+PLUS®II graphic design file (.gdf) format. The easiest way to customize
the PLD design is to import the .gdf file into the MAX+PLUS II software and modify the design. The
MAX+PLUS II Baseline version is available free of charge from Altera. Please refer to the Altera website
(www.altera.com) or contact an Altera representative for further details.
For a graphical representation of the program contained within the CPLD, refer to the schematics
contained later in this manual.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
10 © 2004 PLX Technology, Inc. All rights reserved.

3.9 Prototyping Area
The RDK board contains a large prototyping area that contains 28 surface mount footprints, one 0.05”
pitch BGA landscape, a 25x25 0.1” grid through-hole prototyping area and 5 power rails.
Table 3-3. PCI 9052RDK-LITE Board Prototyping Area Footprints
Package Qty. Width & Pitch Destination Comments
32-pin PLCC 1 0.05” pitch FP1 Populated with
PLCC socket
84-pin PLCC 1 0.05” pitch FP2
68-pin PLCC 1 0.05” pitch FP3
44-pin PLCC 1 0.05” pitch FP4
28-pin PLCC 1 0.05” pitch FP5
FP2 to FP5
co-exist at an
84-pin PLCC
area
20-pin PLCC 1 0.05” pitch FP6
16-pin SOIC narrow 4 .150”wide, 0.05” pitch FP7, 8, 15, 16
54-pin TSOP 2 0.8mm pitch FP9, 10
48-pin SSOP 2 .300”wide, 0.025” pitch FP23, 24
20-pin SOIC wide 4 .300”wide, 0.05” pitch FP17, 18,19,20
24-pin SSOP 2 .150”wide, 0.025” pitch FP21, 22
44-pin TQFP 1 0.8mm pitch FP25
16-Pin SSOP 2 .150” wide, 0.025” pitch FP26, 27
208-pin PQFP 1 0.5mm pitch FP28
144-pin TQFP 1 0.5mm pitch FP29
80-pin TQFP 1 0.5mm pitch FP30
FP28, 29, 30
co-exist in a
208-pin PQFP
area
176-pin PQFP 1 0.5mm pitch FP31
100-pin TQFP 1 0.5mm pitch FP32
48-pin TQFP 1 0.5mm pitch FP33
FP31, 32,33
co-exist in a
176-pin PQFP
area
26x26 BGA matrix 1 0.05” pitch
25x25 0.1” through hole area
2 @ 1x30 0.1” through hole rails for 3.3VCC
2 @ 1x30 0.1” through hole rails for GND
1 @ 1x30 0.1” through hole rail for 5VCC
PCI 9052RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved.11

3.9.1 BGA Prototyping
This RDK features a 26x26 @ 0.05” pitch BGA landscape with a plated-hole size of 0.022” diameter +/-
0.001”. Users can prototype with BGA devices by using BGA to PGA adapters.
Referring to Figure 3-2, designers can use one of two methods to prototype with BGA devices. Both
methods require soldering the BGA device to a BGA Land Socket. The Land Socket can then be soldered
directly to the PC board or, optionally, a Minigrid Socket can be soldered to the board and the Land
Socket plugged into the Minigrid Socket.
These sockets are available from Ironwood Electronics (web site: www.ironwoodelectronics.com).
BGA Device
Ironwood BGA
Land Socket
Ironwood Minigrid
Socket (Optional)
RDK PCB
Solder
Plug
Solder
0.014"
0.018"
Figure 3-2. BGA to PGA Conversion
3.10 RDK Board Configuration
Table 3-4 Configuration Jumper Settings explains how to set the jumpers to configure the board. An “X” in
the Default Jumper column denotes the default jumper setting. The serial EEPROM is programmed to
enable Space 0 and Space 1 to operate in ISA mode by default.
PCI 9052RDK-LITE Hardware Reference Manual v1.3
12 © 2004 PLX Technology, Inc. All rights reserved.