Caen V1729 Technical document

Technical
Information
Manual
MOD. V1729
22 June 2005
Revision n. 3
4 CHANNEL/12BIT
SAMPLING ADC
MANUAL REV.3
NPO:
00109/04:V1729.MUTx/03

CAEN will repair or replace any product within the guarantee period if the Guarantor declares
that the product is defective due to workmanship or materials and has not been caused by
mishandling, negligence on behalf of the User, accident or any abnormal conditions or
operations.
CAEN declines all responsibility for damages or
injuries caused by an improper use of the Modules due
to negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's
Manual before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time
and without giving any notice.

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Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3
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TABLE OF CONTENTS
1. GENERAL DESCRIPTION.......................................................................................................................5
1.1 OVERVIEW .............................................................................................................................................5
1.2 SAMPLING FREQUENCY ..........................................................................................................................6
1.3 INPUT SIGNALS, DYNAMIC RANGE..........................................................................................................6
2. OPERATING MODES...............................................................................................................................7
2.1 DEFINITION OF THE ACQUISITION WINDOW. TRIGGER MODES.................................................................7
2.1.1 Principle, PRETRIG, POSTTRIG..................................................................................................7
2.1.2 Trigger sources..............................................................................................................................8
2.1.3 Trigger edge ..................................................................................................................................8
2.1.4 TRIGOUT signal ...........................................................................................................................8
2.2 VALIDATION OF THE TRIGGER BY A SECOND SUBSEQUENT SIGNAL.........................................................9
2.3 DEAD TIME AT RESTARTING OF THE ACQUISITION; PRETRIG.................................................................10
2.4 STANDARD ACQUISITION SEQUENCE.....................................................................................................10
2.5 CORRECTION OF DATA..........................................................................................................................11
2.5.1 Correction of the pedestals..........................................................................................................12
2.5.2 Temporal corrections ..................................................................................................................13
3. SYNCHRONIZATIONS AND CALIBRATIONS.................................................................................16
3.1 SYNCHRONIZATION BETWEEN THE CHANNELS......................................................................................16
3.1.1 Channels from the same board....................................................................................................16
3.1.2 Channels situated on different boards........................................................................................16
3.2 SYNC_OUT AND BUSY SIGNALS ......................................................................................................16
3.3 CALIBRATIONS .....................................................................................................................................17
3.3.1 Calibration of the interpolator....................................................................................................17
3.3.2 Calibration of the pedestals.........................................................................................................20
3.3.3 Temporal calibration between different channels.......................................................................20
4. TECHNICAL SPECIFICATIONS..........................................................................................................21
4.1 PACKAGING..........................................................................................................................................21
4.2 SAMPLING FREQUENCY ........................................................................................................................21
4.3 INPUT SIGNALS, DYNAMIC RANGE........................................................................................................21
4.4 FRONT PANEL.......................................................................................................................................22
4.5 MECHANICAL AND ELECTRICAL STANDARDS........................................................................................23
4.5.1 Mechanical standard...................................................................................................................23
4.5.2 Electrical interfaces.....................................................................................................................23
4.5.3 Summary of front panel signals...................................................................................................24
4.5.4 Supplies .......................................................................................................................................25
4.5.5 Pinout of the non-standard connectors .......................................................................................25
4.5.6 Straps and resistor network sockets ............................................................................................26
4.5.7 Implementation of differential inputs ..........................................................................................26
4.5.8 Using a shifted input range .........................................................................................................27
4.6 INTERFACES .........................................................................................................................................28
4.6.1 VME interface..............................................................................................................................28
4.6.2 GPIB Interface.............................................................................................................................28
4.7 READING OF THE DATA IN THE RAM, MAPPING....................................................................................29
4.8 LIST OF THE SUB-ADDRESSES................................................................................................................31
4.9 SYNOPSIS OF THE BOARD......................................................................................................................35
5. SPECIFICATIONS AND PERFORMANCES.......................................................................................37
6. BIBLIOGRAPHY .....................................................................................................................................38

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Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V1729 4 Channel 12 Bit Sampling ADC 22/06/2005 3
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LIST OF FIGURES
FIG. 1.1: DATA FLOW IN THE BOARD...................................................................................................................5
FIG. 2.1: CHRONOGRAM OF THE STOPPING OF THE ACQUISITION.........................................................................7
FIG. 2.2: CENTERING OF THE TRIGGER IN THE ACQUISITION WINDOW FOR TWO POSTTRIG CASES...................7
FIG. 2.3: SIMPLIFIED DESCRIPTION OF THE TRIGGER SELECTION CHAIN ..............................................................9
FIG. 2.4: SIMPLIFIED DESCRIPTION OF THE TRIGGER VALIDATION SYSTEM........................................................10
FIG. 2.5: BLOCK DIAGRAM OF A STANDARD ACQUISITION ................................................................................12
FIG. 2.6: TWO POSSIBILITIES FOR DETECTION AND FOR TREATMENT OF THE REQUEST......................................13
FIG. 2.7: UNFOLDING OF THE CIRCULAR MEMORY ............................................................................................14
FIG. 3.1: DIAGRAM OF THE CALIBRATION OF THE VERNIERS.............................................................................18
FIG. 4.1: MOD. V1729 FRONT PANEL..............................................................................................................22
FIG. 4.2: IMPLEMENTATION OF THE CONNECTORS AND CONFIGURATION ELEMENTS ON THE V1729.................23
FIG. 4.3: SYNOPSIS OF THE V1729 BOARD........................................................................................................35
FIG. 4.4: SYNOPSIS OF AN ACQUISITION CHANNEL ON THE MATACQ BOARD .................................................36

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1. General description
1.1 Overview
The CAEN Mod. V1729 board is suited for acquisition of fast analog signals based on the
MATACQ (analog matrix) chip developed by collaboration of the CEA/DAPNIA and the
l’IN2P3/LAL [1].
The V1729 board, in the mechanical format VME double Europe, is compatible with
several standards of acquisition (VME A32/D32, A24/D16, and GPIB).
This board performs the coding of 4 analog channels of bandwidth up to 300MHz over 12
bits at a sampling frequency (Fe) reaching up to 2GHz and over a depth of 2520 usable
points.
This operation is realized in three phases (see Fig 1.1):
Acquisition :
the analog signal is continuously sampled at the frequency Fe in a circular analog
memory. The arrival of a trigger signal initiates the stopping phase of the sampling (2.1.1.
At the end of this phase, the state of the memory is set : it then contains the last 2560
points sampled (of which 2520 are valid).
Numerization and storage :
after a stopping order of the acquisition, the samples stored under analog form in the
MATACQ chips are rapidly (650µs) re-read and coded into digital data over 12 bits, then
stored in a digital memory buffer. The acquisition is informed of the end of the coding
phase either by scrutation of an internal register, or by an interruption.
Reading :
the memory buffer can then be re-read by the acquisition system. For an acquisition
system of VME A24-D16 standard, the latter operation lasts a few ms for the full readout
of a 4-channel board, which permits attaining an acquisition frequency of a few hundred
Hz for the acquisition of 2500 points per channel. With a high performance A32-D32
system, one should reach 1 kHz.
Fig. 1.1: data flow in the board
D
IGITALANALOG
SAMPLING
MATRIX DIGITAL
MEMORY
BUFFER
ADC Acquisition
Input
F
e = 1GS/s or 2GS/s 5 MHz Up to 3MO/s in GPIB
and 20MO/s in VME

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1.2 Sampling frequency
The V1729 board is sequenced by an oscillator at a frequency of 100MHz. No greater
frequency signal exists on the board. This is what explains the low consumption of the
system. The sampling at a very high frequency (Fe) in the MATACQ chip is in fact
realized by virtual multiplication of frequency inside the chip by a factor up to 20.
The MATACQ chip functions with a pilot frequency of 50MHz or 100MHz programmable
on the board by software, which corresponds to a sampling frequency Fe (= 20*Fp) of 1
or 2 GHz.
The EXT_CLK input may possibly be used to inject a very clean external pilot clock
comprised between 50MHz and 100MHz.
Caution : the MATACQ chip cannot work properly with a pilot frequency Fp lower than
50MHz.
1.3 Input signals, Dynamic range
The V1729 board integrates 4 analog channels. The inputs of these channels are
connected through double LEMO plugs (IN0+/- to IN3+/-).
The inputs are by default unipolar and terminated on 50 Ohms. However, the input levels
of the board can be very easily modified (through displacing a few resistors and mounting
new ones) in such a way as to permit the input in differential mode (from which the
double LEMO plugs). For this purpose, free CMS-805 resistor footprints are indeed
implemented on the V1729 board.
The analog to digital conversion is made on 12 bits with a maximum dynamic range of
1V, or an LSB of 250μV. This range is centered on 0V (+/- 0.5V). However, free CMS-
805 footprints are implemented on the V1729 board for shifting the dynamic range in the
interval +/- 0.5V in order to be able to optimize the system for unipolar signals.
The measured noise referred to input is less than 200 μV RMS (i-e below the lsb of the
ADC), and the non-linearity remains below 1 per 1000 over the whole dynamic range.

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2. Operating modes
2.1 Definition of the acquisition window. Trigger modes
2.1.1 Principle, PRETRIG, POSTTRIG
During the acquisition, the analog signal is continuously sampled in the analog memory
which is comparable to a circular buffer with a depth of 2560 points (time depth =
2560/Fe). The stopping of sampling is initiated by the arrival of a trigger signal Ta
(asynchronous trigger) which is common to all the channels of a board. This signal is
only authorized to be produced following a programmable time named PRETRIG after
the triggering of the acquisition sequence.
The effective stopping of the sampling will occur following a pre-defined number (named
POSTTRIG) of clock periods (50MHz or 100MHz) after the trigger (see Fig. 2.1).
Fig. 2.1: chronogram of the stopping of the acquisition
The POSTTRIG, programmable by the user, permits defining and displacing the position
of the trigger signal in the acquisition window. It is adjustable in the 1/Fp to 65535/Fp
range by steps of 1/Fp ( = 20ns or 10ns). This is illustrated in Fig 2.2.
In the example illustrated by Fig 2.2, the POSTTRIG is fixed at 6/Fp. The acquisition will
be stopped 6/Fp + ti after the arrival of the trigger signal (ti corresponds to the time
measured by the vernier between the Ta and the next rising edge of the clock). The
analog memory will then contain the 2560 last samples (of which only 2520 will be
exploited).
Fig. 2.2: centering of the Trigger in the acquisition window for two POSTTRIG cases
Thus, a POSTTRIG value close to 64 assures the centering of the trigger in the middle of
the acquisition window. For the values of POSTTRIG > 127, the trigger is no longer in the
acquisition window.
1/Fp
Rising Edge of Oscillator
Clock
Ta
ti
Acquisition
Stopping o
f
acquisition
POSTTRIG : here
= 6/Fp
Ta Ta
High value of POSTTRIG Low value of POSTTRIG
Asynchronous trigger

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2.1.2 Trigger sources
There are four possible sources for the trigger signal Ta. They are selectable by the user:
Trigger on signal : this is the result of the logic « OR » of the discriminators on the
analog signals of one or several channels of the board by choice of the user. The
common threshold of the discriminators is programmable by steps of 0.25 mV over a
range of ± 0.5V (which corresponds to the integrality of the usable input range of the
board). The user can also define the type of discrimination (signal higher than or inferior
to the threshold) via the choice of the trigger edge.
External trigger : external trigger signal entering on a LEMO plug (EXT_TRIG signal at
the NIM level). This signal can be either used as any other trigger source with choice of
its edge, or exploited directly as an asynchronous trigger (rising edge only) in cases
where one uses discriminators from several boards in order to produce at the exterior of
the boards (via their output TRIG_OUT) a trigger which will be sent back to them in a
synchronous way (see figure 2.2). This mode is selected by the bit 4 of the TRIG_TYPE
register.
Auto trigger : triggered by a software command issued from the acquisition. It permits
the generation of a random trigger. This corresponds to the automatic trigger mode.
- « Auto + normal » trigger : result of a logic « OR » between the trigger on signal and
the automatic trigger.
- Internal random trigger : this internal periodic signal, asynchronous of the clock, can
be enabled or disabled. When it is enabled and the trigger mode selected is « auto », this
signal serves as a source for the automatic trigger. One uses it for the fast calibration of
the verniers of the MATACQ chips.
2.1.3 Trigger edge
The trigger edge (rising or falling) can be selected in all modes (except the direct external
trigger which uses only the rising edge).
2.1.4 TRIGOUT signal
A copy of the pre-trigger signal (positive pulse) generated by the V1729 board is
available at the output on a LEMO plug on the front panel (TRIG_OUT output on the NIM
level). It can in particular permit synchronization of trigger for several boards.
A simplified summary of the trigger modes of the board is presented in fig 2.3.

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Fig. 2.3: simplified description of the trigger selection chain
2.2 Validation of the trigger by a second subsequent signal.
In the case where one would like to validate the data stored in the MATACQ chips before
their transfer towards the RAM, it is possible to make use of the EXT_EN_TRIG input to
introduce therethrough a validation signal (see figure 3c). This is particularly useful if the
system produces such a signal with a delay greater than the maximum sampling depth
(2560/Fp i-e 1.25μs at 2GS/s and 2.5μs at 1GS/s) and smaller than the transfer time
towards the RAM (650μs). This can thus permit a big decrease of the potential dead-time
linked to the readout. In this case, the usual use of the EXT_EN_TRIG signal (which
permits inhibiting the trigger as described on figure 3b) is inhibited.
In order to perform the validation, a programmable 8-bit latency counter ( called
POST_STOP_LATENCY) with steps of 2.5μs is started at the end of the POSTTRIG,
and if the external validation signal hasn’t arrived before the end of that delay, the
Matacq chips switch back into the analog input signal writing mode thus waiting for the
next trigger. If on the other hand the validation signal did arrive, the waiting data is
digitized then stored into the RAM. This mode is validated thanks to the bit 5 of the
TRIGGER_TYPE register (see IV.4). Moreover, a second 8-bit register ( called
POST_LATENCY_PRETRIG) with the same steps of 2.5μs permits the programming of
the time to wait before enabling the trigger again if the validation didn’t occur. The
minimum time for refilling is of 1.25μs at 2GS/s and of 2.5μs at 1GS/s. The minimum
value in that register is thus 1.
TRIGA
Ch0
Ch1
Ch2
Ch3
DAC threshold
TRIG enable
Select Select
Select
TRIG_OUT
TRIG_AUTO
E
XT TRIG
EnCh0
+
- EnCh1
+
- EnCh2
+
- EnCh3
+
-
E
XT EN TRIG
I
n italics with arrows : front panel signals.

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Fig. 2.4: simplified description of the trigger validation system.
2.3 Dead time at restarting of the acquisition; Pretrig
The frequency of the clock present on the board is relatively low (50MHz or 100MHz). In
order to be able to sample at a rate equal to or greater than the Giga-sample per second,
the MATACQ chips realize a virtual multiplication of frequency. This multiplication
requires a servo of which the control loop is interrupted at the time of the data read cycle.
At the time of the start of the acquisition, this servo has to get locked again. This
implicates a typical waiting of 150μs before being able to reach the optimum of the
sampling performances.
For this reason, at each restarting of the acquisition, the board must automatically
generate a dead time during which the triggers are not accepted.
This dead time is adjustable by the PRETRIG, from 1 to 65535 times the period of the
main clock. The minimal recommended PRETRIG values are therefore:
• 7500 (decimal) for a clock frequency of Fp = 50MHz.
• 15000 (decimal) for a clock frequency of Fp = 100MHz.
2.4 Standard acquisition sequence
Fig 2.4 shows the standard course of an acquisition :
The sequence begins with the initialization of the board by a RESET order.
Next, the different parameters which are not used with their default value must be
programmed (PRETRIG, POSTTRIG, TRIGGER TYPE, TRIGGER EDGE, MASK, NB
OF COL TO READ, FP FREQUENCY, …).
The starting order of the acquisition is next sent.