Caen V1729 Technical document

Technical
Information
Manual
MOD. V1729
22 June 2005
Revision n. 3
4 CHANNEL/12BIT
SAMPLING ADC
MANUAL REV.3
NPO:
00109/04:V1729.MUTx/03

CAEN will repair or replace any product within the guarantee period if the Guarantor declares
that the product is defective due to workmanship or materials and has not been caused by
mishandling, negligence on behalf of the User, accident or any abnormal conditions or
operations.
CAEN declines all responsibility for damages or
injuries caused by an improper use of the Modules due
to negligence on behalf of the User. It is strongly
recommended to read thoroughly the CAEN User's
Manual before any kind of operation.
CAEN reserves the right to change partially or entirely the contents of this Manual at any time
and without giving any notice.

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TABLE OF CONTENTS
1. GENERAL DESCRIPTION.......................................................................................................................5
1.1 OVERVIEW .............................................................................................................................................5
1.2 SAMPLING FREQUENCY ..........................................................................................................................6
1.3 INPUT SIGNALS, DYNAMIC RANGE..........................................................................................................6
2. OPERATING MODES...............................................................................................................................7
2.1 DEFINITION OF THE ACQUISITION WINDOW. TRIGGER MODES.................................................................7
2.1.1 Principle, PRETRIG, POSTTRIG..................................................................................................7
2.1.2 Trigger sources..............................................................................................................................8
2.1.3 Trigger edge ..................................................................................................................................8
2.1.4 TRIGOUT signal ...........................................................................................................................8
2.2 VALIDATION OF THE TRIGGER BY A SECOND SUBSEQUENT SIGNAL.........................................................9
2.3 DEAD TIME AT RESTARTING OF THE ACQUISITION; PRETRIG.................................................................10
2.4 STANDARD ACQUISITION SEQUENCE.....................................................................................................10
2.5 CORRECTION OF DATA..........................................................................................................................11
2.5.1 Correction of the pedestals..........................................................................................................12
2.5.2 Temporal corrections ..................................................................................................................13
3. SYNCHRONIZATIONS AND CALIBRATIONS.................................................................................16
3.1 SYNCHRONIZATION BETWEEN THE CHANNELS......................................................................................16
3.1.1 Channels from the same board....................................................................................................16
3.1.2 Channels situated on different boards........................................................................................16
3.2 SYNC_OUT AND BUSY SIGNALS ......................................................................................................16
3.3 CALIBRATIONS .....................................................................................................................................17
3.3.1 Calibration of the interpolator....................................................................................................17
3.3.2 Calibration of the pedestals.........................................................................................................20
3.3.3 Temporal calibration between different channels.......................................................................20
4. TECHNICAL SPECIFICATIONS..........................................................................................................21
4.1 PACKAGING..........................................................................................................................................21
4.2 SAMPLING FREQUENCY ........................................................................................................................21
4.3 INPUT SIGNALS, DYNAMIC RANGE........................................................................................................21
4.4 FRONT PANEL.......................................................................................................................................22
4.5 MECHANICAL AND ELECTRICAL STANDARDS........................................................................................23
4.5.1 Mechanical standard...................................................................................................................23
4.5.2 Electrical interfaces.....................................................................................................................23
4.5.3 Summary of front panel signals...................................................................................................24
4.5.4 Supplies .......................................................................................................................................25
4.5.5 Pinout of the non-standard connectors .......................................................................................25
4.5.6 Straps and resistor network sockets ............................................................................................26
4.5.7 Implementation of differential inputs ..........................................................................................26
4.5.8 Using a shifted input range .........................................................................................................27
4.6 INTERFACES .........................................................................................................................................28
4.6.1 VME interface..............................................................................................................................28
4.6.2 GPIB Interface.............................................................................................................................28
4.7 READING OF THE DATA IN THE RAM, MAPPING....................................................................................29
4.8 LIST OF THE SUB-ADDRESSES................................................................................................................31
4.9 SYNOPSIS OF THE BOARD......................................................................................................................35
5. SPECIFICATIONS AND PERFORMANCES.......................................................................................37
6. BIBLIOGRAPHY .....................................................................................................................................38

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LIST OF FIGURES
FIG. 1.1: DATA FLOW IN THE BOARD...................................................................................................................5
FIG. 2.1: CHRONOGRAM OF THE STOPPING OF THE ACQUISITION.........................................................................7
FIG. 2.2: CENTERING OF THE TRIGGER IN THE ACQUISITION WINDOW FOR TWO POSTTRIG CASES...................7
FIG. 2.3: SIMPLIFIED DESCRIPTION OF THE TRIGGER SELECTION CHAIN ..............................................................9
FIG. 2.4: SIMPLIFIED DESCRIPTION OF THE TRIGGER VALIDATION SYSTEM........................................................10
FIG. 2.5: BLOCK DIAGRAM OF A STANDARD ACQUISITION ................................................................................12
FIG. 2.6: TWO POSSIBILITIES FOR DETECTION AND FOR TREATMENT OF THE REQUEST......................................13
FIG. 2.7: UNFOLDING OF THE CIRCULAR MEMORY ............................................................................................14
FIG. 3.1: DIAGRAM OF THE CALIBRATION OF THE VERNIERS.............................................................................18
FIG. 4.1: MOD. V1729 FRONT PANEL..............................................................................................................22
FIG. 4.2: IMPLEMENTATION OF THE CONNECTORS AND CONFIGURATION ELEMENTS ON THE V1729.................23
FIG. 4.3: SYNOPSIS OF THE V1729 BOARD........................................................................................................35
FIG. 4.4: SYNOPSIS OF AN ACQUISITION CHANNEL ON THE MATACQ BOARD .................................................36

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1. General description
1.1 Overview
The CAEN Mod. V1729 board is suited for acquisition of fast analog signals based on the
MATACQ (analog matrix) chip developed by collaboration of the CEA/DAPNIA and the
l’IN2P3/LAL [1].
The V1729 board, in the mechanical format VME double Europe, is compatible with
several standards of acquisition (VME A32/D32, A24/D16, and GPIB).
This board performs the coding of 4 analog channels of bandwidth up to 300MHz over 12
bits at a sampling frequency (Fe) reaching up to 2GHz and over a depth of 2520 usable
points.
This operation is realized in three phases (see Fig 1.1):
Acquisition :
the analog signal is continuously sampled at the frequency Fe in a circular analog
memory. The arrival of a trigger signal initiates the stopping phase of the sampling (2.1.1.
At the end of this phase, the state of the memory is set : it then contains the last 2560
points sampled (of which 2520 are valid).
Numerization and storage :
after a stopping order of the acquisition, the samples stored under analog form in the
MATACQ chips are rapidly (650µs) re-read and coded into digital data over 12 bits, then
stored in a digital memory buffer. The acquisition is informed of the end of the coding
phase either by scrutation of an internal register, or by an interruption.
Reading :
the memory buffer can then be re-read by the acquisition system. For an acquisition
system of VME A24-D16 standard, the latter operation lasts a few ms for the full readout
of a 4-channel board, which permits attaining an acquisition frequency of a few hundred
Hz for the acquisition of 2500 points per channel. With a high performance A32-D32
system, one should reach 1 kHz.
Fig. 1.1: data flow in the board
D
IGITALANALOG
SAMPLING
MATRIX DIGITAL
MEMORY
BUFFER
ADC Acquisition
Input
F
e = 1GS/s or 2GS/s 5 MHz Up to 3MO/s in GPIB
and 20MO/s in VME

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1.2 Sampling frequency
The V1729 board is sequenced by an oscillator at a frequency of 100MHz. No greater
frequency signal exists on the board. This is what explains the low consumption of the
system. The sampling at a very high frequency (Fe) in the MATACQ chip is in fact
realized by virtual multiplication of frequency inside the chip by a factor up to 20.
The MATACQ chip functions with a pilot frequency of 50MHz or 100MHz programmable
on the board by software, which corresponds to a sampling frequency Fe (= 20*Fp) of 1
or 2 GHz.
The EXT_CLK input may possibly be used to inject a very clean external pilot clock
comprised between 50MHz and 100MHz.
Caution : the MATACQ chip cannot work properly with a pilot frequency Fp lower than
50MHz.
1.3 Input signals, Dynamic range
The V1729 board integrates 4 analog channels. The inputs of these channels are
connected through double LEMO plugs (IN0+/- to IN3+/-).
The inputs are by default unipolar and terminated on 50 Ohms. However, the input levels
of the board can be very easily modified (through displacing a few resistors and mounting
new ones) in such a way as to permit the input in differential mode (from which the
double LEMO plugs). For this purpose, free CMS-805 resistor footprints are indeed
implemented on the V1729 board.
The analog to digital conversion is made on 12 bits with a maximum dynamic range of
1V, or an LSB of 250μV. This range is centered on 0V (+/- 0.5V). However, free CMS-
805 footprints are implemented on the V1729 board for shifting the dynamic range in the
interval +/- 0.5V in order to be able to optimize the system for unipolar signals.
The measured noise referred to input is less than 200 μV RMS (i-e below the lsb of the
ADC), and the non-linearity remains below 1 per 1000 over the whole dynamic range.

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2. Operating modes
2.1 Definition of the acquisition window. Trigger modes
2.1.1 Principle, PRETRIG, POSTTRIG
During the acquisition, the analog signal is continuously sampled in the analog memory
which is comparable to a circular buffer with a depth of 2560 points (time depth =
2560/Fe). The stopping of sampling is initiated by the arrival of a trigger signal Ta
(asynchronous trigger) which is common to all the channels of a board. This signal is
only authorized to be produced following a programmable time named PRETRIG after
the triggering of the acquisition sequence.
The effective stopping of the sampling will occur following a pre-defined number (named
POSTTRIG) of clock periods (50MHz or 100MHz) after the trigger (see Fig. 2.1).
Fig. 2.1: chronogram of the stopping of the acquisition
The POSTTRIG, programmable by the user, permits defining and displacing the position
of the trigger signal in the acquisition window. It is adjustable in the 1/Fp to 65535/Fp
range by steps of 1/Fp ( = 20ns or 10ns). This is illustrated in Fig 2.2.
In the example illustrated by Fig 2.2, the POSTTRIG is fixed at 6/Fp. The acquisition will
be stopped 6/Fp + ti after the arrival of the trigger signal (ti corresponds to the time
measured by the vernier between the Ta and the next rising edge of the clock). The
analog memory will then contain the 2560 last samples (of which only 2520 will be
exploited).
Fig. 2.2: centering of the Trigger in the acquisition window for two POSTTRIG cases
Thus, a POSTTRIG value close to 64 assures the centering of the trigger in the middle of
the acquisition window. For the values of POSTTRIG > 127, the trigger is no longer in the
acquisition window.
1/Fp
Rising Edge of Oscillator
Clock
Ta
ti
Acquisition
Stopping o
f
acquisition
POSTTRIG : here
= 6/Fp
Ta Ta
High value of POSTTRIG Low value of POSTTRIG
Asynchronous trigger

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2.1.2 Trigger sources
There are four possible sources for the trigger signal Ta. They are selectable by the user:
Trigger on signal : this is the result of the logic « OR » of the discriminators on the
analog signals of one or several channels of the board by choice of the user. The
common threshold of the discriminators is programmable by steps of 0.25 mV over a
range of ± 0.5V (which corresponds to the integrality of the usable input range of the
board). The user can also define the type of discrimination (signal higher than or inferior
to the threshold) via the choice of the trigger edge.
External trigger : external trigger signal entering on a LEMO plug (EXT_TRIG signal at
the NIM level). This signal can be either used as any other trigger source with choice of
its edge, or exploited directly as an asynchronous trigger (rising edge only) in cases
where one uses discriminators from several boards in order to produce at the exterior of
the boards (via their output TRIG_OUT) a trigger which will be sent back to them in a
synchronous way (see figure 2.2). This mode is selected by the bit 4 of the TRIG_TYPE
register.
Auto trigger : triggered by a software command issued from the acquisition. It permits
the generation of a random trigger. This corresponds to the automatic trigger mode.
- « Auto + normal » trigger : result of a logic « OR » between the trigger on signal and
the automatic trigger.
- Internal random trigger : this internal periodic signal, asynchronous of the clock, can
be enabled or disabled. When it is enabled and the trigger mode selected is « auto », this
signal serves as a source for the automatic trigger. One uses it for the fast calibration of
the verniers of the MATACQ chips.
2.1.3 Trigger edge
The trigger edge (rising or falling) can be selected in all modes (except the direct external
trigger which uses only the rising edge).
2.1.4 TRIGOUT signal
A copy of the pre-trigger signal (positive pulse) generated by the V1729 board is
available at the output on a LEMO plug on the front panel (TRIG_OUT output on the NIM
level). It can in particular permit synchronization of trigger for several boards.
A simplified summary of the trigger modes of the board is presented in fig 2.3.

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Fig. 2.3: simplified description of the trigger selection chain
2.2 Validation of the trigger by a second subsequent signal.
In the case where one would like to validate the data stored in the MATACQ chips before
their transfer towards the RAM, it is possible to make use of the EXT_EN_TRIG input to
introduce therethrough a validation signal (see figure 3c). This is particularly useful if the
system produces such a signal with a delay greater than the maximum sampling depth
(2560/Fp i-e 1.25μs at 2GS/s and 2.5μs at 1GS/s) and smaller than the transfer time
towards the RAM (650μs). This can thus permit a big decrease of the potential dead-time
linked to the readout. In this case, the usual use of the EXT_EN_TRIG signal (which
permits inhibiting the trigger as described on figure 3b) is inhibited.
In order to perform the validation, a programmable 8-bit latency counter ( called
POST_STOP_LATENCY) with steps of 2.5μs is started at the end of the POSTTRIG,
and if the external validation signal hasn’t arrived before the end of that delay, the
Matacq chips switch back into the analog input signal writing mode thus waiting for the
next trigger. If on the other hand the validation signal did arrive, the waiting data is
digitized then stored into the RAM. This mode is validated thanks to the bit 5 of the
TRIGGER_TYPE register (see IV.4). Moreover, a second 8-bit register ( called
POST_LATENCY_PRETRIG) with the same steps of 2.5μs permits the programming of
the time to wait before enabling the trigger again if the validation didn’t occur. The
minimum time for refilling is of 1.25μs at 2GS/s and of 2.5μs at 1GS/s. The minimum
value in that register is thus 1.
TRIGA
Ch0
Ch1
Ch2
Ch3
DAC threshold
TRIG enable
Select Select
Select
TRIG_OUT
TRIG_AUTO
E
XT TRIG
EnCh0
+
- EnCh1
+
- EnCh2
+
- EnCh3
+
-
E
XT EN TRIG
I
n italics with arrows : front panel signals.

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Fig. 2.4: simplified description of the trigger validation system.
2.3 Dead time at restarting of the acquisition; Pretrig
The frequency of the clock present on the board is relatively low (50MHz or 100MHz). In
order to be able to sample at a rate equal to or greater than the Giga-sample per second,
the MATACQ chips realize a virtual multiplication of frequency. This multiplication
requires a servo of which the control loop is interrupted at the time of the data read cycle.
At the time of the start of the acquisition, this servo has to get locked again. This
implicates a typical waiting of 150μs before being able to reach the optimum of the
sampling performances.
For this reason, at each restarting of the acquisition, the board must automatically
generate a dead time during which the triggers are not accepted.
This dead time is adjustable by the PRETRIG, from 1 to 65535 times the period of the
main clock. The minimal recommended PRETRIG values are therefore:
• 7500 (decimal) for a clock frequency of Fp = 50MHz.
• 15000 (decimal) for a clock frequency of Fp = 100MHz.
2.4 Standard acquisition sequence
Fig 2.4 shows the standard course of an acquisition :
The sequence begins with the initialization of the board by a RESET order.
Next, the different parameters which are not used with their default value must be
programmed (PRETRIG, POSTTRIG, TRIGGER TYPE, TRIGGER EDGE, MASK, NB
OF COL TO READ, FP FREQUENCY, …).
The starting order of the acquisition is next sent.

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The user if necessary sends a software trigger (in the case of an automatic trigger)
having taken care to wait at least the time necessary for the PRETRIG.
- The program then waits for a request emitted by the V1729 board when the data are
ready to be read. For this, there exist two possibilities illustrated by Fig 2.5 :
Waiting and handling of an interruption (SRQ in GPIB, IRQ3 in VME).
Regular scanning of the LSB of the interruption register (INTERRUPT h80).
In both cases, the user should acknowledge the request by writing a 0 in the
INTERRUPT register, but the latter is anyhow reset by the START_ACQ command. The
first solution has the big advantage of being less noisy for the front-end of the board.
- The user can then partially or wholly read the data stored in the board. This includes :
the values of the vernier and of the samples (see 4.7 )
the value of TRIG_REC which permits determination of the position of the trigger in the
acquisition window (see 2.5.2)
- The user must correct the data before using it (see 2.5):
By subtracting the pedestals (see 2.1.1).
By reordering the data (see 2.5.2).
These operations can be executed on-line or off-line according to the context.
2.5 Correction of data
The raw data extracted from the board must be treated before really being usable.
This treatment consists of two operations :
Correction of the pedestals.
Reordering and time alignment of the data.

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Fig. 2.5: block diagram of a standard acquisition
2.5.1 Correction of the pedestals
The analog memories of the MATACQ chips present by design dispersions of pedestal
from cell to cell which can reach several tens of mV. On the other hand, the pedestal of a
data cell is extremely reproducible (250µV RMS). Due to the structure of the chip, the
dispersion of the pedestals presents a principal periodicity of 20 cells, followed by a tiny
individual distribution. If not compensated, this dispersion will appear as a noise at the
reconstruction of the signal because of the random position of the trigger in the matrix.
Board Parameters Initialization
Send START
A
CQUISITIO
N
Wait for REQUEST
Trigger
auto ?
Send SOFT TRIGGER
yes
no
Read Data:
• Read verniers & samples.
• Read TRIG_REC
Correct & Reorder Data:
• Subtract pedestals.
• Reorder data & calculate times
next acquisition
Send RESET BOARD
Wait for end of PRETRIG

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Fig. 2.6: two possibilities for detection and for treatment of the request
In order to obtain the nominal noise performances (signal to noise ratio of 73 to 74dB),
the pedestals, which are stable in time and with temperature, must be removed by the
acquisition software individually cell by cell. Since the pedestal of a cell is linked to its
physical location and not to its position in relation to the Trigger, it is necessary to
realize this removal BEFORE reordering the data.
A method of calibration of the pedestals is demonstrated in section 3.3.2.
2.5.2 Temporal corrections
The signal is sampled in a circular memory. The first operation necessary for the
treatment of the data is therefore to « unfold » the circular memory in order to obtain a
table of 2560 temporally ordered data (see Fig 2.6). This can be done, by example, by
realizing a rotation of :
ROT = (TRIG_REC - POSTTRIG ) * 20
cells towards the left of the data table issued from the RAM.
Or, equivalently through a calculation of a new index number for each data :
(2) NEWi = (2560 + OLDi – END_CELL) modulo 2560
where END_CELL is the index of the last written cell :
END_CELL = 20 * (POSTTRIG + TRIG_REC) modulo128
The trigger signal (asynchronous trigger) Ta is the absolute reference which serves to
temporally realign the data. In order to find its position, one uses the information provided
by a temporal interpolator (vernier) measuring ti, time interval separating the arrival of Ta
from the next rising edge of the Fp clock.
Interrupt request
acknowledge => clear
INTERRUPT
REGISTER
Bit 0 =1
?
yes
Read INTERRUPT REGISTER
no
Interrupt request
acknowledge => clear
INTERRUPT
REGISTER
continue
Asynchronous Interrupt detected
by hardware (IRQ3 or SRQ)

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Fig. 2.7: unfolding of the circular memory
This information associated with the MINVER and MAXVER calibration constants (see
3.3.1 permits determination of the position of the Trigger and therefore realignment of the
data with a precision in the region of 50ps RMS. This realignment is unnecessary if the
user simply desires to study the signal shape and in this case, the curve acquired will
present a jitter of a period of Fp. The information of the 4 verniers from the same board
being redundant in order to realize the temporal adjustement, it is therefore possible :
- to use solely the vernier from the channel 0.
- to use the vernier i for the channel i.
- to calculate the mean of the 4 verniers in order to refine the time precision.
The following formula permits determination of the time of each point of the reordered
table, with by convention a time origin (Time = 0) at the arrival of the Trigger.
(3) Time[NEWi] = DT0 + {NEWi - 20 *[128 - POSTTRIG + Correc_Ver]} * dT
With:
(4) Correc_Ver = (VERNIER - MINVER) / (MAXVER - MINVER)
Writing
direction
Last cell
=cell n
trigger
cell
n+1
cell
n+2
cell
127
cell 0
cell 1 cell i
cell n -1
cell …
cell …
1.1.1.1.1.1.1.1
P
1.1.1.1.1.1.1.
2
REORDERED
ARRAY
CIRCULAR
BUFFER
S
T
A
R
T
T
R
I
G
E
N
D
cell …
cell …

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Where:
dT is the sampling period (500ps or 1ns)
DT0 is a fixed temporal offset, close to 0, due to signal propagation times in the board (of
which the calibration is described in 3.1.1)
An alternative but equivalent solution, consists in generating the reordered table through
a rotation towards the left of the data of :
(1b) ROT = (TRIG_REC - POSTTRIG ) * 20 – INT(Correc_Ver*20) cells
where INT corresponds to rounding off to the nearest whole number.
The trigger is then situated at a time
(5) tT= [Correc_Ver*20– INT(Correc_Ver*20)]* dT
before the cell numbered 20*(128-POSTTRIG) (plus the offset DT0).

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3. Synchronizations and calibrations
3.1 Synchronization between the channels
3.1.1 Channels from the same board
A single trigger signal is used for all of the channels from the same board. The
acquisition of these channels will therefore naturally be synchronous, with a typical jitter
of only 20ps RMS. The possible temporal offset dT0, constant, between the channels
(principally due to the propagation of the trigger signal on the board, but also to the
different lengths of cables at the inputs) will be calibrated once for all. This calibration is
executed by sending a same signal on all of the inputs and by looking for the fine position
of the trigger on each of the channels.
In the case where the board is triggered on one of the input signals, a fine
synchronisation method consists of interpolating by software the crossing of the signal
through the trigger threshold on the given channel, this permitting the fine datation of all
the measured channels.
3.1.2 Channels situated on different boards
The synchronization is only possible if the trigger source is common to the different
boards. For this, several possibilities can be envisaged :
- to use an external trigger signal common to all of the boards.
- to generate the trigger signal on a fixed board (master) which triggers itself and to send
its TRIG_OUT signal output to the external trigger input of the other boards (via a NIM
buffer if there is more than one target board).
- to generate the trigger signal on any one of the boards. The TRIG_OUT outputs of all of
the boards will then be connected on an external NIM logic then the result will be
redistributed in a synchronous fashion to all the boards via their EXT_TRIG input. It is
this latter input which will then be programmed as the source of the asynchronous trigger
via the bit 4 of the TRIGGER_TYPE register on all the boards.
In all cases a calibration of the temporal offset between the boards is necessary. This
calibration, similar to that which is necessary to align the channels from the same board,
will be dependent upon the set-up (length of the cables…).
3.2 SYNC_OUT and BUSY signals
One of the NIM outputs of the front panel can be configured either as a SYNC_OUT, or
as a BUSY respectively with the help of the S4 and S2 straps. SYNC_OUT is a
synchronization signal corresponding to the writing in the first cell of the second column
of the circular analog memory, and which can be made available on the front panel. For
certain applications, this signal can permit triggering of the source analog signals and
thus guaranties their fixed position in the memory. Thus, if the temporal occupation of the
signals to acquire is low, the user will have the possibility to only re-read the beginning of
the depth of the analog memory and to thus limit the dead time linked to the acquisition.

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BUSY is a signal destined to inform the external world that the board is not ready to
receive a signal (it is either idle, or in the process of transferring data between the
MATACQ chips and the RAM, or at the beginning of the acquisition phase). Its transition
to 0 indicates then that the board is now ready to record a signal.
3.3 Calibrations
In order to attain the optimal metrological performance, the V1729 board requires
calibrations. These remain valid for several weeks, even several months.
3.3.1 Calibration of the interpolator
The temporal interpolator (vernier) requires a calibration. This calibration, based on a
statistical measure, will require the acquisition of several thousand events and can last
from one second to a couple of minutes depending on the type of bus and on the
software used. It can be done with the inputs connected to any source, but the trigger
must be asynchronous in relation to the clock. The result of this calibration will be a
“square” histogram, of which the sides correspond to two successive rising edges of Fp.
The corresponding value on the left side (MINVER) will be the « zero » of the vernier,
and the one on the right side (MAXVER) will correspond to a vernier of 1/Fp (in other
words 10 or 20ns). The intermediate values will next be deduced at the time of the
acquisitions by a simple proportional calculation.
The diagram in Fig 3.1, which follows from that in Fig 2.5, shows the sequencing of such
a calibration. It is optimized so as to be the fastest possible. In particular :
The PRETRIG and POSTTRIG are fixed at their minimal value.
NB_OF_COL_TO_READ has to be set to 1.
Only the vernier values are read in the RAM. In other words, if NCH channels are read,
only the 2*NCH first data are read and only the NCH+1 to 2*NCH words are conserved
(see 4.7).
After a certain number of acquisitions (at least 10000), the boundaries of the vernier
MINVER and MAXVER can be calculated.
At first approximation, it is possible to simply use the minimal and maximal values of the
vernier for MAXVER and MINVER. This method is sufficient to obtain temporal
resolutions in the region of 70ps RMS.
To have greater precision, one must in order to find the two sides fix a threshold
corresponding to half the mean number of ADC counts in the « square » distribution.
To obtain even more precision, it is possible to use more complex methods.
A second, much faster method of calibration is available. For this :
Charge NB_OF_COL_TO_READ at 0.
Position the trigger in auto mode.
Authorize the internal random trigger.
Launch a Start_ACQUISITION.

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Fig. 3.1: diagram of the calibration of the verniers
The codes which implement the register setting is the following:
void TCAENADC::Vernier()
{
char s[30];
SetNCols(0);
// Setto PRETRIG
SetPreTrig(1);
// Setto POSTTRIG
SetPostTrig(1);
//??
SetTriggerType(0x08);
int i;
Set PRETRIG=POSTRIG=1
Send START
ACQUISITION
Trigger
auto ?
Send SOFT TRIGGER
yes
no
Read vernier data only
next acquisition
Send RESET BOARD
Board parameters initialization
Calculate MINVER &
MAXVER for each
channel
Wait for request

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StartAcq();
Wait();
GetVernier(vernier);
//fwrite(vernier,sizeof(vernier),1,Fvernier);
for (i=0;i<V1729_VERNIER_DEPH;i++){
sprintf(s,"%d\n",vernier[i]);
fwrite(s,1,strlen(s),Fvernier);}
printf("Vernier results saved\n");
}
void TCAENADC::GetVernier(unsigned short *vernier)
{
printf("TCAENADC::GetVernier()\n");
unsigned short buffer[V1729_VERNIER_DEPH];
int readed;
vme_adr = CAENBASEADDRESS + V1729_RAM_DATA_VME;
CAENVME_SetFIFOMode(Crate,1);
if (CAENVME_BLTReadCycle(Crate, vme_adr , (unsigned char*) buffer,
V1729_VERNIER_DEPH*2,cvA32_U_BLT,cvD32 , &readed )!= cvSuccess)
printf("TCAENADC::GetVernier() - Errore di Accesso\n");
CAENVME_SetFIFOMode(Crate,0);
for (int j = 0; j < V1729_VERNIER_DEPH; j++) vernier[j] = buffer[j] & 0xFFFF;
}
The RAM (buffer[i]) is then filled with 65536 vernier values corresponding to 16384
random triggers. For each trigger one finds only 4 values, arranged in the following
order :
Channel 3 vernier, channel 2 vernier, channel 1 vernier, channel 0 vernier.
It is then necessary to rearrange the buffer in order to obtain 4 arrays (one per channel)
of 16384 samples each.
With such settings we send on each channel a slope signal with 1/Fp duration in such a
way that, if we make an histogram of the channel data, we obtain a “square” signal,
whose edeges correspond (in time) to the Fp ramp-up fronts. The leftmost value
correspond to MINVER, the rightmost to MAXVER.
The result is similiar to a differential non linearity measure and is used in the calibration
in order to weigh the Venier single datum obatined during acquisition; this allows to
measure on which percentage of the clock period the time correction must be performed.
At the end of this calibration, an interruption is generated in order to permit the user to
launch a reading. This reading can be realized in block mode, which permits realization
of the calibration of the vernier in less than one second.
One must note that for this particular method of calibration, the distributions obtained are
not necessarily uniform. Nevertheless, the MAXVER and MINVER boundaries are
extremely well-defined and therefore perfectly exploitable for corrections.
Our experience showed us that this calibration remains valid several weeks, even
several months.

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3.3.2 Calibration of the pedestals
For this, a calibration of the baselines is necessary. This operation will be necessary
following all changes either in the frequency of sampling, or in the bandwidth of the write
amplifier (BWL), or in the read modes (FAST READ MODES). It will consist in realizing a
mean measurement over a few tens of raw acquisitions of the baselines for all of the
cells (disconnected or grounded inputs). The trigger must then be either automatic, or
external.
The acquisition procedure is the same as for a standard acquisition, but the reading of
TRIG_REC can nevertheless be skipped. Of course not the least temporal correction is
made on the data. At each acquisition, the table of the means will be computed and
finally recorded for an eventual subtraction by software from the unaligned raw data. This
calibration operation lasts less than one second.
In cases where the input is connected to unlikely physical signals, it is also possible to
realize this calibration without disconnecting the input. However, it will then probably be
necessary to increase the number of acquisitions in order to diminish the effect of the
induced additional noise.
Our experience shows us that this calibration remains valid several weeks.
3.3.3 Temporal calibration between different channels
See 3.1