Cirrus Logic Crystal LAN CS8900A Operational manual

Copyright  Cirrus Logic, Inc. 1999
(All Rights Reserved)
CS8900A
Product Data Sheet
&U\VWDO/$1 ™ ISA Ethernet
Controller
FEATURES
■Single-Chip IEEE 802.3 Ethernet Controller with
Direct ISA-Bus Interface
■
Maximum Current Consumption = 55 mA (5V Supply )
■3 V Operation
■Industrial Temperature Range
■ Comprehensive Suite of Software Drivers Available
■Efficient PacketPage™ Architecture Operates in
I/O and Memory Space, and as DMA Slave
■Full Duplex Operation
■On-Chip RAM Buffers Transmit andReceive Frames
■10BASE-T Port with Analog Filters, Provides:
— Automatic Polarity Detection and Correction
■AUI Port for 10BASE2, 10BASE5 and 10BASE-F
■Programmable Transmit Features:
— Automatic Re-transmission on Collision
— Automatic Padding and CRC Generation
■Programmable Receive Features:
— Stream Transfer™ for Reduced CPU Overhead
— Auto-Switch Between DMA and On-Chip Memory
— Early Interrupts for Frame Pre-Processing
— Automatic Rejection of Erroneous Packets
■EEPROM Support for Jumperless Configuration
■Boot PROM Support for Diskless Systems
■Boundary Scan and Loopback Test
■LED Drivers for Link Status and LAN Activity
■Standby and Suspend Sleep Modes
DESCRIPTION
The CS8900A is a low-cost Ethernet LAN Controller op-
timized for Industry Standard Architecture (ISA)
Personal Computers. Its highly-integrated design elimi-
nates the need for costly external components required
by other Ethernet controllers. The CS8900A includes
on-chip RAM, 10BASE-T transmit and receive filters,
and a direct ISA-Bus interface with 24 mA Drivers.
In addition to high integration, the CS8900A offers a
broad range of performance features and configuration-
options. Its unique PacketPage architecture
automatically adapts to changing network traffic pat-
terns and available system resources. The result is
increased system efficiency.
The CS8900A is available in a 100-pin TQFP package-
ideally suited for small form-factor, cost-sensitive
Ethernet applications. With the CS8900A, system engi-
neers can design a complete Ethernet circuit that
occupies less than 1.5 square inches (10 sq. cm) of
board space.
ORDERING INFORMATION
CS8900A-CQ 0° to 70° C 5V TQFP-100
CS8900A-IQ -40° to 85° C 5V TQFP-100
CS8900A-CQ3 0° to 70° C 3.3V TQFP-100
CS8900A-IQ3 -40° to 85° C 3.3V TQFP-100
CRD8900A-1 Evaluation Kit
EEPROM
RJ-45 10BASE-T
Attachment
Unit
Interface
(AUI)
20 MHz
XTAL
RAM
ISA
Bus
Logic
Memory
Manager
802.3
MAC
Engine
EEPROM
Control
Encoder/
Decoder
&
PLL
10BASE-T
RX Filters &
Receiver
10BASE-T
TX Filters &
Transmitter
AUI
Transmitter
AUI
Collision
AUI
Receiver
Clock
Power
Manager
Boundary
Scan
Test Logic
LED
Control
CS8900A ISA Ethernet Controller
I
S
A
DS271PP3 MAR ‘99
CIRRUS LOGIC PRODUCT DATA SHEET

2DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
TABLE OF CONTENTS
1.0 INTRODUCTION .........................................................................................................................................8
1.1 General Description...............................................................................................................................8
1.1.1 Direct ISA-Bus Interface ..............................................................................................................8
1.1.2 Integrated Memory.......................................................................................................................8
1.1.3 802.3 Ethernet MAC Engine........................................................................................................8
1.1.4 EEPROM Interface ......................................................................................................................8
1.1.5 Complete Analog Front End ........................................................................................................8
1.2 System Applications..............................................................................................................................8
1.2.1 Motherboard LANs.......................................................................................................................8
1.2.2 Ethernet Adapter Cards...............................................................................................................9
1.3 Key Features and Benefits..................................................................................................................10
1.3.1 Very Low Cost ...........................................................................................................................10
1.3.2 High Performance......................................................................................................................10
1.3.3 Low Power and Low Noise ........................................................................................................10
1.3.4 Complete Support......................................................................................................................10
2.0 PIN DESCRIPTION ................................................................................................................................12
3.0 FUNCTIONAL DESCRIPTION..................................................................................................................17
3.1 Overview .............................................................................................................................................17
3.1.1 Configuration .............................................................................................................................17
3.1.2 Packet Transmission..................................................................................................................17
3.1.3 Packet Reception.......................................................................................................................17
3.2 ISA Bus Interface ................................................................................................................................18
3.2.1 Memory Mode Operation...........................................................................................................18
3.2.2 I/O Mode Operation ...................................................................................................................18
3.2.3 Interrupt Request Signals ..........................................................................................................18
3.2.4 DMA Signals..............................................................................................................................18
3.3 Reset and Initialization........................................................................................................................19
3.3.1 Reset .........................................................................................................................................19
3.3.1.1 External Reset, or ISA Reset ...........................................................................................19
3.3.1.2 Power-Up Reset...............................................................................................................19
3.3.1.3 Power-Down Reset ..........................................................................................................19
3.3.1.4 EEPROM Reset ...............................................................................................................19
3.3.1.5 Software Initiated Reset...................................................................................................19
3.3.1.6 Hardware (HW) Standby or Suspend...............................................................................19
3.3.1.7 Sof tware (SW) Suspend..................................................................................................19
3.3.2 Allowing Time for Reset Operation............................................................................................19
3.3.3 Bus Reset Considerations .........................................................................................................19
3.3.4 Initialization................................................................................................................................20
3.4 Configurations with EEPROM.............................................................................................................21
3.4.1 EEPROM Interface ....................................................................................................................21
3.4.2 EEPROM Memory Organization................................................................................................21
3.4.3 Reset Configuration Block .........................................................................................................21
3.4.3.1 Reset Configuration Block Structure ................................................................................21
3.4.3.2 Reset Configuration Block Header...................................................................................21
3.4.3.3 Determining the EEPROM Type ......................................................................................21
3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ......................................21
3.4.3.5 Determining Number of Bytes in the Reset Configuration Block......................................22
3.4.4 Groups of Configuration Data....................................................................................................22
3.4.4.1 Group Header...................................................................................................................23
3.4.5 Reset Configuration Block Checksum .......................................................................................23
3.4.6 EEPROM Example ....................................................................................................................23
3.4.7 EEPROM Read-out ...................................................................................................................23

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CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.4.7.1 Determining EEPROM Size ............................................................................................. 23
3.4.7.2 Loading Configuration Data .............................................................................................24
3.4.8 EEPROM Read-out Completion................................................................................................ 24
3.5 Programming the EEPROM................................................................................................................ 24
3.5.1 EEPROM Commands................................................................................................................ 24
3.5.2 EEPROM Command Execution.................................................................................................24
3.5.3 Enabling Access to the EEPROM ............................................................................................. 25
3.5.4 Writing and Erasing the EEPROM............................................................................................. 25
3.6 Boot PROM Operation........................................................................................................................ 25
3.6.1 Accessing the Boot PROM........................................................................................................ 25
3.6.2 Configuring the CS8900A for Boot PROM Operation................................................................ 25
3.7 Low-Power Modes .............................................................................................................................. 26
3.7.1 Hardware Standby..................................................................................................................... 26
3.7.2 Hardware Suspend.................................................................................................................... 26
3.7.3 Software Suspend ..................................................................................................................... 27
3.8 LED Outputs........................................................................................................................................ 28
3.8.0.1 LANLED........................................................................................................................... 28
3.8.0.2 LINKLED or HC0.............................................................................................................. 28
3.8.0.3 BSTATUS or HC1 ............................................................................................................ 28
3.8.1 LED Connection ........................................................................................................................ 28
3.9 Media Access Control ......................................................................................................................... 28
3.9.1 Overview.................................................................................................................................... 28
3.9.2 Frame Encapsulation and Decapsulation.................................................................................. 29
3.9.2.1 Transmission.................................................................................................................... 29
3.9.2.2 Reception......................................................................................................................... 29
3.9.2.3 Enforcing Minimum Frame Size....................................................................................... 29
3.9.3 Transmit Error Detection and Handling ..................................................................................... 30
3.9.3.1 Loss of Carrier.................................................................................................................. 30
3.9.3.2 SQE Error......................................................................................................................... 30
3.9.3.3 Out-of-Window (Late) Collision ........................................................................................ 30
3.9.3.4 Jabber Error ..................................................................................................................... 30
3.9.3.5 Transmit Collision............................................................................................................. 30
3.9.3.6 Transmit Underrun........................................................................................................... 30
3.9.4 Receive Error Detection and Handling ...................................................................................... 31
3.9.4.1 CRC Error ........................................................................................................................ 31
3.9.4.2 Runt Frame...................................................................................................................... 31
3.9.4.3 Extra Data........................................................................................................................ 31
3.9.4.4 Dribble Bits and Alignment Error...................................................................................... 31
3.9.5 Media Access Management ...................................................................................................... 31
3.9.5.1 Collision Avoidance.......................................................................................................... 31
3.9.5.2 Two-Part Deferral............................................................................................................. 31
3.9.5.3 Simple Deferral ................................................................................................................ 32
3.9.5.4 Collision Resolution.......................................................................................................... 32
3.9.5.5 Normal Collisions............................................................................................................. 32
3.9.5.6 Late Collisions.................................................................................................................. 33
3.9.5.7 Backoff ............................................................................................................................. 33
3.9.5.8 Standard Backoff.............................................................................................................. 33
3.9.5.9 Modified Backoff............................................................................................................... 33
3.9.5.10 SQE Test........................................................................................................................ 33
3.10 Encoder/Decoder (ENDEC).............................................................................................................. 34
3.10.1 Encoder ................................................................................................................................... 34
3.10.2 Carrier Detection ..................................................................................................................... 34
3.10.3 Clock and Data Recovery........................................................................................................ 34

4DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.10.4 Interface Selection...................................................................................................................35
3.10.4.1 10BASE-T Only..............................................................................................................35
3.10.4.2 AUI Only.........................................................................................................................35
3.10.4.3 Auto-Select.....................................................................................................................35
3.11 10BASE-T Transceiver......................................................................................................................35
3.11.1 10BASE-T Filters.....................................................................................................................35
3.11.2 Transmitter...............................................................................................................................36
3.11.3 Receiver...................................................................................................................................36
3.11.3.1 Squelch Circuit...............................................................................................................36
3.11.3.2 Extended Range.............................................................................................................36
3.11.4 Link Pulse Detection................................................................................................................36
3.11.5 Receive Polarity Detection and Correction..............................................................................37
3.11.6 Collision Detection...................................................................................................................37
3.12 Attachment Unit Interface (AUI) ........................................................................................................37
3.12.1 AUI Transmitter........................................................................................................................37
3.12.2 AUI Receiver............................................................................................................................38
3.12.3 Collision Detection...................................................................................................................38
3.13 External Clock Oscillator...................................................................................................................38
4.0 PACKETPAGE ARCHITECTURE ............................................................................................................39
4.1 PacketPage Overview.........................................................................................................................39
4.1.1 Integrated Memory.....................................................................................................................39
4.1.2 Bus Interface Registers .............................................................................................................39
4.1.3 Status and Control Registers.....................................................................................................39
4.1.4 Initiate Transmit Registers.........................................................................................................39
4.1.5 Address Filter Registers.............................................................................................................39
4.1.6 Receive and Transmit Frame Locations....................................................................................39
4.2 PacketPage Memory Map...................................................................................................................40
4.3 Bus Interface Registers.......................................................................................................................42
4.3.1 Product Identification Code .......................................................................................................42
4.3.2 I/O Base Address ......................................................................................................................42
4.3.3 Interrupt Number .......................................................................................................................43
4.3.4 DMA Channel Number ..............................................................................................................43
4.3.5 DMA Start of Frame ..................................................................................................................44
4.3.6 DMA Frame Count ...................................................................................................................44
4.3.7 RxDMA Byte Count ..................................................................................................................44
4.3.8 Memory Base Address ..............................................................................................................44
4.3.9 Boot PROM Base Address .......................................................................................................45
4.3.10 Boot PROM Address Mask .....................................................................................................45
4.3.11 EEPROM Command ...............................................................................................................46
4.3.12 EEPROM Data ........................................................................................................................46
4.3.13 Receive Frame Byte Counter ..................................................................................................46
4.4 Status and Control Registers ..............................................................................................................47
4.4.1 Configuration and Control Registers..........................................................................................47
4.4.2 Status and Event Registers .......................................................................................................47
4.4.3 Status and Control Bit Definitions..............................................................................................47
4.4.3.1 Act-Once Bits ...................................................................................................................48
4.4.3.2 Temporal Bits ...................................................................................................................48
4.4.3.3 Interrupt Enable Bits and Events......................................................................................48
4.4.3.4 Accept Bits .......................................................................................................................48
4.4.4 Status and Control Register Summary ......................................................................................49
4.4.5 Register 0: Interrupt Status Queue ..........................................................................................52
4.4.6 Register 3: Receiver Configuration ..........................................................................................53
4.4.7 Register 4: Receiver Event ......................................................................................................54

DS271PP3 5
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
4.4.8 Register 5: Receiver Control ................................................................................................... 55
4.4.9 Register 7: Transmit Configuration .......................................................................................... 56
4.4.10 Register 8: Transmitter Event ................................................................................................ 57
4.4.11 Register 9: Transmit Command Status ................................................................................. 58
4.4.12 Register B: Buffer Configuration ............................................................................................ 59
4.4.13 Register C: Buffer Event ........................................................................................................ 60
4.4.14 Register 10: Receiver Miss Counter ...................................................................................... 61
4.4.15 Register 10: Transmit Collision Counter ................................................................................ 62
4.4.16 Register 13: Line Control ....................................................................................................... 63
4.4.17 Register 14: Line Status ........................................................................................................ 64
4.4.18 Register 15: Self Control ....................................................................................................... 65
4.4.19 Register 16: Self Status ......................................................................................................... 66
4.4.20 Register 17: Bus Control ....................................................................................................... 67
4.4.21 Register 18: Bus Status ......................................................................................................... 68
4.4.22 Register 19: Test Control ....................................................................................................... 69
4.4.23 Register 1C: AUI Time Domain Reflectometer ...................................................................... 70
4.5 Initiate Transmit Registers .................................................................................................................. 71
4.5.1 Transmit Command Request - TxCMD .................................................................................... 71
4.5.2 Transmit Length ........................................................................................................................ 71
4.6 Address Filter Registers...................................................................................................................... 72
4.6.1 Logical Address Filter (hash table) ........................................................................................... 72
4.6.2 Individual Address (IEEE address) ........................................................................................... 72
4.7 Receive and Transmit Frame Locations ............................................................................................. 73
4.7.1 Receive PacketPage Locations................................................................................................. 73
4.7.2 Transmit Locations .................................................................................................................... 73
4.8 Eight and Sixteen Bit Transfers........................................................................................................... 73
4.8.1 Transferring Odd-Byte-Aligned Data......................................................................................... 74
4.8.2 Random Access to CS8900A Memory...................................................................................... 74
4.9 Memory Mode Operation .................................................................................................................... 74
4.9.1 Accesses in Memory Mode ....................................................................................................... 74
4.9.2 Configuring the CS8900A for Memory Mode............................................................................. 74
4.9.3 Basic Memory Mode Transmit................................................................................................... 75
4.9.4 Basic Memory Mode Receive.................................................................................................... 75
4.9.5 Polling the CS8900A in Memory Mode...................................................................................... 76
4.10 I/O Space Operation ......................................................................................................................... 76
4.10.1 Receive/Transmit Data Ports 0 and 1...................................................................................... 76
4.10.2 TxCMD Port............................................................................................................................. 76
4.10.3 TxLength Port.......................................................................................................................... 76
4.10.4 Interrupt Status Queue Port..................................................................................................... 76
4.10.5 PacketPage Pointer Port......................................................................................................... 76
4.10.6 PacketPage Data Ports 0 and 1 .............................................................................................. 77
4.10.7 I/O Mode Operation................................................................................................................. 77
4.10.8 Basic I/O Mode Transmit......................................................................................................... 77
4.10.9 Basic I/O Mode Receive.......................................................................................................... 77
4.10.10 Accessing Internal Registers................................................................................................. 78
4.10.11 Polling the CS8900A in I/O Mode.......................................................................................... 78
5.0 OPERATION ............................................................................................................................................. 79
5.1 Managing Interrupts and Servicing the Interrupt Status Queue.......................................................... 79
5.2 Basic Receive Operation..................................................................................................................... 79
5.2.0.1 Overview.......................................................................................................................... 79
5.2.1 Terminology: Packet, Frame, and Transfer............................................................................... 81
5.2.1.1 Packet .............................................................................................................................. 81
5.2.1.2 Frame............................................................................................................................... 81

6DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
5.2.1.3 Transfer............................................................................................................................81
5.2.2 Receive Configuration ...............................................................................................................81
5.2.2.1 Configuring the Physical Interface....................................................................................81
5.2.2.2 Choosing which Frame Types to Accept..........................................................................81
5.2.2.3 Selecting which Events Cause Interrupts.........................................................................82
5.2.2.4 Choosing How to Transfer Frames ..................................................................................82
5.2.3 Receive Frame Pre-Processing.................................................................................................83
5.2.3.1 Destination Address Filtering ...........................................................................................83
5.2.3.2 Early Interrupt Generation................................................................................................84
5.2.3.3 Acceptance Filtering.........................................................................................................84
5.2.3.4 Normal Interrupt Generation.............................................................................................84
5.2.4 Held vs. DMAed Receive Frames..............................................................................................84
5.2.5 Buffering Held Receive Frames.................................................................................................84
5.2.6 Transferring Held Receive Frames............................................................................................86
5.2.7 Receive Frame Visibility.............................................................................................................86
5.2.8 Example of Memory Mode Receive Operation..........................................................................86
5.2.9 Receive Frame Byte Counter.....................................................................................................87
5.3 Receive Frame Address Filtering........................................................................................................87
5.3.0.1 Individual Address Frames...............................................................................................88
5.3.0.2 Multicast Frames..............................................................................................................88
5.3.0.3 Broadcast Frames............................................................................................................88
5.3.1 Configuring the Destination Address Filter ................................................................................88
5.3.2 Hash Filter .................................................................................................................................89
5.3.2.1 Hash Filter Operation .......................................................................................................89
5.3.3 Broadcast Frame Hashing Exception ........................................................................................89
5.4 Receive DMA ......................................................................................................................................90
5.4.1 Overview....................................................................................................................................90
5.4.2 Configuring the CS8900A for DMA Operation...........................................................................90
5.4.3 DMA Receive Buffer Size ..........................................................................................................90
5.4.4 Receive-DMA-Only Operation ...................................................................................................91
5.4.5 Committing Buffer Space to a DMAed Frame............................................................................92
5.4.6 DMA Buffer Organization...........................................................................................................92
5.4.7 RxDMAFrame Bit.......................................................................................................................92
5.4.8 Receive DMA Example Without Wrap-Around ..........................................................................92
5.4.9 Receive DMA Operation for RxDMA-Only Mode.......................................................................92
5.5 Auto-Switch DMA ................................................................................................................................93
5.5.1 Overview....................................................................................................................................93
5.5.2 Configuring the CS8900A for Auto-Switch DMA........................................................................94
5.5.3 Auto-Switch DMA Operation......................................................................................................94
5.5.4 DMA Channel Speed vs. Missed Frames..................................................................................95
5.5.5 Exit From DMA...........................................................................................................................95
5.5.6 Auto-Switch DMA Example........................................................................................................96
5.6 StreamTransfer ...................................................................................................................................96
5.6.1 Overview....................................................................................................................................96
5.6.2 Configuring the CS8900A for StreamTransfer...........................................................................96
5.6.3 StreamTransfer Operation.........................................................................................................96
5.6.4 Keeping StreamTransfer Mode Active.......................................................................................96
5.6.5 Example of StreamTransfer.......................................................................................................98
5.6.6 Receive DMA Summary.............................................................................................................98
5.7 Transmit Operation..............................................................................................................................99
5.7.1 Overview....................................................................................................................................99
5.7.2 Transmit Configuration...............................................................................................................99
5.7.2.1 Configuring the Physical Interface....................................................................................99

DS271PP3 7
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
5.7.2.2 Selecting which Events Cause Interrupts......................................................................... 99
5.7.3 Changing the Configuration....................................................................................................... 99
5.7.4 Enabling CRC Generation and Padding.................................................................................. 100
5.7.5 Individual Packet Transmission............................................................................................... 100
5.7.6 Transmit in Poll Mode.............................................................................................................. 101
5.7.7 Transmit in Interrupt Mode ...................................................................................................... 101
5.7.8 Completing Transmission........................................................................................................ 103
5.7.9 Rdy4TxNOW vs. Rdy4Tx ........................................................................................................ 103
5.7.10 Committing Buffer Space to a Transmit Frame ..................................................................... 103
5.7.11 Transmit Frame Length ......................................................................................................... 105
5.8 Full duplex Considerations................................................................................................................ 105
5.9 Auto-Negotiation Considerations ...................................................................................................... 105
6.0 TEST MODES ......................................................................................................................................... 106
6.0.1 Loopback & Collision Diagnostic Tests ................................................................................... 106
6.0.2 Internal Tests........................................................................................................................... 106
6.0.3 External Tests.......................................................................................................................... 106
6.0.4 Loopback Tests ....................................................................................................................... 106
6.0.5 10BASE-T Loopback and Collision Tests................................................................................ 106
6.0.6 AUI Loopback and Collision Tests........................................................................................... 106
6.1 Boundary Scan.................................................................................................................................. 107
6.1.1 Output Cycle............................................................................................................................ 107
6.1.2 Input Cycle............................................................................................................................... 107
6.1.3 Continuity Cycle....................................................................................................................... 108
7.0 CHARACTERISTICS/SPECIFICATIONS............................................................................................... 111
7.1 ABSOLUTE MAXIMUM RATINGS.................................................................................................... 111
7.2 RECOMMENDED OPERATING CONDITIONS ............................................................................... 111
7.3 DC CHARACTERISTICS.................................................................................................................. 111
7.4 SWITCHING CHARACTERISTICS................................................................................................... 113
7.5 10BASE-T WIRING........................................................................................................................... 120
7.6 AUI WIRING ................................................................................................................................... 121
7.7 QUARTZ CRYSTAL REQUIREMENTS............................................................................................ 121
8.0 PHYSICAL DIMENSIONS....................................................................................................................... 122
9.0 GLOSSARY OF TERMS......................................................................................................................... 123
9.1 Acronyms.......................................................................................................................................... 123
9.2 Definitions ......................................................................................................................................... 124
9.3 Acronyms Specific to the CS8900A.................................................................................................. 125
9.4 Terms Specific to the CS8900A........................................................................................................ 125
9.5 Suffixes Specific to the CS8900A. .................................................................................................... 126

8DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
1.0 INTRODUCTION
1.1 General Description
The CS8900A is a true single-chip, full-duplex,
Ethernet solution, incorporating all of the analog
and digital circuitry needed for a complete Ethernet
circuit. Major functional blocks include: a direct
ISA-bus interface; an 802.3 MAC engine; integrat-
ed buffer memory; a serial EEPROM interface; and
a complete analog front end with both 10BASE-T
and AUI.
1.1.1 Direct ISA-Bus Interface
Included in the CS8900A is a direct ISA-bus inter-
face with full 24 mA drive capability. Its configu-
ration options include a choice of four interrupts
and three DMA channels (one of each selected dur-
ing initialization). In Memory Mode, it supports
Standard or Ready Bus cycles without introducing
additional wait states.
1.1.2 Integrated Memory
The CS8900A incorporates a 4-Kbyte page of on-
chip memory, eliminating the cost and board area
associated with external memory chips. Unlike
most other Ethernet controllers, the CS8900A buff-
ers entire transmit and receive frames on chip,
eliminating the need for complex, inefficient mem-
ory management schemes. In addition, the
CS8900A operates in either Memory space, I/O
space, or with external DMA controllers, providing
maximum design flexibility.
1.1.3 802.3 Ethernet MAC Engine
The CS8900A’s Ethernet Media Access Control
(MAC) engine is fully compliant with the IEEE
802.3 Ethernet standard (ISO/IEC 8802-3, 1993),
and supports full-duplex operation. It handles all
aspects of Ethernet frame transmission and recep-
tion, including: collision detection, preamble gen-
eration and detection, and CRC generation and test.
Programmable MAC features include automatic re-
transmission on collision, and automatic padding
of transmitted frames.
1.1.4 EEPROM Interface
The CS8900A provides a simple and efficient seri-
al EEPROM interface that allows configuration in-
formation to be stored in an optional EEPROM,
and then loaded automatically at power-up. This
eliminates the need for costly and cumbersome
switches and jumpers.
1.1.5 Complete Analog Front End
The CS8900A’s analog front end incorporates a
Manchester encoder/decoder, clock recovery cir-
cuit, 10BASE-T transceiver, and complete Attach-
ment Unit Interface (AUI). It provides manual and
automatic selection of either 10BASE-T or AUI,
and offers three on-chip LED drivers for link sta-
tus, bus status, and Ethernet line activity.
The 10BASE-T transceiver includes drivers, re-
ceivers, and analog filters, allowing direct connec-
tion to low-cost isolation transformers. It supports
100, 120, and 150 Ω shielded and unshielded ca-
bles, extended cable lengths, and automatic receive
polarity reversal detection and correction.
The AUI port provides a direct interface to
10BASE-2, 10BASE-5 and 10BASE-FL networks,
and is capable of driving a full 50-meter AUI cable.
1.2 System Applications
The CS8900A is designed to work well in either
motherboard or adapter applications.
1.2.1 Motherboard LANs
The CS8900A requires the minimum number of
external components needed for a full Ethernet
node. Its small-footprint package and high level of
integration allow System Engineers to design a
complete Ethernet circuit that occupies as little as
1.5 square inches of PCB area (Figure 1). In addi-
tion, the CS8900A’s power-saving features and
CMOS design make it a perfect fit for power-sensi-

DS271PP3 9
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
tive portable and desktop PCs. Motherboard design
options include:
• An EEPROM can be used to store node-specif-
ic information, such as the Ethernet Individual
Address and node configuration.
• The 20 MHz crystal oscillator may be replaced
by a 20 MHz clock signal.
1.2.2 Ethernet Adapter Cards
The CS8900A’s highly efficient PacketPage archi-
tecture, with StreamTransfer™ and Auto-Switch
DMA options, make it an excellent choice for high-
performance, low-cost ISA adapter cards
(Figure 2). The CS8900A’s wide range of configu-
ration options and performance features allow en-
gineers to design Ethernet solutions that meet their
particular system requirements. Adapter card de-
sign options include:
• A Boot PROM can be added to support diskless
applications.
• The 10BASE-T transmitter and receiver im-
pedance can be adjusted to support 100, 120, or
150 Ohm twisted pair cables.
• An external Latchable-Address-bus decode cir-
cuit can be added to operate the CS8900A in
Upper-Memory space.
• On-chip LED ports can be used for either op-
tional LEDs, or as programmable outputs.
RJ-45 10BASE-T
CS8900A
I
S
A
EEPROM 20 MHz
XTAL
(2.0 sq. in.)
Figure 1. Complete Ethernet Motherboard Solution
CS8900A
EEPROM
Boot PROM
’245
20 MHz
XTAL
RJ-45
LED
Attachment
Unit
Interface
(AUI)
Figure 2. Full-Featured ISA Adapter Solution

10 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
1.3 Key Features and Benefits
1.3.1 Very Low Cost
The CS8900A is designed to provide the lowest-
cost Ethernet solution available for embedded ap-
plications, portable motherboards, non-ISA bus
systems and adapter cards. Cost-saving features in-
clude:
• Integrated RAM eliminates the need for expen-
sive external memory chips.
• On-chip 10BASE-T filters allow designers to
use simple isolation transformers instead of
more costly filter/transformer packages.
• The serial EEPROM port, used for configura-
tion and initialization, eliminates the need for
expensive switches and jumpers.
• The CS8900A is designed to be used on a 2-
layer circuit board instead of a more expensive
multilayer board.
• The 8900A-based solution offers the smallest
footprint available, saving valuable printed cir-
cuit board area.
• A set of certified software drivers is available at
no charge, eliminating the need for costly soft-
ware development.
1.3.2 High Performance
The CS8900A is a full 16-bit Ethernet controller
designed to provide optimal system performance
by minimizing time on the ISA bus and CPU over-
head per frame. It offers equal or superior perfor-
mance for less money when compared to other
Ethernet controllers. The CS8900A’s PacketPage
architecture allows software to select whichever
access method is best suited to each particular
CPU/ISA-bus configuration. When compared to
older I/O-space designs, PacketPage is faster, sim-
pler and more efficient.
To boost performance further, the CS8900A in-
cludes several key features that increase throughput
and lower CPU overhead, including:
• StreamTransfer cuts up to 87% of interrupts to
the host CPU during large block transfers.
• Auto-Switch DMA allows the CS8900A to
maximize throughput while minimizing missed
frames.
• Early interrupts allow the host to preprocess in-
coming frames.
• On-chip buffering of full frames cuts the
amount of host bandwidth needed to manage
Ethernet traffic.
1.3.3 Low Power and Low Noise
For low power needs, the CS8900A offers three
power-down options: Hardware Standby, Hard-
ware Suspend, and Software Suspend. In Standby
mode, the chip is powered down with the exception
of the 10BASE-T receiver, which is enabled to lis-
ten for link activity. In either Hardware or Software
Suspend mode, the receiver is disabled and power
consumption drops to the micro-ampere range.
In addition, the CS8900A has been designed for
very low noise emission, thus shortening the time
required for EMI testing and qualification.
1.3.4 Complete Support
The CS8900A comes with a suite of software driv-
ers for immediate use with most industry standard
network operating systems. In addition, complete
evaluation kits and manufacturing packages are
available, significantly reducing the cost and time
required to produce new Ethernet products.

DS271PP3 11
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
EECS
EEDATAOUT
EESK
SA[0:19]
MEMW
MEMR
IOW
IOR
REFRESH
SBHE
SD[0:15]
INTRQ0
INTRQ1
RXD-
RXD+
TXD-
TXD+
DO-
DO+
CI-
CI+
DI-
DI+
LANLED
LINKLED
CSOUT
EEDATAIN
AEN
RESET
INTRQ2
INTRQ3
DMARQ0
DMACK0
DMARQ1
DMACK1
DMARQ2
DMACK2
MEMCS16
IOCHRDY
1:
68 pF
1
3
6
8
24.3 Ω, 1%
24.3
Ω, 1%
92
91
88
87
100
Ω, 1%
RJ45
16
14
11
9
10
6
3
2
1
1:1
1
4
5
8
84
82
81
79
16
13
12
9
10
10
9
2
5
83
80
2
7
15 3
12
1:1
1:1
0.1
µ
F
.1 µ F
680
Ω
680
Ω
CE
OE
OE
DIR
20
22
19
1
74LS245
XTAL1 XTAL2 SLEEP TEST RES
CS
DO
DI
CLK
1
3
2
43
5
4
6
93C46
28
62
61
29
7
IRQ10
IRQ11
IRQ12
IRQ5
DRQ5
DACK5
DRQ6
DACK6
DRQ7
DACK7
16
20
SA[0:19]
LA[20:23]
BALE
4
97 98 93
4.99 k
Ω
, 1%
12 V
4, 6
20 MHz
0.1
µ
F
39.2 Ω , 1%
5 V
4.7 k
Ω
CS8900A
CHIPSEL
IOCS16
49
63
75
36
34
64
33
32
30
35
31
15
13
14
16
11
12
99
100
17
39.2
Ω
, 1%
39.2
Ω , 1% 39.2
Ω
, 1%
EEPROM
Address
Decoder
PAL
27C256
2
ELCS
ISA
BUS
10 BASE T
Isolation
Transformer
1:1
15 pin D
AUI Isolation
Transformer
BSTATUS/HCI
Boot-PROM
PD[0:7]
SA[0:14]
SD[0:7]
15
8
5 V
13
77 76
78
Figure 3. Typical Connection Diagram

12 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
2.0 PIN DESCRIPTION
36 40 41 46 47 48 49 50 26 27 28 29 30
31
33
32
34 35 37 38
39
42
43
44
45 81
82
83
84
85
86 87 88 89 90 91 92
93
94
95 96 97 98 99
100
76 77 78
79
80
2
1
3
16
5
4
6
8
7
9
10
11
12
13
14
15
17
18
20
19
21
22
23
24 53
54
55
56
57
58
59
60
61
62
63
64
51
52
65
66
68
67
69
70
71
72
73
74
75
25
EEDataOut
EESK
EECS
EEDataIn
CHIPSEL
DMACK2
DMACK1
DMACK0
DMARQ2
DMARQ1
DMARQ0
SD15
SD14
SD13
SD12
DVDD2
DVSS2
SD11
CSOUT
SD10
SD08
SA3 SA4
SA15
SA14
AVSS4
BSTATUS or HC1 TXD + TXD - AVSS1 AVDD1 RXD - RXD + AVSS2 AVDD2 TEST SLEEP XTAL1 XTAL2 RES
AVSS3
SA0
INTRQ2
INTRQ1
IOCS16
INTRQ0
MEMCS16
SBHE
SA1
SA2
INTRQ3
SA9
SA10
SA8
SA11
SA5 SA6 SA7
REFRESH
SA19
SA18
SA17
DVDD3
DVSS3
SA16
SD0
AEN
IOW
IOR
IOCHRD
Y
SD1
SD5
SD4
SD3
SD2
DVSS4
DVDD4
SD6
SD7
LINKLED or HC0
RESET
SA13
MEMW
MEMR
DVSS1
DVDD1
ELCS
AVSS0
DVSS1A
SD09
SA12
DVSS3A
AVDD3 LANLED DO- DO+ DI- DI+
CI-
CI+
CS8900A
100-pin
TQFP
(Q)
Top View

DS271PP3 13
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
ISA Bus Interface
SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60.
Lower 20 bits of the 24-bit System Address Bus used to decode accesses to CS8900A I/O and
Memory space, and attached Boot PROM. SA0-SA15 are used for I/O Read and Write
operations. SA0-SA19 are used in conjunction with external decode logic for Memory Read
and Write operations.
SD[0:15] - System Data Bus, Bi-Directional with 3-State Output PINS 65-68, 71-74, 27-24, 21-18.
Bi-directional 16-bit System Data Bus used to transfer data between the CS8900A and the host.
RESET - Reset, Input PIN 75.
Active-high asynchronous input used to reset the CS8900A. Must be stable for at least 400 ns
before the CS8900A recognizes the signal as a valid reset.
AEN - Address Enable, Input PIN 63.
When TEST is high, this active-high input indicates to the CS8900A that the system DMA
controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave
I/O space operations. When TEST is low, this pin becomes the shift clock input for the
Boundary Scan Test. AEN should be inactive when performing an IO or memory access and it
should be active during a DMA cycle.
MEMR - Memory Read, Input PIN 29.
Active-low input indicates that the host is executing a Memory Read operation.
MEMW - Memory Write, Input PIN 28.
Active-low input indicates that the host is executing a Memory Write operation.
MEMCS16 - Memory Chip Select 16-bit, Open Drain Output PIN 34.
Open-drain, active-low output generated by the CS8900A when it recognizes an address on the
ISA bus that corresponds to its assigned Memory space (CS8900A must be in Memory Mode
with the MemoryE bit (Register 17, BusCTL, Bit A) set for MEMCS16 to go active). 3-Stated
when not active.
REFRESH - Refresh, Input PIN 49.
Active-low input indicates to the CS8900A that a DRAM refresh cycle is in progress. When
REFRESH is low, MEMR, MEMW, IOR, IOW, DMACK0, DMACK1, and DMACK2 are
ignored.
IOR - I/O Read, Input PIN 61.
When IOR is low and a valid address is detected, the CS8900A outputs the contents of the
selected 16-bit I/O register onto the System Data Bus. IOR is ignored if REFRESH is low.
IOW - I/O Write, Input PIN 62.
When IOW is low and a valid address is detected, the CS8900A writes the data on the System
Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low.

14 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
IOCS16 - I/O Chip Select 16-bit, Open Drain Output PIN 33.
Open-drain, active-low output generated by the CS8900A when it recognizes an address on the
ISA bus that corresponds to its assigned I/O space. 3-Stated when not active.
IOCHRDY - I/O Channel Ready, Open Drain Output PIN 64.
When driven low, this open-drain, active-high output extends I/O Read and Memory Read
cycles to the CS8900A. This output is functional when the IOCHRDYE bit in the Bus Control
register (Register 17) is clear. This pin is always 3-Stated when the IOCHRDYE bit is set.
SBHE - System Bus High Enable, Input PIN 36.
Active-low input indicates a data transfer on the high byte of the System Data Bus (SD8-
SD15). After a hardware or a software reset, provide a HIGH to LOW and then LOW to HIGH
transition on SBHE signal before any IO or memory access is done to the CS8900A.
INTRQ[0:2] - Interrupt Request, 3-State PINS 30-32, 35.
Active-high output indicates the presence of an interrupt event. Interrupt Request goes low once
the Interrupt Status Queue (ISQ) is read as all 0’s. Only one Interrupt Request output is used
(one is selected during configuration). All non-selected Interrupt Request outputs are placed in
a high-impedance state. (Section 3.2 on page 18 and Section 5.1 on page 79.)
DMARQ[0:2] - DMA Request, 3-State PINS 11, 13, and 15.
Active-high, 3-Stateable output used by the CS8900A to request a DMA transfer. Only one
DMA Request output is used (one is selected during configuration). All non-selected DMA
Request outputs are placed in a high-impedance state.
DMACK[0:2] - DMA Acknowledge, Input PINS 12, 14, and 16.
Active-low input indicates acknowledgment by the host of the corresponding DMA Request
output.
CHIPSEL - Chip Select, Input PIN 7.
Active-low input generated by external Latchable Address bus decode logic when a valid
memory address is present on the ISA bus. If Memory Mode operation is not needed,
CHIPSEL should be tied low. The CHIPSEL is ignored for IO and DMA mode of the
CS8900A.
EEPROM and Boot PROM Interface
EESK - EEPROM Serial Clock, PIN 4.
Serial clock used to clock data into or out of the EEPROM.
EECS - EEPROM Chip Select, PIN 3.
Active-high output used to select the EEPROM.

DS271PP3 15
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
EEDataIn - EEPROM Data In, Input Internal Weak Pullup PIN 6.
Serial input used to receive data from the EEPROM. Connects to the DO pin on the EEPROM.
EEDataIn is also used to sense the presence of the EEPROM.
ELCS - External Logic Chip Select, Internal Weak Pullup PIN 2.
Bi-directional signal used to configure external Latchable Address (LA) decode logic. If
external LA decode logic is not needed, ELCS should be tied low.
EEDataOut - EEPROM Data Out,PIN 5.
Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM.
When TEST is low, this pin becomes the output for the Boundary Scan Test.
CSOUT - Chip Select for External Boot PROM, PIN 17.
Active-low output used to select an external Boot PROM when the CS8900A decodes a valid
Boot PROM memory address.
10BASE-T Interface
TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88.
Differential output pair drives 10 Mb/s Manchester-encoded data to the 10BASE-T transmit
pair.
RXD+/RXD- - 10BASE-T Receive, Differential Input Pair PINS 91 and 92.
Differential input pair receives 10 Mb/s Manchester-encoded data from the 10BASE-T receive
pair.
Attachment Unit Interface (AUI)
DO+/DO- - AUI Data Out, Differential Output Pair PINS 83 and 84.
Differential output pair drives 10 Mb/s Manchester-encoded data to the AUI transmit pair.
DI+/DI- - AUI Data In, Differential Input Pair PINS 79 and 80.
Differential input pair receives 10 Mb/s Manchester-encoded data from the AUI receive pair.
CI+/CI- - AUI Collision In, Differential Input Pair PINS 81 and 82.
Differential input pair connects to the AUI collision pair. A collision is indicated by the
presence of a 10 MHz ± 15% signal with duty cycle no worse than 60/40.
General Pins
XTAL[1:2] - Crystal, Input/Output PINS 97 and 98.
A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20 MHz
signal should be connected to XTAL1 and XTAL2 should be left open. (See Section 7.3 on
page 111 and Section 7.7 on page 121.)

16 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
SLEEP - Hardware Sleep, Input Internal Weak Pullup PIN 77.
Active-low input used to enable the two hardware sleep modes: Hardware Suspend and
Hardware Standby. (See Section 3.7 on page 26.)
LINKLED or HC0 - Link Good LED or Host Controlled Output 0, Open Drain Output PIN 99.
When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is
low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the
host may drive this pin low by setting the HCBO in the Self Control register.
BSTATUS or HC1 - Bus Status or Host Controlled Output 1, Open Drain Output PIN 78.
When the HC1E bit of the Self Control register (Register 15) is clear, this active-low output is
low when receive activity causes an ISA bus access. When the HC1E bit is set, the host may
drive this pin low by setting the HCB1 in the Self Control register.
LANLED - LAN Activity LED, Open Drain Output PIN 100.
During normal operation, this active-low output goes low for 6 ms whenever there is a receive
packet, a transmit packet, or a collision. During Hardware Standby mode, this output is driven
low when the receiver detects network activity.
TEST - Test Enable, Input Internal Weak Pullup PIN 76.
Active-low input used to put the CS8900A in Boundary Scan Test mode. For normal operation,
this pin should be high.
RES - Reference Resistor, Input PIN 93.
This input should be connected to a 4.99KΩ± 1% resistor needed for biasing of internal analog
circuits.
DVDD[1:4] - Digital Power, Power PINS 9, 22, 56, and 69.
Provides 5 V ± 5% power to the digital circuits of the CS8900A.
DVSS[1:4} and DVSS1A, DVSS3A - Digital Ground, Ground PINS 8, 10, 23, 55, 57, and 70.
Provides ground reference (0 V) to the digital circuits of the CS8900A.
AVDD[1:3] - Analog Power, Power PINS 90, 85, and 95.
Provides 5 V ± 5% power to the analog circuits of the CS8900A.
AVSS[0:4] - Analog Ground, Ground PINS 1, 89, 86, 94, 96.
Provide ground reference (0 V) to the analog circuits of the CS8900A.

DS271PP3 17
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.0 FUNCTIONAL DESCRIPTION
3.1 Overview
During normal operation, the CS8900A performs
two basic functions: Ethernet packet transmission
and reception. Before transmission or reception is
possible, the CS8900A must be configured.
3.1.1 Configuration
The CS8900A must be configured for packet trans-
mission and reception at power-up or reset. Various
parameters must be written into its internal Config-
uration and Control registers such as Memory Base
Address; Ethernet Physical Address; what frame
types to receive; and which media interface to use.
Configuration data can either be written to the
CS8900A by the host (across the ISA bus), or load-
ed automatically from an external EEPROM. Oper-
ation can begin after configuration is complete.
Section 3.3 on page 19 and Section 3.4 on page 21
describe the configuration process in detail.
Section 4.4 on page 47 provides a detailed descrip-
tion of the bits in the Configuration and Control
Registers.
3.1.2 Packet Transmission
Packet transmission occurs in two phases. In the
first phase, the host moves the Ethernet frame into
the CS8900A’s buffer memory. The first phase be-
gins with the host issuing a Transmit Command.
This informs the CS8900A that a frame is to be
transmitted and tells the chip when to start trans-
mission (i.e. after 5, 381, 1021 or all bytes have
been transferred) and how the frame should be sent
(i.e. with or without CRC, with or without pad bits,
etc.). The Host follows the Transmit Command
with the Transmit Length, indicating how much
buffer space is required. When buffer space is
available, the host writes the Ethernet frame into
the CS8900A’s internal memory, either as a Mem-
ory or I/O space operation.
In the second phase of transmission, the CS8900A
converts the frame into an Ethernet packet then
transmits it onto the network. The second phase be-
gins with the CS8900A transmitting the preamble
and Start-of-Frame delimiter as soon as the proper
number of bytes has been transferred into its trans-
mit buffer (5, 381, 1021 bytes or full frame, de-
pending on configuration). The preamble and Start-
of-Frame delimiter are followed by the Destination
Address, Source Address, Length field and LLC
data (all supplied by the host). If the frame is less
than 64 bytes, including CRC, the CS8900A adds
pad bits if configured to do so. Finally, the
CS8900A appends the proper 32-bit CRC value.
The Section 5.7 on page 99 provides a detailed de-
scription of packet transmission.
3.1.3 Packet Reception
Like packet transmission, packet reception occurs
in two phases. In the first phase, the CS8900A re-
ceives an Ethernet packet and stores it in on-chip
memory. The first phase of packet reception begins
with the receive frame passing through the analog
front end and Manchester decoder where Manches-
ter data is converted to NRZ data. Next, the pream-
ble and Start-of-Frame delimiter are stripped off
and the receive frame is sent through the address
filter. If the frame’s Destination Address matches
the criteria programmed into the address filter, the
packet is stored in the CS8900A’s internal memo-
ry. The CS8900A then checks the CRC, and de-
pending on the configuration, informs the
processor that a frame has been received.
In the second phase, the host transfers the receive
frame across the ISA bus and into host memory.
Receive frames can be transferred as Memory
space operations, I/O space operations, or as DMA
operations using host DMA. Also, the CS8900A
provides the capability to switch between Memory
or I/O operation and DMA operation by using
Auto-Switch DMA and StreamTransfer.
The Section 5.2 on page 79 through Section 5.6 on
page 96 provide a detailed description of packet re-
ception.

18 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
3.2 ISA Bus Interface
The CS8900A provides a direct interface to ISA
buses running at clock rates from 8 to 11 MHz. Its
on-chip bus drivers are capable of delivering
24 mA of drive current, allowing the CS8900A to
drive the ISA bus directly, without added external
"glue logic".
The CS8900A is optimized for 16-bit data trans-
fers, operating in either Memory space, I/O space,
or as a DMA slave.
Note that ISA-bus operation below 8 MHz should
use the CS8900A’s Receive DMA mode to mini-
mize missed frames. See Section 5.4 on page 90 for
a description of Receive DMA operation.
3.2.1 Memory Mode Operation
When configured for Memory Mode operation, the
CS8900A’s internal registers and frame buffers are
mapped into a contiguous 4-Kbyte block of host
memory, providing the host with direct access to
the CS8900A’s internal registers and frame buff-
ers. The host initiates Read operations by driving
the MEMR pin low and Write operations by driv-
ing the MEMW pin low.
For additional information about Memory Mode,
see Section 4.9 on page 74.
3.2.2 I/O Mode Operation
When configured for I/O Mode operation, the
CS8900A is accessed through eight, 16-bit I/O
ports that are mapped into sixteen contiguous I/O
locations in the host system’s I/O space. I/O Mode
is the default configuration for the CS8900A and is
always enabled.
For an I/O Read or Write operation, the AEN pin
must be low, and the 16-bit I/O address on the ISA
System Address bus (SA0 - SA15) must match the
address space of the CS8900A. For a Read, IOR
must be low, and for a Write, IOW must be low.
For additional information about I/O Mode, see
Section 4.10 on page 76.
3.2.3 Interrupt Request Signals
The CS8900A has four interrupt request output
pins that can be connected directly to any four of
the ISA bus Interrupt Request signals. Only one in-
terrupt output is used at a time. It is selected during
initialization by writing the interrupt number (0 to
3) into PacketPage Memory base + 0022h. Unused
interrupt request pins are placed in a high-imped-
ance state. The selected interrupt request pin goes
high when an enabled interrupt is triggered. The
pin goes low after the Interrupt Status Queue (ISQ)
is read as all 0’s (see Section 5.1 on page 79 for a
description of the ISQ).
Table 1 presents one possible way of connecting
the interrupt request pins to the ISA bus that utiliz-
es commonly available interrupts and facilitates
board layout.
3.2.4 DMA Signals
The CS8900A interfaces directly to the host DMA
controller to provide DMA transfers of receive
frames from CS8900A memory to host memory.
The CS8900A has three pairs of DMA pins that can
be connected directly to the three 16-bit DMA
channels of the ISA bus. Only one DMA channel is
used at a time. It is selected during initialization by
writing the number of the desired channel (0, 1 or
2) into PacketPage Memory base + 0024h. Unused
DMA pins are placed in a high-impedance state.
The selected DMA request pin goes high when the
CS8900A has received frames to transfer to the
host memory via DMA. If the DMABurst bit (reg-
ister 17, BusCTL, Bit B) is clear, the pin goes low
after the DMA operation is complete. If the
CS8900A Interrupt
Request Pin ISA Bus Interrupt PacketPage base + 0022h
INTRQ3 (Pin 35) IRQ5 0003h
INTRQ0 (Pin 32) IRQ10 0000h
INTRQ1 (Pin 31) IRQ11 0001h
INTRQ2 (Pin 30) IRQ12 0002h
Table 1. Interrupt Assignments

DS271PP3 19
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
DMABurst bit is set, the pin goes low 32 µs after
the start of a DMA transfer.
The DMA pin pairs are arranged on the CS8900A
to facilitate board layout. Crystal recommends the
configuration in Table 2 when connecting these
pins to the ISA bus.
For a description of DMA mode, see Section 5.4 on
page 90.
3.3 Reset and Initialization
3.3.1 Reset
Seven different conditions cause the CS8900A to
reset its internal registers and circuits.
3.3.1.1 External Reset, or ISA Reset
There is a chip-wide reset whenever the RESET pin
is high for at least 400 ns. During a chip-wide reset,
all circuitry and registers in the CS8900A are reset.
3.3.1.2 Power-Up Reset
When power is applied, the CS8900A maintains re-
set until the voltage at the supply pins reaches ap-
proximately 2.5 V. The CS8900A comes out of
reset once Vcc is greater than approximately 2.5 V
and the crystal oscillator has stabilized.
3.3.1.3 Power-Down Reset
If the supply voltage drops below approximately
2.5 V, there is a chip-wide reset. The CS8900A
comes out of reset once the power supply returns to
a level greater than approximately 2.5 V and the
crystal oscillator has stabilized.
3.3.1.4 EEPROM Reset
There is a chip-wide reset if an EEPROM check-
sum error is detected (see Section 3.4 on page 21).
3.3.1.5 Software Initiated Reset
There is a chip-wide reset whenever the RESET bit
(Register 15, SelfCTL, Bit 6) is set.
3.3.1.6 Hardware (HW) Standby or Suspend
The CS8900A goes though a chip-wide reset when-
ever it enters or exits either HW Standby mode or
HW Suspend mode (see Section 3.7 on page 26 for
more information about HW Standby and Sus-
pend).
3.3.1.7 Sof tware (SW) Suspend
Whenever the CS8900A enters SW Suspend mode,
all registers and circuits are reset except for the ISA
I/O Base Address register (located at PacketPage
base + 0020h) and the SelfCTL register (Register
15). Upon exit, there is a chip-wide reset (see
Section 3.7 on page 26 for more information about
SW Suspend).
3.3.2 Allowing Time for Reset Operation
After a reset, the CS8900A goes through a self con-
figuration. This includes calibrating on-chip analog
circuitry, and reading EEPROM for validity and
configuration. Time required for the reset calibra-
tion is typically 10 ms. Software drivers should not
access registers internal to the CS8900A during
this time. When calibration is done, bit INITD in
the Self Status Register (register 16) is set indicat-
ing that initialization is complete, and the SIBUSY
bit in the same register is cleared indicating the EE-
PROM is no longer being read or programmed.
3.3.3 Bus Reset Considerations
The CS8900A reads 3000h from IObase+0Ah after
the reset, until the software writes a non-zero value
at IObase+0Ah. The 3000h value can be used as
part of the CS8900A signature when the system
scans for the CS8900A. See Section 4.10 on
page 76.
CS8900A DMA
Signal (Pin #) ISA DMA Signal PacketPage base + 0024h
DMARQ0 (Pin 15) DRQ5 0000h
DMACK0 (Pin 16) DACK5
DMARQ1 (Pin 13) DRQ6 0001h
DMACK1 (Pin 14) DACK6
DMARQ2 (Pin 11) DRQ7 0002h
DMACK2 (Pin 12) DACK7
Table 2. DMA Assignments

20 DS271PP3
CS8900A
Crystal LAN™ ISA Ethernet Controller
CIRRUS LOGIC PRODUCT DATA SHEET
After a reset, the ISA bus outputs INTRx and
DMARQx are 3-Stated, thus avoiding any interrupt
or DMA channel conflicts on the ISA bus at power-
up time.
3.3.4 Initialization
After each reset (except EEPROM Reset), the
CS8900A checks the sense of the EEDataIn pin to
see if an external EEPROM is present. If EEDI is
high, an EEPROM is present and the CS8900A au-
tomatically loads the configuration data stored in
the EEPROM into its internal registers (see next
section). If EEDI is low, an EEPROM is not
present and the CS8900A comes out of reset with
the default configuration shown in Table 3.
A low-cost serial EEPROM can be used to store
configuration information that is automatically
loaded into the CS8900A after each reset (except
EEPROM reset). The use of an EEPROM is op-
tional.
The CS8900A operates with any of six standard
EEPROM’s shown in Table 4.
PacketPage
Address Register Contents Register Descriptions
0020h 0300h I/O Base Address*
0022h XXXX XXXX
XXXX X100 Interrupt Number
0024h XXXX XXXX
XXXX XX11 DMA Channel
0026h 0000h DMA Start of Frame
Offset
0028h X000h DMA Frame Count
002Ah 0000h DMA Byte Count
002Ch XXX0 0000h Memory Base Address
0030h XXX0 0000h Boot PROM Base
Address
0034h XXX0 0000h Boot PROM Address
Mask
0102h 0003h Register 3 - RxCFG
0104h 0005h Register 5 - RxCTL
0106h 0007h Register 7 - TxCFG
0108h 0009h Register 9 - TxCMD
010Ah 000Bh Register B - BufCFG
010Ch Undefined Reserved
010Eh Undefined Reserved
0110h Undefined Reserved
0112h 00013h Register 13 - LineCTL
0114h 0015h Register 15 - SelfCTL
0116h 0017h Register 17 - BusCTL
0118h 0019h Register 19 - TestCTL
* I/O base address is unaffected by Software Suspend mode.
Table 3. Default Configuration
EEPROM Type Size (16-bit words)
‘C46 (non-sequential) 64
‘CS46 (sequential) 64
‘C56 (non-sequential) 128
‘CS56 (sequential) 128
‘C66 (non-sequential) 256
‘CS66 (sequential) 256
Table 4. Supported EEPROM Types