Cisco UCS C480 M5 User manual

CISCO SYSTEMS PUBLICATION HISTORY
170 WEST TASMAN DR
SAN JOSE, CA, 95134 REV A.1 AUGUST 19, 2019 
WWW.CISCO.COM
Guide
Cisco UCS C480 M5
Memory Guide

Cisco UCS C480 M5 Memory Guide
1
CONTENTS
Server CPU Module Bay Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Memory Devices (DIMMs and DCPMMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Memory Configurations and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DIMM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DCPMM Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DIMM Memory Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CPU Configuration Without Memory Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
CPU Configuration With Memory Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
System Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DIMM Population Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DIMM Population Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommended DIMM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Capacities for CPU Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
All DIMM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
All DIMM Configurations for 2nd Generation Intel® Xeon® Scalable Processors . . . . . . 19
All DIMM Configurations for Intel® Xeon® Scalable Processors . . . . . . . . . . . . . . . . . 21
Mixed DIMM/DCPMM Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DIMM/DCPMM Configurations for 2nd Generation Intel® Xeon® Scalable Processors . . . 22
Installing a DIMM or DIMM Blank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Cisco UCS C480 M5 Memory Guide
Server CPU Module Bay Layout
3
Server CPU Module Bay Layout
The front of the C480 M5 server is shown in Figure 1. Notice that there are two CPU Module bays, the lower
bay (Bay 1) and the upper bay (Bay 2).
The CPU numbering is as follows:
■Lower Bay: CPU1 and CPU2
■Upper Bay: CPU3 and CPU4
Figure 1 C480 CPU Module Bays
Drive Bay 01 Drive Bay 02 Drive Bay 03 Drive Bay 04 Drive Bay 05 Drive Bay 06 Drive Bay 07 Drive Bay 08 Drive Bay 09 Drive Bay 10
Drive Bay 11
Drive Bay 12 Drive Bay 13 Drive Bay 14 Drive Bay 15 Drive Bay 16 Drive Bay 17 Drive Bay 18 Drive Bay 19 Drive Bay 20 Drive Bay 21 Drive Bay 22 Drive Bay 23 Drive Bay 24
306011
CPU Module Bay 1
CPU Module Bay 2
Each CPU has six memory channels, and each channel controls two memory DIMMs.
The channel numbering for each CPU is as follows:
Lower Bay:
■CPU1: A, B, C, D, E, F
■CPU2: G, H, J, K, L, M
Upper Bay:
■CPU3: A, B, C, D, E, F
■CPU4: G, H, J, K, L, M

Cisco UCS C480 M5 Memory Guide
4
Memory Organization
Memory Organization
The standard memory features are:
— Clock speed: 2666 MHz or 2933 MHz depending on CPU type
— Ranks per DIMM: 1, 2, 4, or 8
— DIMM operational voltage: 1.2 V
— Registered ECC DDR4 DIMMS (RDIMMs), Load-reduced DIMMs (LRDIMMs),
through-silicon via DIMMs (TSV DIMMs), or Intel®OptaneTM DC Persistent Memory
Modules (DCPMMs).
Memory is organized with six memory channels per CPU, with up to two memory devices per
channel, as shown in Figure 2. CPU1 and CPU2 are in the lower bay; CPU3 and CPU 4 are in the
upper bay. CPU1 and CPU2 control up to 24 DIMMs and CPU3 and CPU4 also control up to 24
DIMMs, for a total of up to 48 DIMMs total for the server.
Figure 2 C480 Memory Organization
CPU 2/
CPU4
24 DIMMS
6 memory channels per CPU,
up to 2 DIMMs per channel
A1 A2
B1 B2
E1 E2
Chan B
Chan C
Chan D
Chan A
Chan E
Chan F
Chan H
Chan J
Chan L
Chan M
F1 F2
CPU1/
CPU3
Slot 2 Slot 1
Slot 2 Slot 1
H2 H1
J2 J1
L2 L1
M2 M1
Chan G
G2 G1
Chan K
K2 K1
C1 C2
D1 D2

Cisco UCS C480 M5 Memory Guide
Memory Devices (DIMMs and DCPMMs)
5
Memory Devices (DIMMs and DCPMMs)
The available memory devices for the C480 M5 are listed in Table 1.
Table 1 Available DDR4 DIMMs and DCPMMs
Product ID (PID) PID Description Voltage Ranks
/DIMM
2666-MHz DIMMs
UCS-MR-128G8RS-H 128 GB DDR4-2666-MHz TSV-RDIMM/8R/x4 1.2 V 8
UCS-MR-X64G4RS-H 64 GB DDR4-2666-MHz TSV-RDIMM/4R/x4 1.2 V 4
UCS-ML-X64G4RS-H 64 GB DDR4-2666-MHz LRDIMM/4R/x4 1.2 V 4
UCS-MR-X32G2RS-H 32 GB DDR4-2666-MHz RDIMM/2R/x4 1.2 V 2
UCS-ML-X32G2RS-H 32 GB DDR4-2666-MHz LDIMM/2R/x4 1.2 V 2
UCS-MR-X16G1RS-H 16 GB DDR4-2666-MHz RDIMM/1R/x4 1.2 V 1
2933-MHz DIMMs
UCS-ML-128G4RT-H 128 GB DDR4-2933-MHz LRDIMM/4Rx4 1.2 V 4
UCS-ML-X64G4RT-H 64 GB DDR4-2933-MHz LRDIMM/4Rx4 1.2 V 4
UCS-MR-X64G2RT-H 64 GB DDR4-2933-MHz RDIMM/2Rx4 1.2 V 2
UCS-MR-X32G2RT-H 32GB DDR4-2933-MHz RDIMM/2Rx4 1.2 V 2
UCS-MR-X16G1RT-H 16 GB DDR4-2933-MHz RDIMM/1Rx4 1.2 V 1
Intel®OptaneTM DC Persistent Memory Product
UCS-MP-128GS-A0 Intel®OptaneTM DC Persistent Memory, 128GB, 2666MHz
UCS-MP-256GS-A0 Intel®OptaneTM DC Persistent Memory, 256GB, 2666MHz
UCS-MP-512GS-A0 Intel®OptaneTM DC Persistent Memory, 512GB, 2666MHz
Intel® OptaneTM DC Persistent Memory Product Operational Modes
UCS-DCPMM-AD App Direct Mode
UCS-DCPMM-MM Memory Mode
Memory Mirroring Option
N01-MMIRROR Memory mirroring option

Cisco UCS C480 M5 Memory Guide
6
Memory Configurations and Modes
Memory Configurations and Modes
DIMM Guidelines
NOTE: For more details on DIMM population and guidelines, see DIMM Population
Rules, page 14.
■System speed is dependent on the CPU DIMM speed support. Refer to Table 1 on page 5 for
DIMM speeds.
■The C480 M5 server supports three different memory reliability, availability, and
serviceability (RAS) modes:
— Independent Channel Mode
— Mirrored Channel Mode
— Lockstep Channel Mode
NOTE: Mixing of Non-Mirrored and Mirrored mode is not allowed.
■Do not mix RDIMMs, LRDIMMs, and TSV-RDIMMs.
■Single-rank DIMMs can be mixed with dual-rank DIMMs in the same channel
■For best performance, observe the following:
— DIMMs with different timing parameters can be installed on different slots within the
same channel, but only timings that support the slowest DIMM will be applied to all.
As a consequence, faster DIMMs will be operated at timings supported by the slowest
DIMM populated.
— When one DIMM is used, it must be populated in DIMM slot 1 (farthest away from the
CPU) of a given channel.
— When single or dual rank DIMMs are populated for two DIMMs per channel (2DPC),
always populate the higher number rank DIMM first (starting from the farthest slot).
For example, first populate slot 1 with dual rank DIMMs. Then populate DIMM slot 2
with single-rank DIMMs.
■DIMMs for all four CPUs must always be configured identically.
■Cisco memory from previous generation servers (DDR3 and DDR4) is not compatible or
supported with the UCS C480 server
NOTE: System performance is optimized when the DIMM type and quantity are equal
for both CPUs, and when all channels are filled equally across the CPUs in the server.

Cisco UCS C480 M5 Memory Guide
Memory Configurations and Modes
7
DCPMM Guidelines
DCPMMs require second generation Intel Xeon Scalable Family processors. First generation Xeon Scalable
processors do not support DCPMMs.
All installed DCPMMs must be the same size. Mixing DCPMMs of different capacities is not supported.
DCPMMs and DIMMs must be populated as shown in Table 2 (6 DIMMs per CPU with 2, 4, or 6 DCPMMs per
CPU, as shown).
Table 2 2nd Generation Intel®Xeon®Scalable Processor DIMM and DCPMM1Physical Configurations (quad
socket)
DIMM
to
DCPMM
Count
CPU 1 (lower bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
F2 F1 E2 E1 D2 D1 C2 C1 B2 B1 A2 A1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM
DIMM
to
DCPMM
Count CPU 2 (lower bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
M2 M1 L2 L1 K2 K1 J2 J1 H2 H1 G2 G1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM
DIMM
to
DCPMM
Count
CPU 3 (upper bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
F2 F1 E2 E1 D2 D1 C2 C1 B2 B1 A2 A1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM

Cisco UCS C480 M5 Memory Guide
8
Memory Configurations and Modes
■Four CPUs must be installed when using DCPMMs.
■For Memory Mode and App Direct Mode, install a minimum 2 DCPMMs and 6 DIMMs per CPU
■When either Memory Mode or Mixed Mode is used, the recommended ratio of DIMM capacity to
DCPMM capacity is between 1:16 and 1:4, and 1:4 achieves the best performance. For example, 6x
16 GB DIMMs + 2x 256 GB DCPMMs is a capacity ratio of 1:5.33 (96GB:512GB). In Mixed Mode, the
ratio is between memory and only the volatile portion of the DCPMMs. This ratio requirement does
not apply to App Direct mode. See Table 3 for DCCPM memory modes.
Table 3
Intel®OptaneTM DC Persistent Memory Modes
App Direct Mode: DCPMM operates as a solid-state disk storage device. Data is saved and is
non-volatile. Both DCPMM and DIMM capacity counts towards CPU tiering
(both DCPMM and DIMM capacities count towards the CPU capacity limit)
Memory Mode:1DCPMM operates as a 100% memory module. Data is volatile and DRAM acts
as a cache for DCPMMs. Only DCPMM capacity counts towards CPU tiering
(only the DCPMM capacity counts towards the CPU capacity limit). This is
the factory default mode.
Mix Mode: DRAM as cache. Only DCPMM capacity counts towards CPU tiering (only the
DCPMM capacity counts towards the CPU capacity limit).
Intel®OptaneTM DC Persistent Memory Modes
■For each memory channel with both a DCPMM and a DIMM installed, the DCPMM is installed in
channel slot 2 (closest to the CPU) and the DIMM is installed in channel slot 1.
■To maximize performance, balance all memory channels
■In configurations with DCPMMs installed, memory mirroring is supported, with two restrictions:
DIMM
to
DCPMM
Count CPU 4 (upper bay)
iMC1 iMC0
Channel 2 Channel 1 Channel 0 Channel 2 Channel 1 Channel 0
M2 M1 L2 L1 K2 K1 J2 J1 H2 H1 G2 G1
6 to 2 DIMM DIMM DCPMM DIMM DIMM DIMM DCPMM DIMM
6 to 4 DIMM DCPMM DIMM DCPMM DIMM DIMM DCPMM DIMM DCPMM DIMM
6 to 6 DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM DCPMM DIMM
Notes:
1. All systems must be fully populated with four CPUs when using DCPMMs at this time.
Notes:
1. For Memory Mode, the Intel-recommended DIMM to DCPMM capacity ratio in the same CPU socket is from 1:4 to
1:16.
Table 2 2nd Generation Intel®Xeon®Scalable Processor DIMM and DCPMM1Physical Configurations (quad
socket)

Cisco UCS C480 M5 Memory Guide
Memory Configurations and Modes
9
■Mirroring is only enabled on the DIMMs installed in the server; The DCPMMs themselves do
not support mirroring.
■Only App Direct mode is supported. Memory mirroring cannot be enabled when DCPMMs are
in Memory Mode or Mixed Mode.
For detailed Intel DCPMM configurations, refer to the following link:
https://www.cisco.com/c/en/us/td/docs/unified_computing/ucs/c/hw/C480M5/install/C480M5/C480M5_
chapter_011.html?bookSearch=true#concept_b1k_mbt_tgb

Cisco UCS C480 M5 Memory Guide
10
DIMM Memory Mirroring
DIMM Memory Mirroring
Memory mirroring is supported only on the DIMMs; DCPMMs do not support memory mirroring. When memory
mirroring is enabled, the memory subsystem simultaneously writes identical data to two adjacent channels.
If a memory read from one of the channels returns incorrect data due to an uncorrectable memory error,
the system automatically retrieves the data from the other channel. Atransient or soft error in one channel
does not affect the mirrored data, and operation continues unless there is a simultaneous error in exactly
the same location on a DIMM and its mirrored DIMM. Memory mirroring reduces the amount of memory
available to the operating system by 50% because only one of the two populated channels provides data.
CPU/Memory Configuration With Memory Mirroring
There are two CPU modules, one in each CPU bay. The lower CPU module occupies Bay 1 and the upper CPU
module occupies Bay 2. CPU 1 and CPU2 are in Bay 1; CPU 3 and 4 are in Bay 2.
Select from 4, 6, 8, or 12 DIMMs per CPU (DIMMs for all four CPUs must be configured identically). In
addition, the memory mirroring option (N01-MMIRROR) as shown in Table 1 on page 5 must be selected.
The DIMMs will be placed by the factory as shown in the following tables.
CPU 1 DIMM Placement in Channels
(for identical ranked DIMMs) CPU 2 DIMM Placement in Channels (for identical ranked DIMMs)
CPU 1 CPU 2
8(A1,B1); (D1,E1) (G1, H1); (K1, L1)
12 (A1, B1, C1); (D1, E1, F1) (G1, H1, J1); (K1, L1, M1)
16 (A1, A2, B1, B2); (D1, D2, E1, E2) (G1, G2, H1, H2); (K1, K2, L1, L2)
24 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2,
F1, F2) (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)
CPU 3 DIMM Placement in Channels
(for identical ranked DIMMs) CPU 4 DIMM Placement in Channels (for identical ranked DIMMs)
CPU 3 CPU 4
8(A1,B1); (D1,E1) (G1, H1); (K1, L1)
12 (A1, B1, C1); (D1, E1, F1) (G1, H1, J1); (K1, L1, M1)
16 (A1, A2, B1, B2); (D1, D2, E1, E2) (G1, G2, H1, H2); (K1, K2, L1, L2)
24 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2,
F1, F2) (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)
NOTE: System performance is optimized when the DIMM type and quantity are equal
for both CPUs, and when all channels are filled equally across the CPUs in the server.

Cisco UCS C480 M5 Memory Guide
DIMM Memory Mirroring
11
Normal CPU/Memory Configuration (no memory mirroring)
There are two CPU modules, one in each CPU bay. The lower CPU module occupies Bay 1 and the upper CPU
module occupies Bay 2. CPU 1 and CPU2 are in Bay 1; CPU 3 and 4 are in Bay 2.
Select from 4, 6, 8, or 12 DIMMs per CPU (DIMMs for all four CPUs must be configured identically). The
DIMMs will be placed by the factory as shown in the following tables.
CPU 1 DIMM Placement in Channels (for identically ranked DIMMs)
4(A1, B1); (D1, E1)
6(A1, B1, C1); (D1, E1, F1)
8(A1, A2, B1, B2); (D1, D2, E1, E2)
12 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2, F1, F2)
CPU 2 DIMM Placement in Channels (for identically ranked DIMMs)
4(G1, H1); (K1, L1)
6(G1, H1, J1); (K1, L1, M1)
8(G1, G2, H1, H2); (K1, K2, L1, L2)
12 (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)
CPU 3 DIMM Placement in Channels (for identically ranked DIMMs)
4(A1, B1); (D1, E1)
6(A1, B1, C1); (D1, E1, F1)
8(A1, A2, B1, B2); (D1, D2, E1, E2)
12 (A1, A2, B1, B2, C1, C2); (D1, D2, E1, E2, F1, F2)
CPU 4 DIMM Placement in Channels (for identically ranked DIMMs)
4(G1, H1); (K1, L1)
6(G1, H1, J1); (K1, L1, M1)
8(G1, G2, H1, H2); (K1, K2, L1, L2)
12 (G1, G2, H1, H2, J1, J2); (K1, K2, L1, L2, M1, M2)

Cisco UCS C480 M5 Memory Guide
12
System Speeds
System Speeds
System speed is dependent on how many DIMMs are populated per channel and the CPU DIMM speed
support. See Table 4 for details.
Table 4 2666-MHz DIMM Memory Speeds with Different Intel®Xeon®Scalable Processors
DIMM and CPU
Frequencies
(MHz) DPC
TSV-
RDIMM
(8Rx4) - 
128 GB
(MHz)
TSV-
RDIMM 
(4Rx4) - 
64 GB
(MHz)
LRDIMM 
(4Rx4) - 
64 GB (MHz)
RDIMM 
(2Rx4) - 
32 GB (MHz)
LRDIMM 
(2Rx4) - 
32 GB (MHz)
RDIMM 
(1Rx4) - 
16 GB (MHz)
1.2 V 1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
DIMM = 2666
CPU = 2666 1DPC 2666 2666 2666 2666 2666 2666
2DPC 2666 2666 2666 2666 2666 2666
DIMM = 2666
CPU = 2400 1DPC 2400 2400 2400 2400 2400 2400
2DPC 2400 2400 2400 2400 2400 2400
DIMM = 2666
CPU = 2133 1DPC 2133 2133 2133 2133 2133 2133
2DPC 2133 2133 2133 2133 2133 2133
Table 5 2933-MHz DIMM Memory Speeds with Different 2nd Generation Intel®Xeon®Scalable Processors
DIMM and
CPU
Frequencies
(MHz)
DPC

LRDIMM
(4Rx4)-
128 GB (MHz)

LRDIMM 
(4Rx4) - 
64 GB (MHz)
RDIMM
(2Rx4) - 
64 GB (MHz)
RDIMM 
(2Rx4) - 
32 GB (MHz)
RDIMM 
(1Rx4) - 
16 GB (MHz)
1.2 V 1.2 V 1.2 V 1.2 V 1.2 V
DIMM = 2933
CPU = 2933 1DPC 2933 2933 2933 2933 2933
2DPC 2933 2933 2933 2933 2933
DIMM = 2933
CPU = 2666 1DPC 2666 2666 2666 2666 2666
2DPC 2666 2666 2666 2666 2666
DIMM = 2933
CPU = 2400 1DPC 2400 2400 2400 2400 2400
2DPC 2400 2400 2400 2400 2400
DIMM = 2933
CPU = 2133 1DPC 2133 2133 2133 2133 2133
2DPC 2133 2133 2133 2133 2133

Cisco UCS C480 M5 Memory Guide
Physical Layout
13
Physical Layout
Each CPU has six channels:
■CPU1 and CPU3 have channels A, B, C, D, E, and F
■CPU2 and CPU 4 have channels G, H, J, K, L, and M
Each channel has two slots: slot 1 and slot 2. The blue-colored DIMM slots are for slot 1 and the black slots
for slot 2.
As an example, slots A1, B1, C1, D1, E1, and F1 belong to slot 1, while A2, B2, C2, D2, E2, and F2 belong to
slot 2.
Figure 3 shows how slots and channels are physically laid out on the motherboard. The slots on the right
half of the motherboard (channels A, B, C, D, E, and F) are associated with CPU 1 for the lower bay and CPU
3 for the upper bay, while the slots on the left half of the motherboard (channels G, H, J, K, L, and M) are
associated with CPU 2 for the lower bay and CPU 4 for the upper bay. The slot 1 (blue) slots are always
located farther away from a CPU than the corresponding slot 2 (black) slots. Slot 1 slots (blue) are
populated before slot 2 slots (black).
Figure 3 Physical Layout of C480 M5 CPU Channels and Slots
Front of Lower CPU Module (Bay 1)
CPU 2 CPU 1
A2
A1
B2
B1 C2
C1
F1
F2
E1
E2
D1
D2
G2 G1 H2
H1
J2 J1
M1
M2
L1
L2
K1
K2
Front of Upper CPU Module (Bay 2)
CPU 4 CPU 3
A2
A1
B2
B1 C2
C1
F1
F2
E1
E2
D1
D2
G2 G1 H2
H1
J2 J1
M1
M2
L1
L2
K1
K2
Top View
Top View

Cisco UCS C480 M5 Memory Guide
14
DIMM Population Rules
DIMM Population Rules
When considering the memory configuration of your server, consider the following items:
■Each channel has two DIMM slots (for example, channel A = slots A1 and A2).
— A channel can operate with one or two DIMMs installed.
— If a channel has only one DIMM, populate slot 1 first (the blue slot).
■When both CPUs are installed, populate the DIMM slots of each CPU identically.
— For 1, 2, 3, 4, and 6 DIMMs per socket configurations, fill the blue slots (slot 1) in the
memory channels as per recommended DIMM populations in DIMM Population
Order, page 16.
— For 8 and 12 DIMMs per socket configurations, fill the blue slots (slot 1) and black
slots (slot 2) as per recommended DIMM populations in DIMM Population Order,
page 16.
— Refer to DIMM Population Order, page 16 for more details.
■For best memory performance, use identical DIMM types within a server (same speed, size
and ranks).
■For optimum performance, populate at least one DIMM per memory channel per CPU.
■When populating DIMM slots for optimal performance, multiples of 12 DIMMs are best
because there are 6 memory channels per CPU socket and 2 CPUs must be populated.
■For populations of 1 DIMM per channel (1DPC) and 2DPC, with Intel Xeon scalable processors,
all supported DIMMs on Cisco UCS M5 servers run at their labeled speed provided the
processor supports that speed.
■At the same memory speed, 2 DPC may perform slightly better than 1 DPC for RDIMMs
(workload dependent).
■For small to medium memory capacities, whenever possible, install dual rank RDIMMs for
optimal performance. Dual rank RDIMMs perform slightly better than single rank RDIMMs.
Single rank DIMMs limit the performance of memory-intensive workloads in 1 DIMM per
channel configurations.
■For applications requiring larger memory capacities, use 64 GB LRDIMMs or 64 GB TSV
RDIMMs. At 1DPC, 64 GB LRDIMMs outperform 64 GB TSV DIMMs. However, at 2DPC the
performance of 64 GB LRDIMMs and 64 GB TSV RDIMMs is similar except for latency. At 2DPC,
64 GB TSV DIMMs have better latency than 64 GB LRDIMMs.
■For applications requiring larger memory configuration, if there is a possibility of expanding
the memory size in the future, use TSV RDIMMs. 64 GB TSV RDIMMs can be mixed with 128 GB
TSV DIMMs if needed.
■128GB RDIMMs should be used for the largest memory capacity requirement (up to 3 TB for a
2 socket server). These DIMMs provide the maximum memory size supported for 2 socket
UCS M5 servers based on Intel Xeon scalable processors.

Cisco UCS C480 M5 Memory Guide
DIMM Population Rules
15
■When mixing DIMMs, the following rules must be followed:
— RDIMMs cannot be mixed with LRDIMMs.
— RDIMMs of different sizes can be mixed within a channel. When mixing RDIMMs of
different densities (sizes), populate DIMMs with the highest density first. For
example, if you have to mix 32 GB RDIMMs with 16 GB RDIMMs, then populate the 32
GB DIMMs in blue slots (or slot 1) and then 16 GB DIMMs in black slots (or slot 2).
— RDIMMs of different ranks can be mixed within a channel. When mixing RDIMMs with
different ranks, populate RDIMMs with the higher rank first. For example, when
mixing dual-rank RDIMMs with single-rank RDIMMs populate the dual-rank RDIMMs in
blue slots first and then single-rank RDIMMs in black slots.
— 64 GB 2933-MHz LRDIMMs can only be mixed with 128 GB 2933-MHz LRDIMMs.
— 2666-MHz TSV RDIMMs cannot be mixed with standard RDIMMs. For example, 64 GB
2666-MHz TSV RDIMMs cannot be mixed with 32 GB 2666-MHz RDIMMs.
— TSV RDIMMs cannot be mixed with LRDIMMs. For example, 128 GB 2666-MHz TSV
RDIMMs cannot be mixed with 64 GB 2666-MHz LRDIMMs.
— 64 GB 2666-MHz TSV RDIMMs can only be mixed with 128 GB 2666-MHz TSV RDIMMs.
— 64 GB 2666-MHz LRDIMMs can only be mixed with 32 GB 2666-MHz LRDIMMs.
■Any DIMM installed in a DIMM socket for which the CPU is absent is not recognized.
■Observe the DIMM mixing rules shown in Table 6
Table 6 DIMM Rules for C480 M5 Servers
DIMM Parameter DIMMs in the Same Channel DIMM in the Same Slot1
DIMM Capacity
RDIMM = 16, 32, 64, 128 GB
LRDIMM = 64 GB, 128 GB
TSV-RDIMM = 64 GB, 128GB
DIMMs in the same channel (for
example, A1 and A2) can have
different capacities.


Do not mix TSV-RDIMMS with
LRDIMMs nor RDIMMs
For best performance, DIMMs in the
same slot (for example, A1, B1, C1,
D1, E1, F1) should have the same
capacity.

Do not mix TSV-RDIMMS with
LRDIMMs nor RDIMMs
DIMM Speed
2666-MHz or 2933-MHz DIMMs will run at the lowest
speed of the CPU installed DIMMs will run at the lowest speed
of the CPU installed
DIMM Type
TSV-RDIMMS, RDIMMs, or
LRDIMMs
Do not mix DIMM types in a
channel Do not mix DIMM types in a slot
Notes:
1. Although different DIMM capacities can exist in the same slot, this will result in less than optimal performance.
For optimal performance, all DIMMs in the same slot should be identical.

Cisco UCS C480 M5 Memory Guide
16
DIMM Population Order
DIMM Population Order
Populate the DIMMs for a CPU according to Table 7.
Table 7 C480 M5 DIMM Population Order
Populate CPU1 or CPU 3 Slots Populate CPU2 or CPU 4 Slots
Blue Slots Black slots Blue slots Black slots
1(A1) -(G1) -
2(A1, D1) -(G1, K1) -
3(A1, B1, C1) -(G1, H1, J1) -
4(A1,B1); (D1,E1) -(G1,H1); (K1,L1) -
6(A1,B1); (C1,D1);
(E1, F1) -(G1,H1); (J1,K1); (L1, M1) -
8(A1,B1); (D1,E1) (A2,B2); (D2,E2) (G1,H1); (K1,L1) (G2,H2); (K2,L2)
12 (A1,B1); (C1,D1);
(E1, F1) (A2,B2); (C2,D2);
(E2, F2) (G1, H1); (J1, K1);
(L1, M1) (G2,H2); (J2,K2);
(L2,M2)
NOTE: 5, 7, 9, 10, 11 DIMMs per CPU is not recommended.
■The maximum combined memory allowed in the 12 DIMM slots controlled by any one CPU is
768 GB. To populate the 12 DIMM slots with more than 768 GB of combined memory, you
must use a high-memory CPU that has a PID that ends with an “M”, for example,
UCS-CPU-6134M.
■All DIMMs must be DDR4 DIMMs that support ECC. Non-buffered UDIMMs and non-ECC DIMMs
are not supported.
■Memory mirroring reduces the amount of memory available by 50 percent because only one
of the two populated channels provides data. When memory mirroring is enabled, you must
install DIMMs in even numbers of channels.
■NVIDIA M-Series GPUs can support only less than 1 TB memory in the server.
■NVIDIA P-Series, V-series, and T-series GPUs can support 1 TB or more memory in the server.
■AMD FirePro S7150 X2 GPUs can support only less than 1 TB memory in the server.

Cisco UCS C480 M5 Memory Guide
Recommended DIMM Configuration
17
Recommended DIMM Configuration
This section explains the recommended DIMM population order rules for best performance.
■All DIMMs must be DDR4 DIMMs.
■Do not mix:
— DIMMs with different clock rates in a channel
— RDIMMs and LRDIMMs or TSV-RDIMMs with any other DIMMs
■There are blue and black DIMM slots. Populate blue slots first.
■When DIMMs ranks are mixed in the same channel, always populate the highest rank DIMM in
the blue DIMM slot and lower rank DIMM(s) in the black DIMM slots.
■Table 8 shows the recommended configurations for 2nd Generation Intel Xeon Scalable
Processors and Table 9 shows the recommended configurations for Intel Xeon Scalable
Processors. The rows highlighted in yellow indicate configurations with optimum
performance.
Table 8 Recommended Memory Configurations for 2nd Generation Intel Xeon Scalable Processors
Total
System
Memory
Size
CPU1 CPU2
DIMM Type Total DIMMs in
the system
Blue Slots Black Slots Blue Slots Black Slots
Bank 1 Bank 2 Bank 1 Bank 2
(A1,B1,C1,D1,
E1, F1) (A2, B2, C2, D2, E2, F2) (G1, H1, J1, K1, L1, M1) (G2, H2, J2, K2, L2, M2)
192 GB 6x16 GB -6x16 GB - R 12
384 GB 6x16 GB 6x16 GB 6x16 GB 6x16 GB R24
384 GB 6x32 GB -6x32 GB - R 12
576 GB 6x32 GB 6x16 GB 6x32 GB 6x16 GB R24
768 GB 6x32 GB 6x32 GB 6x32 GB 6x32 GB R24
768 GB 6x64 GB -6x64 GB - R 12
768 GB 6x64 GB -6x64 GB -LR 12
1152 GB 6x64 GB 6x32 GB 6x64 GB 6x32 GB R24
1536 GB 6x64 GB 6x64 GB 6x64 GB 6x64 GB R24
1536 GB 6x64 GB 6x64 GB 6x64 GB 6x64 GB LR 24
1536 GB 6x128 GB -6x128 GB -LR 12
2304 GB 6x128 GB 6x64 GB 6x128 GB 6x64 GB LR 24
3072 GB 6x128 GB 6x128 GB 6x128 GB 6x128 GB LR 24

Table 9 Recommended Memory Configurations for Intel Xeon Scalable Processors
Total
System
Memory
Size
CPU-1 CPU-2
DIMM Type Total DIMMs in
the system
Blue Slots Black Slots Blue Slots Black Slots
Bank 1 Bank 2 Bank 1 Bank 2
(A1,B1,C1,D1,
E1, F1) (A2, B2, C2, D2, E2, F2) (G1, H1, J1, K1, L1, M1) (G2, H2, J2, K2, L2, M2)
192 GB 6x16 GB -6x16 GB - R 12
384 GB 6x16 GB 6x16 GB 6x16 GB 6x16 GB R24
384 GB 6x32 GB -6x32 GB - R 12
384 GB 6x32 GB -6x32 GB -LR 12
576 GB 6x32 GB 6x16 GB 6x32 GB 6x16 GB R24
768 GB 6x32 GB 6x32 GB 6x32 GB 6x32 GB R24
768 GB 6x32 GB 6x32 GB 6x32 GB 6x32 GB LR 24
768 GB 6x64 GB -6x64 GB -LR 12
768 GB 6x64 GB -6x64 GB -TSV-R 12
1152 GB 6x64 GB 6x32 GB 6x64 GB 6x32 GB LR 24
1536 GB 6x64 GB 6x64 GB 6x64 GB 6x64 GB LR 24
1536 GB 6x64 GB 6x64 GB 6x64 GB 6x64 GB TSV-R 24
1536 GB 6x128 GB -6x128 GB -TSV-R 12
2304 GB 6x128 GB 6x64 GB 6x128 GB 6x64 GB TSV-R 24
3072 GB 6x128 GB 6x128 GB 6x128 GB 6x128 GB TSV-R 24
Cisco UCS C480 M5 Memory Guide
18
Recommended DIMM Configuration

Cisco UCS C480 M5 Memory Guide
Memory Capacities for CPU Classes
19
Memory Capacities for CPU Classes
This following material describes the configurable memory capacities using DIMMs and DCPMMs for various
classes of 2nd Generation Intel® Xeon® Scalable Processors and Intel® Xeon® Scalable Processors used in
C480 M5 servers.
All DIMM Configurations
This section describes the memory capacities for configurations that use all DIMMs.
All DIMM Configurations for 2nd Generation Intel®Xeon®Scalable Processors
Table 10 through Table 12 show the possible configurations for 2nd Generation Intel® Xeon® Scalable
Processors populated with all DIMMs.
Table 10 2nd Gen “M” CPUs With All DIMM Memory (4, 6, 8, or 12 DIMMs per CPU)
Number of DIMMs 
per CPU
Capacity Per DIMM (GB)
16 32 64 128 2561
464 128 256 512 1024
696 192 384 768 1536
8128 256 512 1024 2048
12 192 384 768 1536 N/A
NOTE: The cells marked with N/A indicate a memory capacity that would be more
than the allowable 2048 GB and therefore cannot be configured.
Notes:
1. 256 GB DIMMs are available in CQ4'CY2019
Total Capacity per CPU (GB)

Table 11 2nd Gen “L” CPUs With All DIMM Memory (4, 6, 8, or 12 DIMMs per CPU)
Number of DIMMs 
per CPU
Capacity Per DIMM (GB)
16 32 64 128 2561
464 128 256 512 1024
696 192 384 768 1536
8128 256 512 1024 2048
12 192 384 768 1536 3072
Cisco UCS C480 M5 Memory Guide
20
Memory Capacities for CPU Classes
Notes:
1. 256 GB DIMMs are available in CQ4'CY2019
Total Capacity per CPU (GB)
Table 12 2nd Gen non-“M” and non-“L” CPU All DIMM Memory (4, 6, 8, or 12 DIMMs per CPU)1
Notes:
1. Total DIM M capacity for 2nd Gen non-”M” and non-”L” CPUs cannot exceed 1024 GB
Number of DIMMs 
per CPU
Capacity Per DIMM (GB)
16 32 64 128 2562
2. 256 GB DIMMs are available in CQ4'CY2019
Total Capacity per CPU (GB)
4 64 128 256 512 1024
6 96 192 384 768 N/A
8 128 256 512 1024 N/A
12 192 384 768 N/A N/A
NOTE: The cells marked with N/A indicate a memory capacity that would be more
than the allowable 1024 GB and therefore cannot be configured.