CML Microcircuits CMX649 Installation and operating instructions

Application Note
CMLMicrocircuits
COMMUNICATION SEMICONDUCTOR
S
CMX649 Wireless Voice
Link Design Guide
AN/2WR/649Des/2 November 2004
CMX649 Wireless Voice Link Design Guide Page 1 of 42
1 Introduction
The CMX649 is an innovative adaptive delta modulation (ADM) voice codec that was
designed to serve in advanced wireless voice links. The purpose of this document is
to present an example design that combines the CMX649 with other external
components in a small form factor, low power, fully functional two-way wireless voice
link.
This document presumes that the reader is familiar with the CMX649 and ADM voice
coding. Additional background information can be obtained from the following
application notes, which can be found at www.cmlmicro.com:
• “CMX649 Operation and Application”
• “CMX649 Recommended Settings”
• “Continuously Variable Slope Delta Modulation Tutorial”

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TABLE OF CONTENTS
1Introduction.........................................................................................................1
2Targeted Application & Design Objectives..........................................................3
3Description of Operation .....................................................................................3
4Hardware Description..........................................................................................5
4.1 Voice Coding – CMX649..............................................................................5
4.2 RF Transceiver – MICRF505.......................................................................7
4.2.1 Transmitter............................................................................................9
4.2.2 Receiver..............................................................................................11
4.2.3 Crystal Oscillator.................................................................................12
4.2.4 Frequency Synthesizer.......................................................................12
4.3 Microcontroller – MSP430F1232................................................................13
4.3.1 Data Buffering Scheme.......................................................................15
4.4 Battery .......................................................................................................18
4.5 Voltage Regulators ....................................................................................19
4.6 Peripheral Functions..................................................................................19
5Firmware Description........................................................................................20
5.1.1 Interrupt Vectors.................................................................................21
5.1.2 RESET................................................................................................21
5.1.3 SETUP649..........................................................................................23
5.1.4 SETUPRF...........................................................................................23
5.1.5 MAINLOOP.........................................................................................24
5.1.6 START_RFTX.....................................................................................25
5.1.7 SET_RF_TX ....................................................................................... 25
5.1.8 RFCHIPTX..........................................................................................26
5.1.9 START_RFRX....................................................................................28
5.1.10 SET_RF_RX.......................................................................................30
5.1.11 RFCHIPRX .........................................................................................30
5.1.12 CMX649_TRANSFER.........................................................................34
6Circuit Schematics and Board Layout...............................................................36
7Bill of Materials..................................................................................................40
8Conclusion ........................................................................................................41

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2 Targeted Application & Design Objectives
The design presented in this document is targeted towards a low-power, small form-
factor wireless headset product, but the information is readily adapted to other
wireless voice applications.
The objectives used to guide this design include:
• Small size consistent with mobile/cordless phone wireless headset form factor
• Optimal sound quality
• License-free operation
• Low power consumption for maximum talk-time and standby-time
• Lowest possible bill-of-materials (BOM) cost
3 Description of Operation
Two main circuit areas comprise this wireless voice link design: a base unit (also
called the ‘master’) and a headset unit (also called a ‘slave’). Each unit contains:
• Voice codec: CML Microcircuits CMX649
• RF transceiver: Micrel MICRF505
• Microcontroller: Texas Instruments MSP430F1232
In addition to these three core products, other functions such as battery, low-dropout
voltage regulator, microphone, speaker, and amplifiers are also provided in the
design.
CMX649
Voice
Codec
MICRF505
RF
Transceiver
MSP430F1232
Microcontroller
Encoded voice
TPA6203
Audio
Amp
Rx data frames Rx data
MAX8511
3.3V
Regulator
Voice
Output
Voice
Input
Battery
MAX8510
2.5V
Regulator
8MHz
Crystal
Control
Data frames
Control
Figure 1, Project Block Diagram

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The master and slave units transfer voice data at 166.6kbps over a wireless link in
the European wireless audio band of 863-865MHz (as stated in the CEPT ERC
recommendation 70-03 Annex 13). Time-division duplexing is used to create a
simulated full-duplex link. Channel selection and volume adjustment are provided in
the design.
Operation is similar on both the master and slave units. The CMX649 uses 27.8kbps
adaptive delta modulation (ADM) to encode the microphone audio input. ADM is an
optimal voice-coding scheme for wireless voice applications. ADM uses one-bit-per
sample (instead of eight or sixteen bits per sample), and unlike many other schemes,
ADM does not require data framing. These two abilities combine to give ADM robust
performance when subjected to bit errors present in wireless environments.
The encoded voice data is passed to the MSP430F1232 microcontroller where it is
buffered and assembled into frames. The microcontroller then passes the data
frames to the MICRF505 RF transceiver for transmission to a ‘paired’ board. The
MICRF505 transmits the data frame at an over-the-air rate of 166.6kbps on a
transmission frequency determined by software configuration.
Data is transferred over the RF link in a half-duplex manner, but the perceived effect
is full duplex because the MICRF505’s data rate is more than twice the CMX649’s
coding rate. Two RF frames can be exchanged serially over the RF link, one in each
direction, within the time it takes the CMX649 to encode one audio packet and
decode another audio packet in parallel.
Framing, ID and
Command Information
576µs
Data
7.68ms
Post Tx
384µs
Bit Sync
1.15ms
Figure 2, Over-The-Air Transmitted Frame Example
The MICRF505 on the ‘paired’ board receives the transmission, extracts the data
frames, and passes those frames to the MSP430F1232 for processing. The

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MSP430F1232 disassembles the frames and passes the resulting bit stream to the
CMX649 for reconstruction of the voice signal. The CMX649 ADM decoder converts
the bit stream into the original analog voice signal, which is then passed to a power
amplifier for delivery to a headset speaker.
Tx Frame:
Master to Slave Tx Frame: Slave to Master
TDD Latency
= 2ms
Time
Figure 3, TDD Latency
In addition to providing the time-division duplexing scheme, the microcontroller
firmware also accomplishes a ‘pairing’ procedure that causes the master and slave
units to communicate together while ignoring signals from other sources.
4 Hardware Description
4.1 Voice Coding – CMX649
The CMX649 is ideal for this design because of its robust voice coding, low power
consumption, and highly integrated feature set. Some of the many features of this
innovative chip are:
• Full duplex ADM, CVSD, Linear PCM, µ-law PCM, and A-law PCM
• Ability to transcode between coding schemes
• Low power consumption (2.5mA @ Vdd=3.0V typical)
• Data clock recovery
• Flexible clock generation capabilities
• Programmable ‘voice activity detector’ (VAD)
• Programmable digital scrambler
• Flexible microcontroller interfaces
• Programmable filters, including anti-alias and anti-image filters
• Programmable gain stages
• ‘Sidetone’ generation
• On-chip microphone amplifier
The CMX649 operates from a 3.3V supply and uses an 8MHz clock source in this
design. The CMX649’s extensive power control settings are adjusted in software to
provide the lowest possible power consumption.

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Two interfaces are used between the MSP430F1232 and the CMX649. Control
signals are sent to the CMX649 via its ‘CBUS’ serial interface, while voice data is
transferred between the codec and microcontroller over the CMX649’s ‘burst mode
interface’. Highlights of the burst mode interface include:
o Tx output data is applied to CMX649 TX DATA pin.
o Rx input data is applied to CMX649 RX DATA pin.
o ‘Sync’ signal, used to mark byte boundaries, is applied to CMX649
STROBE pin.
o ‘Burst Clock’ signal, used to clock bits in/out, is applied to the CMX649 RX
CLK pin.
The CBUS interface is a simple, SPI-compatible, five-wire serial interface. For more
information on CBUS, please download the “CBUS Microcontroller Interface”
application note, and for more information on the CMX649 burst mode interface,
please download the “CMX649 Operation and Application” application note. Both of
these documents, as well as other information on CML products, can be found at the
following website: www.cmlmicro.com
A noise-canceling microphone was chosen for this design because of its lower-noise
performance as compared to other types of microphones. A Zetex ZXMP3A13F
p-channel MOSFET is used to power down the microphone during sleep mode; this
eliminates the current draw from the microphone bias circuit during unneeded
periods. The noise-canceling microphone output signal is amplified by the CMX649
internal microphone amplifier. The gain and frequency response of this microphone
amplifier is determined by external components.
The amplified microphone signal passes through the CMX649 programmable
anti-alias filter before arriving at its ADM encoder. The programmable anti-alias filter
bandwidth is set to 2.9kHz in software. This bandwidth value was selected because
it is approximately equal to 1/10th of the ADM data rate, and this fraction of audio
bandwidth results in optimal voice quality.
The amplified and filtered microphone signal is then applied to the CMX649 ADM
encoder, which converts the analog signal into a 1-bit-per-sample serial data stream.
The encoding ‘bit clock’ (i.e. sampling clock) is derived from the crystal input signal
and is set to 27.8kbps through software control. The ADM encoder settings, such as
time constants and integrator step sizes, have been empirically determined to
provide outstanding voice quality at the selected sampling rate.
The digital data stream is passed through the programmable scrambler and
delivered to the CMX649 TX DATA pin. The data is then sent, in eight-bit bytes, to
the microcontroller via the ‘burst mode interface’.
At the receiving end, the recovered digital data stream is passed from the
microcontroller to the CMX649 RX DATA pin in eight-bit bytes. The CMX649’s ‘burst
mode interface’ internally converts the eight-bit bytes into a serial data stream that is
fed into its ADM decoder. The ADM decoder converts the digital data into a

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reproduction of the original analog voice signal. The ADM decoder settings, such as
time constants and integrator step sizes, have been empirically determined to
provide outstanding voice quality at the selected sampling rate. The recovered voice
signal is filtered and amplified before it is sent out of the AUDIO OUT pin to the audio
amplifier.
The Texas Instruments TPA6203 differential audio amplifier is used to drive the
earpiece speaker with the audio output from the CMX649. The TPA6203 was
selected because of its low noise, low quiescent current, small form factor, and low
cost. A single-ended input configuration was used because of the single-ended
output from the CMX649 voice codec. The differential output capability of the
TPA6203 was used because:
• No output DC blocking capacitor was required, saving cost and space,
minimizing “popping” noises during power up/down transients, and improving
low-frequency audio response.
• Output signal is biased at Vdd/2, regardless of input signal biasing.
• Higher output power (4x) can be realized, for the same power supply voltage
and load impedance, with differential drive as compared to single-ended
output.
The TPA6203 amplifier is supplied directly from the battery to prevent current-surge
induced noise from propagating through to the other components. This capability is
possible due to the wide range of power supply voltage that the TPA6203 can
accept. The “Cbypass” capacitor was added to enhance the amplifier’s power supply
rejection ratio (PSRR). The recommended 10µF Cbypass capacitor is a relatively
expensive component, so the end customer should decide whether the improvement
in PSRR is worth the extra cost and board space required by that component. For
more information on this audio amplifier, please visit
http://focus.ti.com/docs/prod/folders/print/tpa6203a1.html
The speaker used for this design was the Prime Acoustics 20N10 32Ωdevice. This
product was chosen for its small size, low power consumption, and very low cost.
The board layout for this project was performed specifically for this product. For
more information on this speaker, please visit
http://www.speaker.co.kr/product/micro.html.
While this particular speaker was satisfactory for this project, our speaker selection
process did not fully consider real-world production issues. In other words, we did
not have to select a speaker that would fit within a particular plastic injection-molding
cast. The end customer is encouraged to consider their own headset housing as
they select a low cost, small form factor speaker
4.2 RF Transceiver – MICRF505
The RF transceiver circuitry is based on the Micrel MICRF505 ‘zero-IF’ single-chip
transceiver. This device was chosen because of its low external component cost,
device flexibility, and its ability to block co-channel interference.

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The MICRF505 operates on 2.5V from a dedicated voltage regulator to optimize
noise performance. An 8MHz crystal provides the required timing signal for the
MICRF505 in this application; this 8MHz crystal is the only crystal in the design and
is also used to provide timing for both the MSP430F1232 microcontroller and the
CMX649 voice codec. A slight improvement in adjacent channel rejection can be
realized with a dedicated 16MHz crystal for the transceiver, but this improvement
comes at the expense of the additional component cost and required board space.
The design engineer must consider which option would be best for their design.
The MICRF505 internal registers are configured in this design to provide operation in
the European wireless audio band of 863-865MHz (as stated in the CEPT ERC
recommendation 70-03 Annex 13). The MICRF505 is configured to use five 500kHz
channels within this frequency range. The center frequencies of these channels are:
Channel Number Frequency (in MHz)
0 863.0
1 863.5
2 864.0
3 864.5
4 865.0
Table 1, RF Channels Used in Project
The MICRF505 can be easily adjusted to conform to other frequency bands, such as
the 902-928MHz ‘ISM’ (industrial, scientific, and medical) license-free frequency
band used in the USA. In order to modify this design to support operation in other
frequency bands, the following items must be considered:
• Crystal frequency may need to be changed to achieve desired channel
spacing and RF carrier frequency.
• VCO register must be adjusted to change VCO free-running frequency.
• Frequency synthesizer registers (e.g. dividers) must be adjusted to change
channel spacing and RF carrier frequency
• RF output filter components may need to be changed for the new RF carrier
frequency.
Please contact Micrel Semiconductor for assistance in MICRF505
configuration for particular carrier frequencies.
The microcontroller exchanges data and control signals with the MICRF505. Control
signals are sent to the MICRF505 via its 3-wire serial ‘control interface’ (i.e. ‘SCLK’,
‘IO’, ‘CS’ pins). Data exchange with the MICRF505 occurs over its serial ‘data
interface’ (i.e. ‘DATAIXO’ and ‘DATACLK’ pins) at the same 166.6kbps rate as the
air link.
Additional information on the MICRF505 RF transceiver can be found at:
www.micrel.com

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4.2.1 Transmitter
The MICRF505 is properly configured, and a delay for PLL settling time is inserted,
before data from the microcontroller is applied to the MICRF505’s DATAIXO pin for
transmission.
The MICRF505 is placed in synchronous data mode for transmission, and this
causes an internally generated bit clock signal to be presented on the ‘DATACLK’
pin. This bit clock signal, referred to as ‘fBITRATE_CLK’ in the MICRF505 datasheet, is
programmed internally and can be expressed mathematically as follows:
kS)BitRate_cl(7
XCO
KBITRATE_CL 2Refclk_K x
f
f− =
where:
• fBITRATE_CLK = clock frequency used to control the transmitted bit rate
• fXCO = crystal oscillator frequency
• Refclk_K = b5-0 of control register 0x07
• BitRate_clkS = b0 of control register 0x06 and b7-6 of control register 0x07
This signal is used by the microcontroller to control the flow of data into the
MICRF505. The transmit data transitions on the falling edge of the DATACLK signal
and is sampled by the MICRF505 on its rising edge. A value of 166.6kHz (equal to
data rate) is used for fBITRATE_CLK in this application.
(NOTE: The ‘Refclk_K’ value is also used to calculate the modulator clock signal
(‘fMOD_CLK’) and bit synchronizer clock signal (‘fBITSYNC_CLK’), so be aware of this in
your calculations. Changes in ‘Refclk_K’ will cause changes in three different clock
signals! It may be desirable, from a programming complexity standpoint, to only
change the ‘BitRate_clkS’ value to accomplish bitrate clock programming.)
The closed loop modulation mode selected for this project causes the transmit data
to be applied directly to the MICRF505’s VCO. PLL-based synthesizers have an
inherent high-pass filter characteristic, and data streams with long strings of ones or
zeros will create low frequency content that will be attenuated by the synthesizer.
This means that direct VCO modulation of a data signal can result in undesired
attenuation in the signal passband.
To prevent this situation in this design, the transmit data is Manchester encoded in
the microcontroller to ensure that the bandwidth of the data signal is high enough to
be passed by the synthesizer. Manchester encoding effectively doubles the transmit
data rate, resulting in the 166.6kbps rate of data transfer both in and out of the
MICRF505. (CMX649 voice codec rate is 27.8kbps, data rate adjusted for framing
and TDD is 83.3kbps, and actual over-the-air data rate after Manchester encoding is
166.6kbps.)

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The transmit data is internally filtered by the MICRF505 before modulation and
transmission to reduce its spectral content. The degree of filtering is determined by
the MICRF505’s programmed ‘modulator clock” (fMOD_CLK) setting, which can be
represented mathematically by the following formula:
Mod_clkS)(7
XCO
MOD_CLK 2Refclk_K x
f
f− =
where:
• fMOD_CLK = modulator clock frequency
• fXCO = crystal oscillator frequency
• Refclk_K = b5-0 of control register 0x07
• Mod_clkS = b6-4 of control register 0x06
For example, an fMOD_CLK settingof eight times the bit rate results in Gaussian filtering
with a bandwidth-period (BT) product of 1.0. (Please note that a BT=1.0 represents
the maximum amount of filtering available in the MICRF505; higher fMOD_CLK settings
result in higher BT values, which correspond to lower amounts of filtering.) A value
of 1.33MHz is used for fMOD_CLK in this application. Since this fMOD_CLK value
corresponds to eight times the bit rate, the transmit data signal is Gaussian filtered
with a BT=1.0 (maximum filtering).
The frequency deviation must be programmed such that the modulation index is
always greater than or equal to two. The modulation index can be represented as
follows:
Baudrate
)xf2(
IndexModulation dev
=
…where fdev is the single-sided frequency deviation:
offsetdev fBaudratef
+
=
…and foffset is the total frequency offset between transmitter and receiver.
Assuming a baudrate of 166.6kbps and a foffset of 20kHz, the required single-sided
frequency deviation is:
kHz6.186kHz20kHz6.166fdev
=
+
=
MICRF505 control registers 0x04 through 0x07 are programmed such that an fdev of
186.6kHz is realized. After processing, the data waveform is passed to the internal
VCO to create the actual frequency modulation.
The power amplifier is bypassed by setting bit 4 of Control Register 0x02 to 1 in the
SETUPRF firmware subroutine. This was done for two reasons. First, significant RF
power isn’t required for the expected one-meter transmit distance between units.
(Note: designs with expected transmit distances of greater than one meter can
activate the PA and adjust its gain accordingly.) Second, bypassing the PA caused

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a dramatic reduction in current consumption, thereby enhancing battery life and talk-
time.
4.2.2 Receiver
When receive mode is selected, the MICRF505 control registers are adjusted to
cause the following actions to occur:
• Receive mode selected.
• Synchronous data mode selected.
• LNA not bypassed.
• Sallen-Key filter bandwidth set to 340kHz.
• Main channel filter disabled.
• Lock detect enabled.
The antenna input is amplified by a LNA that drives a quadrature mixer. The mixer
output is amplified and presented to a Sallen-Key low-pass filter, whose bandwidth is
set to 340kHz to prevent attenuation in the signal passband.
The main channel filter is bypassed in this application by setting bit 6 of Control
Register 0x02 to 1. The reason for doing this involves a tradeoff between current
consumption, voice quality and BER performance, and is explained as follows.
The formula for estimated receive bandwidth is:
fBW = foffset + fdev + (Baudrate/2)
…where fdev andfoffset are as previously defined,and fBW is the required receive
bandwidth. Substituting previously calculated values yields the estimated receive
bandwidth:
fBW = 20kHz + 186.7kHz + (166.6kHz/2) ≅290kHz
The bandwidth of the main channel lowpass filter must be higher than the required
receive bandwidth to prevent attenuation of energy in the signal passband.
A single 8MHz crystal translates to a maximum main channel lowpass filter cutoff
frequency of 200kHz, significantly lower than the required bandwidth of 290kHz.
This situation would cause significant attenuation of energy in the passband, with a
corresponding degradation of BER.
Three potential remedies for this situation exist:
1. Use two crystals to increase main channel lowpass filter cutoff frequency.
2. Reduce the baud rate to reduce the required bandwidth.
3. Bypass the main channel lowpass filter and keep the same baudrate.
Option 1 requires an extra crystal that presents additional cost and board space.
Option 2 is undesirable because a baudrate reduction would jeopardize either the
voice quality or the TDD nature of the application. Empirical data suggests that
option 3 is an acceptable compromise so long as the Sallen-Key filter bandwidth is

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chosen to avoid attenuation of passband energy. The 340kHz Sallen-Key filter
bandwidth used in this design achieves that objective.
The demodulator output is placed on the DATAIXO pin for presentation to the
microcontroller. During reception, the MICRF505 ‘bit synchronizer’ uses a
programmed clock signal to derive a timing signal that is synchronized to the
incoming data. This internal bit synchronizer clock signal must be equal to 16x the
desired bit rate and is expressed mathematically as follows:
kS)BitSync_cl(7
XCO
KBITSYNC_CL 2Refclk_K x
f
f−
=
where:
• fBITSYNC_CLK = bit synchronizer clock signal
• fXCO = crystal oscillator frequency
• Refclk_K = b5-0 of control register 0x07
• BitSync_clkS = b3-1 of control register 0x06
The resulting signal on the DATACLK pin is derived from this “bit synchronizer” clock
signal and is synchronized to the incoming data stream. The received data on the
DATAIXO pin is sampled by the microcontroller on the rising edge of this DATACLK
signal. A value of 2.667MHz (16 x 166.6kHz) is used for fBITSYNC_CLK in this
application.
The receive signal strength indicator (RSSI), while potentially beneficial for some
applications, is not needed in this project and is therefore not used.
4.2.3 Crystal Oscillator
The MICRF505 crystal oscillator in this design is based on an 8MHz external crystal.
The MICRF505 provides the ability, under software control, to fine-tune the oscillator
frequency by adding internal capacitance to the crystal pins. This feature can be
used as an integral part of a self-calibration procedure, which could be particularly
important if lower tolerance, less expensive crystals are selected for the design. The
ability to adjust crystal frequency by adding on-chip capacitance is utilized in this
project.
4.2.4 Frequency Synthesizer
The voltage controlled oscillator (VCO) ‘free-running’ frequency is set to 868MHz by
writing 0xCD to control register 0x03 on power up. The VCO gain is approximately
67MHz/volt.
(For the following calculations, the ‘0’-set of frequency synthesizer dividers is
referenced because direct VCO modulation is used in this design. Please review the
MICRF505 data sheet for more information.)
The reference oscillator frequency (e.g. crystal frequency) is divided down to create
the desired RF channel spacing (i.e. “phase detector comparison frequency” in

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MICRF505 data sheet). The 12-bit ‘M0’ divider controls the reference oscillator
division ratio and the channel spacing. The ‘M0’ divider spans two control registers
within the MICRF505: bits 3-0 of control register 0x0D and bits 7-0 of control register
0x0E. The formula that relates channel spacing to the ‘M0’ value is:
M0
F
FSpacingChannel XCO
C==
For example, a value of M0=16 will divide the 8MHz reference down to the desired
500kHz channel spacing.
A dual-modulus prescaler is used to generate the carrier frequency through
manipulation of the ‘N0’ and ‘A0’ dividers. The 12-bit N0 divider spans control
registers 0x0B (bits 3-0) and 0x0C (bits 7-0), while the 6-bit A0 divider spans control
registers 0x0A (bits 5-0).
The formula that relates carrier frequency to the ‘N0’ and ‘A0’ values is:
RF Carrier Frequency = Channel Spacing x (16N + A)
For example, with a channel spacing of 500kHz, values of ‘N0’=107 and ‘A0’=14
produce a carrier frequency of 863.0MHz. (NOTE: N0 must be larger than A0 in
order for this to work as described.)
The charge pump is set to 125µA by clearing bit 7 in control register 0x02. The PLL
second order loop filter uses component values that have been calculated based on
the following parameters:
• 166.6kbps data rate
• 3kHz loop bandwidth
• 60°phase margin
• 67MHz/V VCO gain
• 125µA charge pump current
Several third-party loop filter calculator programs are available, including a program
from Micrel called “RF TestBench”. Please consult Micrel for technical assistance
with loop filter component selection.
4.3 Microcontroller – MSP430F1232
The Texas Instruments MSP430F1232 microcontroller was selected for this project
because of its low power consumption and rich feature set.
The MSP430F1232 is placed in its active mode during voice communications and
performs all required system management functions. If voice is absent for more than
twenty-three seconds, the boards will enter powersave mode (MSP430F1232 “Low-
power mode 0”). The master and slave boards, if paired, will wake from powersave
mode when voice is presented at the audio input to the master board.
The microcontroller operates from a 3.3V power supply and an 8MHz crystal in this
design. The 8MHz crystal sources the microcontroller’s ‘basic clock module’ during

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normal operation, and the digitally controlled oscillator (DCO) provides the timing
signal during sleep mode operation.
The MSP430F1232 provides 8kB of FLASH and 256B of RAM. The entire RAM is
used for variables and stack pointer space, and less than 4k of FLASH are used in
this project.
Two universal synchronous/asynchronous receiver/transmitters (USARTs, also
called SPI ports) were required for this design: one USART for the CMX649-to-
MSP430F1232 communications, and another USART for MICRF505-to-
MSP430F1232 communications. While other members of the MSP430 family
contain two SPI ports, the MSP430F1232 with its one SPI port was selected over
other family members because of its cost savings.
The microcontroller’s hardware SPI port services the communications between the
RF transceiver and the microcontroller. A second SPI port, needed for the
communications between the voice codec and the microcontroller, is emulated with a
‘bit-banging’ routine coupled with the TIMER_A function of the MSP430F1232.
The watchdog timer is disabled during normal operations. When the design is
placed in sleep mode, the watchdog timer occasionally causes the circuitry to power
up and check for the presence of audio signals.
The A/D converter provided in the MSP430F1232 is unused in this design. A likely
use for this function in a production design would be for temperature monitoring to
allow for dynamic crystal frequency trimming.
The following tables describe the microcontroller port configurations used in this
design. (For more information on the JTAG programming interface, please consult
the Texas Instruments’ application report entitled “Programming a Flash-Based
MSP430 Using the JTAG Interface”, SLAA149-September 2002.)
PORT 1
Port
Number Port Name Description Input or Output Default Output
Values
P1.0 649TXCLK Timing signal output for TIMER_A Output N/A
P1.1 649RXDATA Received data stream, passed to CMX649 for
decoding. Output High
P1.2 649STRB “Strobe” clocking signal used for CMX649 ‘burst
mode’ interface. Output Low
P1.3 LED Signal is active when LED is active (i.e. volume or
channel changing). Input Low
P1.4 JTAG TCK JTAG clock input. Input N/A
P1.5 JTAG TMS Signal to control the JTAG state machine. Input N/A
P1.6 JTAG TDI JTAG data input and VOL+ shared pin; signal that
increases volume by increasing CMX649 audio
gain.
Input N/A
P1.7 JTAG TDO JTAG data output. Output N/A

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PORT 2
Port
Number Port Name Description Input or Output Default Output
Values
P2.0 ACLK CMX649 xtal/clk input. Output N/A
P2.1 VOL - Signal that decreases volume by decreasing
CMX649 audio output gain. Input N/A
P2.2 CHNL Signal that causes a change in RF channel by
adjusting MICRF505 synthesizer programming. Input N/A
P2.3 649RPLY CMX649 CBUS interface: “reply data” to the
microcontroller. Input N/A
P2.4 649RXCLK CMX649 “burst clock” signal applied to RX CLK
pin. Output low
P2.5 MICR505_CS MICRF505 “chip select” signal. Output low
P2.6 Not present on MSP430F1232
P2.7 Not present on MSP430F1232
PORT 3
Port
Number Port Name Description Input or Output Default Output
Values
P3.0 BATT_SENSE Signal corresponding to battery voltage, to be used
with battery recharging circuit (not included in this
design).
Input N/A
P3.1 MICR505_DATAIXO MICRF505 data interface; SPI output line (‘slave in
master out). Output N/A
P3.2 MICR505_DATAIXO MICRF505 data interface; SPI output line (‘slave
out master in’). Input N/A
P3.3 MICR505_DATACLK MICRF505 data interface; clock input line. Output N/A
P3.4 649TXDATA CMX649 encoded data output. Input N/A
P3.5 649CSN CMX649 CBUS interface: “chip select” line. Output High
P3.6 649_505_SCLK Serial clock signal for both the CMX649 “SCLK”
(CBUS interface) and the MICRF505 “SCLK”
(control interface).
Output Low
P3.7 649_505_CMD Command data signal for both the CMX649 “CMD”
(CBUS interface) and the MICRF505 “IO” (control
interface).
Output Low
Table 2, Microcontroller Port Mapping
Connector J1 provides connections to the microcontroller’s JTAG interface to allow
the device to be reprogrammed and debugged using the Texas Instruments MSP430
Flash Emulation Tool MSP-FETP430IF (not provided).
4.3.1 Data Buffering Scheme
The general flow of data in this design is summarized in the following diagram:
CMX649
Voice Codec
SPI-Rx RXRF_BUF
SPI-Tx RXTF_BUF
Manchester
Encoding
Manchester
Decoding
83.3kbps166.6kbps
MSP430F1232
Microcontroller
MICRF505
RF Transceiver 27.7kbps166.6kbps
Figure 4, Data Processing Flow Path

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Data is exchanged between the RF transceiver and the microcontroller in a
half-duplex fashion via the microcontroller’s SPI port. Data is transferred in a full-
duplex fashion, however, between the microcontroller and the ‘burst mode’ interface
of the CMX649.
A large difference exists between the CMX649 voice coding rate (27.8kbps) and the
over-the-air baud rate used by the MICRF505 (166.6kbps). If the RF transmitter and
CMX649 were activated at the same time, the RF transmitter would transmit the data
faster than the CMX649 could generate the data, and an underflow condition would
quickly occur. In a similar manner, the 166.6kbps received data from the transceiver
would quickly overwrite data being sent to the CMX649 at 27.8kbps. To manage the
speed mismatches and prevent data overwrites/underwrites, a buffering scheme is
implemented in the microcontroller.
Eighty bytes of RAM in the MSP430F1232 are used as data buffers for both transmit
(“RFTX_BUF”) and receive (“RFRX_BUF”) modes. Two microcontroller registers are
used as counters to track the flow of data in and out of RFTX_BUF. These counters,
called FROM649_CNTR and TORF_CNTR, are set to their maximum values when
the transmit mode is first started. The FROM649_CNTR counter is decremented
with each byte of encoded voice data that is passed from the CMX649 to the
MSP430F1232. As the RFTX_BUF fills up, the FROM649_CNTR decreases in
value. When the FROM649_CNTR decreases to the correct value, configuration
data is loaded to the MICRF505 and the RF transmitter is enabled.
180
Data input from
CMX649 Data output to
MICRF505
79 34
RF transmission
begins
RFTX_BUF byte location
Manchester
Encoding
FROM649_CNTR
at maximum value FROM649_CNTR at minimum value
Figure 5, RFTX_BUF Byte Locations
After the RF transceiver is configured and enabled, the following header information
is passed from the microcontroller to the transceiver:
• Bit sync (12 bytes)
• Frame sync (2 bytes)
• Command information (2 bytes)
• Identification information (2 bytes)
The voice data and header information is Manchester encoded in the microcontroller;
this is done to add sufficient transitions to the data signal to prevent the PLL from

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attenuating the signal. The Manchester encoding is performed by splitting the bytes
into nibbles, which are then mapped into a lookup table to obtain the appropriate
Manchester-encoded value. A four-bit nibble will be converted into an eight-bit byte
after Manchester encoding, therefore, the use of Manchester encoding effectively
doubles the amount of data transmitted over the RF link:
Raw binary
data nibble
Manchester
encoded binary
data
Resulting
hex value
0000 10101010 AA
0001 10101001 A9
0010 10100110 A6
0011 10100101 A5
0100 10011010 9A
0101 10011001 99
0110 10010110 96
0111 10010101 95
1000 01101010 6A
1001 01101001 69
1010 01100110 66
1011 01100101 65
1100 01011010 5A
1101 01011001 59
1110 01010110 56
1111 01010101 55
Table 3, Mapping of TX Data to Manchester encoded data
The data is then passed to the MICRF505 for transmission via the microcontroller’s
USART0. The TORF_CNTR is decremented for each byte of data that is passed
from the microcontroller to the MICRF505.
When the last byte of data is transferred out of RFTX_BUF, both FROM649_CNTR
and TORF_CNTR have achieved their minimum values. A four-byte ‘dummy’ packet
is passed to the MICRF505 to ensure that all of the actual data has been
transmitted, and the microcontroller prepares the transceiver for receive operation.
In receive mode, the recovered data is passed from the transceiver to the
microcontroller’s USART0 receive buffer, and then to an eighty-byte section of RAM
referred to as “RFRX_BUF”. Two microcontroller registers are used as counters to
track the flow of data in and out of RFRX_BUF. These counters, called
FROMRF_CNTR and TO649_CNTR, are set to their maximum values when the
receive mode is first started. The FROMRF_CNTR counter is decremented by one
for each byte of data that is passed from the transceiver to the microcontroller. The
TO649_CNTR counter is decremented by one for each byte of data that is passed
from the microcontroller to the CMX649.

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Data input from
MICRF505 Data output to
CMX649
RFRX_BUF byte location
Manchester
Decoding
180 79
TO649_CNTR at
minimum value
TO649_CNTR at
maximum value
Figure 6, RFRX_BUF Byte Locations
The first information that is received corresponds to header information; this
information is not intended for decoding and is not passed to the CMX649. Once the
header is recognized, the subsequent received bytes are passed to the CMX649 for
voice signal reconstruction. Since the transceiver is operating at a much higher data
rate than the CMX649, the data will flow into the RFRX_BUF faster than it is sent out
to the CMX649. Once the first data byte is loaded into the RFRX buffer, data can be
transferred to the CMX649 with no risk of data underflow.
4.4 Battery
The battery chosen for this design is an Ultralife UBC 641730 lithium-polymer
rechargeable battery. Lithium-ion polymer technology was chosen for this project
because of its exceptional energy density and its ability to withstand multiple
charge/discharge cycles with no “memory effect”. This particular battery was chosen
because of its very small form factor and sizeable energy capacity.
The current consumption of this design is dependent on many factors, including how
often the user speaks into the unit, the volume with which the user speaks, the
volume setting for the unit’s speaker, and the RF power setting. The observed value
for current consumption during normal conversation is 19.25mA, which translates to
a “talk time” of approximately 10.4 hours. The observed current consumption for
sleep mode is 140µA, which translates to a “standby time” of approximately 60 days.
(Note: these values are based on 100% battery capacity being available for use, but
the low discharge rate of this design makes this assumption reasonably accurate.)
The battery voltage is monitored by microcontroller P3.0. This function, when paired
with a user-supplied algorithm, can detect low battery voltage and powerdown the
circuitry to prevent excessive discharge and battery damage. The Ultralife UBC
641730 lithium-polymer battery includes a protection module that guards against
excessive current discharge, overvoltage and undervoltage conditions. Please
consult your battery vendor to learn if your lithium-based battery contains such a
protection module, and if not, the steps you must take to ensure safe product
operation.

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Lithium-based batteries provide many benefits, but the technology that yields
these benefits requires special care and precaution, especially with regards to
operating voltage, operating temperature, current discharge rate and
recharging. In particular, lithium-based batteries can be damaged if excessive
discharge occurs, or if an over/undervoltage condition is allowed to develop.
Many lithium-based batteries are supplied with protection circuitry that is
designed to prevent these harmful conditions. Please consult the battery
vendor for more information on care, operation, and recharging issues related
to lithium-based batteries.
The battery circuit is configured to easily accommodate an external, user-supplied
charging circuit. Vendors such as Micrel, Maxim, National Semiconductor, Texas
Instruments and others supply integrated circuits that can form the foundation of a
battery charging circuit.
A Micrel MIC79110 1.2A linear Li-Ion battery charger demonstration board was used
in the development work for this project. Information on the Micrel MIC79110
integrated circuit and demonstration board can be found at:
www.micrel.com.
For more information on this battery and related battery charging issues, please visit:
www.ultralifebatteries.com.
4.5 Voltage Regulators
Two low-voltage dropout (LDO) regulators from Maxim are used in this design. The
low-noise MAX8510EXK25 is used to translate the nominal 3.7V battery voltage to
2.5V for the RF transceiver, and the low-noise MAX8511EXK33 produces the 3.3V
for the other integrated circuits. These products were chosen because of their low
noise performance, small size and low cost. For more information on these
products, please visit: www.maxim-ic.com.
4.6 Peripheral Functions
Two approaches were considered for the timing source used in this design. Each
approach offers costs and benefits, and the end customer must make the
determination regarding which approach best suits their requirements:
• A 16MHz crystal for the RF transceiver and an 8MHz crystal for the
microcontroller and voice codec.
• An 8MHz crystal for the RF transceiver, microcontroller and voice codec
The first approach uses two crystals, one for the RF transceiver and the other for the
voice codec and microcontroller. This approach would yield a slight improvement in
adjacent channel rejection, at a cost of the additional crystal, load capacitors, and
required board space.
The second alternative is the use of a single 8MHz crystal for the RF transceiver,
microcontroller, and voice codec. This approach represented the optimal trade-off

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between performance and costs and was therefore selected as the timing source for
this project.
Temperature monitoring is not performed in this design. The expectation is that the
end customer can pair their own algorithm with the ADC capability afforded by the
MSP430F1232 microcontroller to efficiently perform this function.
5 Firmware Description
The firmware used for the Master board is different than that used in the Slave
board, but both have the same basic structure. The firmware controls the CMX649
voice codec, the RF transceiver, and the transfer of data between them. The master
board synchronizes all communications.
The Master board’s firmware takes advantage of the CMX649’s programmable voice
activity detector (VAD) to determine when voice/audio is present. This allows the
Master board to decide when to power save (i.e. after periods where voice/audio is
consistently absent), and when to wake from power save (i.e. when voice/audio has
been detected).
The firmware source code for this project was written in assembly language and was
compiled using the IAR Embedded Workbench from IAR Systems. More information
concerning the IAR Embedded Workbench can be found at:
http://www.iar.com/Products/EW/
The source code used in this project can be downloaded from the CML website at:
www.cmlmicro.com/products/applications/649/DE6492.zip
The firmware can be reprogrammed using the JTAG programming port (P1.4-1.7), if
desired. More MSP430F1232 programming information can be found in the
following resources:
1. Texas Instruments’ application report “Programming a Flash-Based MSP430
Using the JTAG Interface”, SLAA149-September 2002.
2. Texas Instruments’ document “MSP430x1xx Family User’s Guide”,
SLAU049C, 2003.