Cmsemicon Bat32g137 User manual

BAT32G137 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 1 / 1052 V2.1.1

BAT32G137 User Manual

Ultra-low power 32-bit microcontroller based on ARM® Cortex®-M0+

Rev.2.1.1

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BAT32G137 User's Guide |Documentation Usage Instructions

www.mcu.com.cn 2 / 1052 V2.1.1

Documentation Instructions

This manual is the technical reference manual for the BAT32G137 microcontroller product. The technical

reference manual is the application instruction material on how to use this series of products, including the

structure, function description, working mode and register configuration of each functional module.

The technical reference manual is a description of all functional modules of this series of products. If you want

to know the feature description of the product (that is, the functional configuration), you can refer to the respective

data sheet.

The data sheet information is as follows：

BAT32G137xx：BAT32G137_datasheet_vx.x.x. pdf

Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product

can meet the functional requirements of the design; after basically selecting the required product, you need to check

the technical reference manual to determine whether the working mode of each functional module does meet the

requirement；When determining the selection and entering the programming design stage, you need to read the

technical reference manual in detail to understand the specific implementation and register configuration of each

function. Refer to the data sheet for information on voltages, currents, drive capabilities, and pin assignments when

designing hardware。

For a detailed description of the Cortex-M0+ core, SysTick timer and NVIC, please refer to the respective ARM

documents.

BAT32G137 User's Guide |Documentation Usage Instructions 
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Index 
Documentation Instructions ................................................................................... 2
Chapter 1 CPU....................................................................................................................... 20 
1 verview................................................................................................................................................................... 20 
2 Cortex-M0+ core features...................................................................................................................................... 20 
3 Debug features...................................................................................................................................................... 20 
4 SWD interface pin.................................................................................................................................................. 22 
5 ARM reference document...................................................................................................................................... 23 
Chapter 2 Pin function.......................................................................................................... 24 
1 port function........................................................................................................................................................... 24 
2 port multiplex ......................................................................................................................................................... 24 
3 Register for controlling port function...................................................................................................................... 25 
3.1 Port Mode Register (PMxx) ................................................................................................................................. 27 
3.2 Port Register (Pxx).............................................................................................................................................. 28 
3.3 Pull-up resistance selection register (PUxx)........................................................................................................ 29 
3.4 Port input mode register (PIMxx)......................................................................................................................... 30 
3.5 Port output mode register (POMxx)..................................................................................................................... 31 
3.6 Port mode control register (PMCxx) .................................................................................................................... 32 
3.7 Peripheral I/O Redirection Register 0 (PIOR0).................................................................................................... 33 
3.8 Peripheral I/O Redirection Register 1 (PIOR1).................................................................................................... 35 
3.9 Peripheral I/O Redirection Register 2 (PIOR2).................................................................................................... 36 
3.10 Peripheral I/O Redirection Register 3 (PIOR3).................................................................................................... 37 
4 Handling of unused pins ........................................................................................................................................ 39 
5 Register Settings When Using Multiplexing........................................................................................................... 40 
5.1 The Basic principal of Using Multiplexing Function.............................................................................................. 40 
5.2 Examples of Register Settings for Port and Multiplexing Functions Used ........................................................... 41 
Chapter 3 system structure ................................................................................................. 51 
1 Overview................................................................................................................................................................ 51 
2 system address partitioning................................................................................................................................... 52 
Chapter 4 clock generator.................................................................................................... 54 
1 Function of clock generation circuit........................................................................................................................ 54 
2 Structure of clock generating circuit....................................................................................................................... 56 
3 Register for controlling clock generation circuit...................................................................................................... 58 
3.1 Clock Run Mode Control Register (CMC)............................................................................................................ 59 
3.2 System Clock Control Register (CKC)................................................................................................................. 60 
3.3 Clock Operational Status Control Register (CSC)............................................................................................... 61 
3.4 State register of the oscillation stabilization time counter (OSTC)....................................................................... 63 
3.5 Oscillating Stable Time Select Register (OSTS).................................................................................................. 65 
3.6 Peripheral Enable Registers 0, 1 (PER0, PER1)................................................................................................. 66 
3.7 Secondary system clock provides mode control register (OSMC)....................................................................... 71 
3.8 Frequency selection register (HOCODIV) for high speed internal oscillator........................................................ 72 

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3.9 High speed internal oscillator fine-tuned register (HIOTRM) ............................................................................... 73 
4 System clock oscillating circuit............................................................................................................................... 74 
4.1 X1 oscillating circuit............................................................................................................................................. 74 
4.2 XT1 oscillating circuit........................................................................................................................................... 74 
4.3 high speed internal oscillator............................................................................................................................... 78 
4.4 low-speed internal oscillator ................................................................................................................................ 78 
5 Operation of clock generation circuit...................................................................................................................... 79 
6 clock control........................................................................................................................................................... 81 
6.1 Example of high speed internal oscillator set-up ................................................................................................. 81 
6.2 An example of X1 oscillation circuit..................................................................................................................... 83 
6.3 Setting example of XT1 oscillation circuit............................................................................................................ 84 
6.4 CPU Clock State Transition Diagram .................................................................................................................. 85 
6.5 Conditions before CPU clock transfer and post-transfer processing ................................................................... 91 
6.6 Time required to switch CPU clock and main system clock................................................................................. 93 
6.7 Conditions before clock oscillation stops............................................................................................................. 94 
Chapter 5 hardware divider.................................................................................................. 95 
1 characteristics........................................................................................................................................................ 95 
2 Feature Description ............................................................................................................................................... 95 
3 Register for hardware divider................................................................................................................................. 95 
3.1 division register (DIVIDEND)............................................................................................................................... 96 
3.2 Divisor register (DIVISOR)................................................................................................................................... 96 
3.3 quotient register (QUOTIENT)............................................................................................................................. 96 
3.4 Remainder register (REMAINDER)..................................................................................................................... 96 
3.5 status register (STATUS) .................................................................................................................................... 97 
Chapter 6 Universal Timer Unit Timer4............................................................................... 98 
1 Function of universal timer unit............................................................................................................................ 100 
1.1 Stand-alone channel operation.......................................................................................................................... 100 
1.2 multi-channel coordinated operation function.................................................................................................... 102 
1.3 8-bit timer operation function (only for channel 1 and channel 3 of unit 0). ....................................................... 103 
1.4 LIN-bus support (Cell 0-only channel 3)............................................................................................................ 103 
2 Structure of universal timer unit........................................................................................................................... 104 
2.1 Universal timer unit register list.......................................................................................................................... 107 
2.2 Timer count register mn (TCRmn)..................................................................................................................... 108 
2.3 timer data register mn (TDRmn)........................................................................................................................ 110 
3 Register for controlling universal timer unit.......................................................................................................... 111 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 112 
3.2 Timer Clock Select Register m (TPSm)............................................................................................................. 113 
3.3 timer mode register mn (TMRmn)...................................................................................................................... 116 
3.4 timer status register mn (TSRmn)...................................................................................................................... 120 
3.5 Timer channel allows state register m (TEm) to be ........................................................................................... 121 
3.6 Timer channel start register m (TSm)................................................................................................................ 122 
3.7 Timer channel stop register m (TTm). ............................................................................................................... 123 
3.8 Timer Input-Output Selection Register (TIOS0, TIOS1) .................................................................................... 124 

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3.9 timer output allow register m (TOEm)................................................................................................................ 126 
3.10 Timer output register m (TOm).......................................................................................................................... 127 
3.11 Timer output level register m (TOLm)................................................................................................................ 128 
3.12 Timer output mode register m (TOMm) ............................................................................................................. 129 
3.13 Input switch control register (ISC)...................................................................................................................... 130 
3.14 Noise Filter Admission Register (NFEN1) ......................................................................................................... 131 
3.15 Register for controlling timer input/output pin port function................................................................................ 132 
4 Basic rules for universal timer units ..................................................................................................................... 133 
4.1 Basic Prinicpal of Multi-channel Coordinated Operation Function..................................................................... 133 
4.2 Basic Principal of the 8-bit timer operation function (only for channel 1 and channel 3).................................... 135 
5 Operation of counters .......................................................................................................................................... 136 
5.1 Count Clock (fTCLK) ......................................................................................................................................... 136 
5.2 Starting sequence of Counter............................................................................................................................ 138 
5.3 Operation of counters........................................................................................................................................ 139 
6 Control of channel output (TOmn pin).................................................................................................................. 144 
6.1 Structure of TOmn pin output circuit.................................................................................................................. 144 
6.2 Output settings for TOmn pins........................................................................................................................... 145 
6.3 Precaution for Channel Output Operation ......................................................................................................... 146 
6.4 One-time operation of TOmn bits ...................................................................................................................... 151 
6.5 About timer interrupts and TOmn pin output at start of counting ....................................................................... 152 
7 Control of timer input (TImn)................................................................................................................................ 153 
7.1 Structure of TImn pin input circuit...................................................................................................................... 153 
7.2 noise filter.......................................................................................................................................................... 153 
7.3 Precautions When Operating Channel Inputs ................................................................................................... 154 
8 Independent channel operation function of universal timer unit........................................................................... 155 
8.1 Operation as Interval Timer/Square wave Output.............................................................................................. 155 
8.2 Run as External Event Counter......................................................................................................................... 159 
8.3 Operation as a frequency divider (only for channel 0 of cell 0).......................................................................... 162 
8.4 Operation as an input pulse interval measurement ........................................................................................... 165 
8.5 Operation as voltage high and low level width measurement of input signal..................................................... 168 
8.6 Operation as delay counter ............................................................................................................................... 172 
9 Multi-channel coordinated operation function of universal timer unit ................................................................... 175 
9.1 Operation as single trigger pulse output function............................................................................................... 175 
9.2 Operation as PWM Function.............................................................................................................................. 182 
9.3 Operation as Multiple PWM Output Function..................................................................................................... 189 
10 Precautions when using a universal timer unit..................................................................................................... 197 
10.1 Precautions When Using Timer Output............................................................................................................. 197 
Chapter 7 Timer A............................................................................................................... 198 
1 Function of timer A............................................................................................................................................... 198 
2 Structure of timer A.............................................................................................................................................. 199 
3 Register for control timer A.................................................................................................................................. 200 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 200 
3.2 Secondary system clock provides mode control register (OSMC)..................................................................... 201 

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3.3 timer A count register 0 (TA0)............................................................................................................................ 202 
3.4 timer A control register 0 (TACR0). ................................................................................................................... 203 
3.5 Timer AI/O control register 0 (TAIOC0) ............................................................................................................. 204 
3.6 timer A control register 0 (TAMR0).................................................................................................................... 206 
3.7 Timer A Event Pin Selection Register 0 (TAISR0)............................................................................................. 207 
3.8 Port Mode Register x (PMx) .............................................................................................................................. 208 
4 Operation of timer A............................................................................................................................................. 209 
4.1 Reload register and counter override ................................................................................................................ 209 
4.2 timer mode......................................................................................................................................................... 210 
4.3 pulse output mode............................................................................................................................................. 211 
4.4 Event Counter Mode.......................................................................................................................................... 212 
4.5 pulse width measurement mode........................................................................................................................ 214 
4.6 pulse period measurement mode...................................................................................................................... 215 
4.7 Collaboration with EVENTC............................................................................................................................... 216 
4.8 Output settings for each mode........................................................................................................................... 216 
5 Precautions when using timer A .......................................................................................................................... 217 
5.1 Start and stop control of count........................................................................................................................... 217 
5.2 Access to flags (TEDGF and TUNDF bits of the TACR0 register)..................................................................... 217 
5.3 Access to a counter register.............................................................................................................................. 217 
5.4 Changes in Patterns.......................................................................................................................................... 218 
5.5 Set-up steps for TAO and TAIO pins................................................................................................................. 218 
5.6 When timer A not used...................................................................................................................................... 218 
5.7 Stopping execution clock of timer A................................................................................................................... 218 
5.8 Configuration steps for deep sleep mode (event counter mode)....................................................................... 219 
5.9 Functional limitations in deep sleep mode (event counter mode only) .............................................................. 219 
5.10 Forced count stop with TSTOP bit..................................................................................................................... 219 
5.11 digital filter ......................................................................................................................................................... 219 
5.12 The Case of Selecting fIL as Count Source....................................................................................................... 219 
Chapter 8 Timer B............................................................................................................... 220 
1 Function of timer B............................................................................................................................................... 220 
2 Structure of timer B.............................................................................................................................................. 221 
3 Register for control timer B.................................................................................................................................. 222 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 223 
3.2 timer B mode register (TBMR)........................................................................................................................... 224 
3.3 Timer B count control register (TBCNTC).......................................................................................................... 225 
3.4 Timer B Control Register (TBCR)...................................................................................................................... 226 
3.5 Timer B interrupt enable register (TBIER) ......................................................................................................... 227 
3.6 Timer B Status Register (TBSR)........................................................................................................................ 228 
3.7 Timer BI/O control register (TBIOR).................................................................................................................. 230 
3.8 Timer B Counter (TB) ........................................................................................................................................ 232 
3.9 timer b general register a, b, c, d....................................................................................................................... 233 
3.10 port register and port mode register .................................................................................................................. 235 
4 Operation of timer B............................................................................................................................................. 236 

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4.1 Common Issues Concerning Multiple Models and Functions............................................................................ 236 
4.2 timer mode (input capture function)................................................................................................................... 241 
4.3 timer mode (output comparison function).......................................................................................................... 244 
4.4 PWM mode........................................................................................................................................................ 248 
4.5 phase counting mode........................................................................................................................................ 252 
5 timer B interrupt................................................................................................................................................... 255 
6 Precautions when using timer B .......................................................................................................................... 257 
6.1 Phase difference, overlap and pulse width in phase counting mode................................................................. 257 
6.2 mode switching.................................................................................................................................................. 257 
6.3 Switch of count source ...................................................................................................................................... 257 
6.4 Set-up steps for TBIO0 and TBIO1 pins............................................................................................................ 258 
6.5 external clock TBCLK0 and TBCLK1................................................................................................................. 258 
6.6 Read and write access to SFR.......................................................................................................................... 258 
6.7 Input capture operation when stopping count.................................................................................................... 259 
Chapter 9 timer C................................................................................................................ 260 
1 Function of timer C .............................................................................................................................................. 260 
2 Structure of timer C.............................................................................................................................................. 261 
3 Register for controlling timer C ............................................................................................................................ 262 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 262 
3.2 timer C count register (TC)................................................................................................................................ 263 
3.3 timer C count buffer register (TCBUF)............................................................................................................... 263 
3.4 timer C control register 1 (TCCR1).................................................................................................................... 264 
3.5 timer C control register 1 (TCCR2).................................................................................................................... 265 
3.6 timer C status register (TCSR) .......................................................................................................................... 266 
4 Operation of timer C ............................................................................................................................................ 267 
4.1 count source...................................................................................................................................................... 267 
4.2 Timer C starts counting actions......................................................................................................................... 267 
4.2.1 Select the Timer M signal as the setting and action for the trigger.................................................................. 268 
4.2.2 Select the settings and actions when the software fires.................................................................................. 269 
4.3 Timer C counts stop actions.............................................................................................................................. 270 
4.3.1 Select Comparator 1 as Trigger Settings and Actions..................................................................................... 270 
4.3.2 Settings and actions when software is triggered ............................................................................................. 270 
4.4 Input capture action........................................................................................................................................... 271
4.5 timer C count reset action.................................................................................................................................. 272 
4.6 Interruption of timer C........................................................................................................................................ 274 
5 Precautions for Using Timer C............................................................................................................................. 275 
5.1 Read/write of register ........................................................................................................................................ 275 
5.2 overflow interrupt............................................................................................................................................... 275 
5.3 Input capture and timer C count reset actions................................................................................................... 275 
5.4 Steps when timer C and timer M and comparator 1 are linked.......................................................................... 275 
Chapter 10 Timer M.............................................................................................................. 276 
1 Function of timer M.............................................................................................................................................. 276 
2 Structure of timer M............................................................................................................................................. 277 

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3 Register for controlling timer M............................................................................................................................ 278 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 279 
3.2 timer M EVENTC register (TMELC)................................................................................................................... 280 
3.3 Timer M Start Register (TMSTR)....................................................................................................................... 281 
3.4 timer M mode register (TMMR).......................................................................................................................... 282 
3.5 Timer M PWM Function Selection Register (TMPMR) ...................................................................................... 283 
3.6 Timer M Functional Control Register (TMFCR)................................................................................................. 284 
3.7 Timer M outputs master permissive register 1 (TMOER1) ................................................................................ 285 
3.8 Timer M outputs Master Permissive Register 2 (TMOER2)............................................................................... 286 
3.9 Timer M Output Control Register (TMOCR) ...................................................................................................... 287 
3.10 timer m digital filter function selection register i (TMDFi) (i=0,1)........................................................................ 290 
3.11 Timer M control register i (TMCRi) (i=0,1)......................................................................................................... 292 
3.12 Timer MI/O control register Ai(TMIORAi) (i=0,1) ............................................................................................... 297 
3.13 Timer MI/O control register Ci(TMIORCi) (i=0,1)............................................................................................... 299 
3.14 Timer M Status Register 0 (TMSR0) ................................................................................................................. 301 
3.15 Timer M Status Register 1 (TMSR1) ................................................................................................................. 306 
3.16 timer m interrupt enable register i (TMIERi) (i=0,1) ........................................................................................... 312 
3.17 timer MPWM function output level control register i (TMPOCRi) (i=0,1)............................................................ 313 
3.18 timer M counter i (TMi) (i=0,1)........................................................................................................................... 314 
3.19 timer m general register ai, bi, ci, di................................................................................................................... 316 
3.20 Port Mode Register (PMxx, PMCxx).................................................................................................................. 325 
4 Common Issues on Multiple Models.................................................................................................................... 326 
4.1 count source...................................................................................................................................................... 326 
4.2 buffer operation ................................................................................................................................................. 327 
4.3 synchronous operation ...................................................................................................................................... 330 
4.4 Forced Cutoff of Pulse Output........................................................................................................................... 331 
4.5 Events entered from the Event Coordination Controller(EVENTC).................................................................... 333 
4.6 Events output to the event Coordination Controller(EVENTC)/data transfer controller (DMA) .......................... 334 
5 Operation of timer M............................................................................................................................................ 335 
5.1 Input capture function........................................................................................................................................ 335 
5.2 output comparison function ............................................................................................................................... 340 
5.3 PWM function.................................................................................................................................................... 345 
5.4 Reset synchronous PWM mode........................................................................................................................ 350 
5.5 complementary PWM mode .............................................................................................................................. 353 
5.6 PWM3 mode...................................................................................................................................................... 358 
6 Timer M interrupt ................................................................................................................................................. 360 
7 Precautions when using timer M.......................................................................................................................... 363 
7.1 Read and write access to SFR.......................................................................................................................... 363 
7.2 mode switching.................................................................................................................................................. 363 
7.3 count source...................................................................................................................................................... 364 
7.4 Input capture function........................................................................................................................................ 364 
7.5 Set-up steps for TMIOAi, TMIOBi, TMIOCi, TMIODi pins (i=0,1)....................................................................... 364 
7.6 external clock TMCLK ....................................................................................................................................... 365 
7.7 complementary PWM mode .............................................................................................................................. 365 

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8 PWMOP............................................................................................................................................................... 370 
8.1 Features of PWMOP ......................................................................................................................................... 371 
8.2 Register for PWMOP......................................................................................................................................... 371 
8.3 Running of PWMOP.......................................................................................................................................... 377 
8.3.1output forced cut-off ........................................................................................................................................ 377 
8.3.2Hardware Undoing (HS_SEL=0) ..................................................................................................................... 377 
8.3.3Software Undoing (HS_SEL=1)....................................................................................................................... 387 
8.3.4Hazard countermeasure.................................................................................................................................. 393 
8.3.5Output Force Cutoff of Source Checked Out and Unchecked Out.................................................................. 394 
8.3.6The time sequence diagram when the value of the counter of timer M reaches 0000 H................................. 394 
8.3.7Configuration Steps......................................................................................................................................... 396 
8.4 Precautions........................................................................................................................................................ 397 
Chapter 11 real-time clock .................................................................................................. 398 
1 The Function of Real-time Clock.......................................................................................................................... 398 
2 Structure of real-time clock.................................................................................................................................. 398 
3 Register for controlling real-time clock................................................................................................................. 400 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 401 
3.2 Real-time clock selection register (RTCCL)....................................................................................................... 402 
3.3 Real-time clock control register 0 (RTCC0)....................................................................................................... 403 
3.4 Real-time clock control register 1 (RTCC1)....................................................................................................... 404 
3.5 Clock error correction register (SUBCUD)......................................................................................................... 406 
3.6 Second Count Register (SEC)........................................................................................................................... 407 
3.7 Minute Count Register (MIN)............................................................................................................................. 407 
3.8 Hour count register (HOUR).............................................................................................................................. 408 
3.9 Day count register (DAY)................................................................................................................................... 410 
3.10 Week count register (WEEK)............................................................................................................................. 411 
3.11 Month count register (MONTH) ......................................................................................................................... 412 
3.12 Year count register (YEAR)............................................................................................................................... 412 
3.13 Alarm clock minute register (ALARMWM) ......................................................................................................... 413 
3.14 Alarm clock hour register (ALARMWH) ............................................................................................................. 413 
3.15 Alarm clock week register (ALARMWW)........................................................................................................... 413 
3.16 port mode register and port register .................................................................................................................. 414 
4 Operation of real-time clock................................................................................................................................. 415 
4.1 Real Time clock Operation start ........................................................................................................................ 415 
4.2 Transition to sleep mode after start of operation ............................................................................................... 416 
4.3 Real-time clock counter reading and writing...................................................................................................... 417 
4.4 Alarm setting for real-time clock ........................................................................................................................ 419 
4.5 1 Hz output of real-time clock............................................................................................................................ 420 
4.6 Example of clock deviation calibration for a real-time clock............................................................................... 421 
Chapter 12 15-bit interval timer .......................................................................................... 423 
1 The function of a 15-bit interval timer................................................................................................................... 423 
2 Structure of 15-bit interval timer........................................................................................................................... 423 
3 Register for controlling 15-bit interval timer.......................................................................................................... 424 

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3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 424 
3.2 Real-time clock selection register (RTCCL)....................................................................................................... 425 
3.3 Control register for 15-bit interval timer (ITMC) ................................................................................................. 426 
4 Operation of a 15-bit interval timer....................................................................................................................... 427 
4.1 Run-time sequence of 15-bit interval timer........................................................................................................ 427 
4.2 The operation of the counter is started after returning from the sleep mode and the transfer to the sleep mode is 
repeated............................................................................................................................................................ 428 
Chapter 13 Clock output/buzzer output control circuit .................................................... 429 
1 The Function of Clock Output/Buzzer Output Control Circuit............................................................................... 429 
2 Structure of clock output/buzzer output control circuit ......................................................................................... 430 
3 Register for control clock output/buzzer output control circuit.............................................................................. 430 
3.1 Clock output selection register n (CKSn)........................................................................................................... 430 
3.2 Register for controlling clock output/buzzer output pin port function.................................................................. 432 
4 Operation of clock output/buzzer output control circuit ........................................................................................ 433 
4.1 Operation of the Output Pin............................................................................................................................... 433 
5 Precautions for Clock Output/Buzzer Output Control Circuit................................................................................ 433 
Chapter 14 watchdog timer................................................................................................. 434 
1 Function of watchdog timer.................................................................................................................................. 434 
2 Structure of watchdog timer................................................................................................................................. 434 
3 Register for controlling watchdog timer................................................................................................................ 436 
3.1 Watchdog timer enable register (WDTE)........................................................................................................... 436 
3.2 WDTCFG configuration register (WDTCFG0/1/2/3) .......................................................................................... 437 
4 Operation of watchdog timer................................................................................................................................ 438 
4.1 Operation control of watchdog timer.................................................................................................................. 438 
4.2 Setting of overflow time of watchdog timer........................................................................................................ 439 
4.3 Watchdog timer window settings during opening............................................................................................... 440 
4.4 Setting of watchdog timer interval interrupt ....................................................................................................... 441 
4.5 Operation of watchdog timer when WDTCFG is not configured........................................................................ 441 
Chapter 15 A/D converter.................................................................................................... 442 
1 Functions of A/D Converter.................................................................................................................................. 442 
2 Register for controlling A/D converter.................................................................................................................. 444 
2.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 445 
2.2 Mode register 0 (ADM0) for A/D converter ........................................................................................................ 446 
2.3 Mode register 1 for A/D converter (ADM1) ........................................................................................................ 451 
2.4 Mode register 2 for A/D converter (ADM2) ........................................................................................................ 452 
2.5 A/D converter trigger mode register (ADTRG)................................................................................................... 453 
2.6 Analog input channel assignment register (ADS).............................................................................................. 454 
2.7 12-bit A/D conversion result register (ADCR).................................................................................................... 456 
2.8 8-bit A/D conversion result register (ADCRH).................................................................................................... 457 
2.9 Conversion Result Compare Upper Value Setting Register (ADUL) ................................................................. 458 
2.10 Translation Results Compare Lower Limit Settings Register (ADLL) ................................................................ 458 
2.11 A/D Sample Time Control Register (ADNSMP)................................................................................................. 459 

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2.12 A/D Sample Time Extension Register (ADSMPWAIT) ...................................................................................... 460 
2.13 A/D test register (ADTES) ................................................................................................................................. 461 
2.14 A/D status register (ADFLG).............................................................................................................................. 462 
2.15 A/D charge/discharge control register (ADNDIS)............................................................................................... 463 
2.16 Register for controlling analog input pin port function........................................................................................ 464 
3 Input voltage and conversion results ................................................................................................................... 465 
4 Operation mode of the A/D Converter ................................................................................................................. 466 
4.1 Software trigger mode (select mode, continuous conversion mode) ................................................................. 466 
4.2 Software Trigger Mode (Select Mode, Single Conversion Mode)...................................................................... 467 
4.3 Software Trigger Mode (Scan Mode, Continuous Conversion Mode)................................................................ 468 
4.4 Software Trigger Mode (Scan Mode, Single Conversion Mode)........................................................................ 469 
4.5 Hardware triggers no-wait mode (select mode, continuous conversion mode) ................................................. 470 
4.6 Hardware triggers no-wait mode (select mode, Single Conversion Mode)........................................................ 471 
4.7 Hardware triggered no-wait mode (scan mode, continuous conversion mode)................................................. 472 
4.8 Hardware triggered no-wait mode (scan mode, Single Conversion Mode)........................................................ 473 
4.9 Hardware triggered wait mode (select mode, continuous conversion mode) .................................................... 474 
4.10 Hardware triggered wait mode (select mode, Single Conversion Mode)........................................................... 475 
4.11 Hardware triggered wait mode (scan mode, continuous conversion mode) ...................................................... 476 
4.12 Hardware triggered wait mode (scan mode, Single Conversion Mode)............................................................. 477 
5 Converter Set-up Flowchart................................................................................................................................. 478 
5.1 Settings for software trigger mode..................................................................................................................... 478 
5.2 Hardware Trigger No Wait Mode Settings......................................................................................................... 479 
5.3 Settings for Hardware Trigger Wait Mode ......................................................................................................... 480 
5.4 Settings when selecting the output voltage/internal reference voltage of the temperature sensor .................... 481 
5.5 Settings for test mode........................................................................................................................................ 482 
Chapter 16 D/A Converter ................................................................................................... 483 
1 Function of D/A Converter ................................................................................................................................... 483 
2 Structure of D/A converter ................................................................................................................................... 484 
3 Register for controlling D/A converter.................................................................................................................. 485 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 485 
3.2 Mode register (DAM) for D/A converter. ............................................................................................................ 486 
3.3 D/A conversion value setting register i(DACSi) (i=0,1)...................................................................................... 486 
3.4 event output target selection register n(ELSELRn), n=00~21 ........................................................................... 487 
3.5 Register for controlling analog input pin port function........................................................................................ 487 
4 Operation of D/A Converter ................................................................................................................................. 488 
4.1 Normal mode operation..................................................................................................................................... 488 
4.2 Operation of Real-time Output Mode................................................................................................................. 489 
4.3 Output Timing of D/A Conversion Values.......................................................................................................... 490 
5 Precautions of using the D/A converter ............................................................................................................... 491 
Chapter 17 comparator........................................................................................................ 492 
1 Function of comparator........................................................................................................................................ 492 
2 Structure of comparator....................................................................................................................................... 493 
3 Register for control comparator ........................................................................................................................... 495 

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3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 496 
3.2 Comparator mode set-up register (COMPMDR)................................................................................................ 497 
3.3 Comparator filter control register (COMPFIR) ................................................................................................... 498 
3.4 Comparator output control register (COMPOCR).............................................................................................. 500 
3.5 Comparator built-in reference voltage control register (CVRCTL) ..................................................................... 502 
3.6 Comparator built-in reference voltage selection register (CiRVM)..................................................................... 503 
3.7 Comparator 0 input signal selection control register (CMPSEL0)...................................................................... 504 
3.8 Comparator 1 input signal selection control register (CMPSEL1)...................................................................... 505 
3.9 Register for controlling analog input pin port function........................................................................................ 506 
4 Operation Instructions.......................................................................................................................................... 507 
4.1 Digital filter for comparator i (i=0,1).................................................................................................................... 509 
4.2 comparator i interrupt (i=0,1)............................................................................................................................. 509 
4.3 Event signal output to the Coordination Controller(EVENTC) ........................................................................... 510 
4.4 Output of comparator i (i=0,1)............................................................................................................................ 511 
4.5 Stop and provision of comparator clock............................................................................................................. 511 
Chapter 18 programmable gain amplifier (PGA) ............................................................... 512 
1 Function of Programmable Gain Amplifier........................................................................................................... 512 
2 Structure of programmable gain amplifier............................................................................................................ 513 
3 Register of programmable gain amplifier............................................................................................................. 514 
3.1 Peripheral Enable Register 1 (PER1)................................................................................................................ 514 
3.2 programmable gain amplifier control register (PGAnCTL)................................................................................. 515 
3.3 Register for controlling analog input pin port function........................................................................................ 515 
4 Operation of programmable gain amplifier........................................................................................................... 516 
4.1 Starting operation steps of programmable gain amplifier .................................................................................. 516 
4.2 Stopping operation step of programmable gain amplifier .................................................................................. 517 
Chapter 19 universal serial communication unit .............................................................. 518 
1 Functions of Universal Serial Communication Unit.............................................................................................. 520 
1.1 3-wire Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20,SSPI21)............................................................ 520 
1.2 UART (UART0~UART2).................................................................................................................................... 521 
1.3 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) ......................................................................................... 522 
2 Structure of universal serial communication unit.................................................................................................. 523 
2.1 shift register....................................................................................................................................................... 526 
2.2 Low 8-bit or low 9-bit for serial data register mn (SDRmn)................................................................................ 526 
3 Register for controlling universal serial communication unit ................................................................................ 528 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 529 
3.2 Serial clock selection register m (SPSm)........................................................................................................... 530 
3.3 Serial mode register mn (SMRmn).................................................................................................................... 531 
3.4 Serial Communication Run Set-up Register mn (SCRmn)................................................................................ 533 
3.5 Serial data register mn (SDRmn)....................................................................................................................... 535 
3.6 Serial flag clear trigger register mn (SIRmn)...................................................................................................... 537 
3.7 Serial state register mn (SSRmn)...................................................................................................................... 538 
3.8 Serial channel start register m (SSm)................................................................................................................ 540 
3.9 Serial channel stop register m (STm). ............................................................................................................... 541 

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3.10 Serial channel allows state register m (SEm).................................................................................................... 542 
3.11 Serial output allows register m (SOEm)............................................................................................................. 543 
3.12 Serial output register m (SOm).......................................................................................................................... 544 
3.13 Serial output level register m (SOLm)................................................................................................................ 545 
3.14 Input switch control register (ISC)...................................................................................................................... 547 
3.15 Noise filter allows register 0 (NFEN0)................................................................................................................ 548 
3.16 Register for controlling serial input/output pin port function............................................................................... 549 
4 Idle Mode............................................................................................................................................................. 550 
4.1 Unit Stop Operation........................................................................................................................................... 550 
4.2 Stop by Channel................................................................................................................................................ 551 
5 Operation of Serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21) Communication with 3 Lines ..... 552 
5.1 master transmission .......................................................................................................................................... 553 
5.2 master receive................................................................................................................................................... 561 
5.3 Master send and receive ................................................................................................................................... 569 
5.4 Slave send......................................................................................................................................................... 577 
5.5 slave receive...................................................................................................................................................... 585 
5.6 Slave send and receive..................................................................................................................................... 591 
5.7 Calculation of transmission clock frequency...................................................................................................... 600 
5.8 Processing steps for errors occurring during 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, 
SSPI21) communication.................................................................................................................................... 602 
6 Clock synchronization serial communication operation of slave selectioninput function...................................... 603 
6.1 Slave send......................................................................................................................................................... 606 
6.2 slave receive...................................................................................................................................................... 616 
6.3 Slave send and Receive.................................................................................................................................... 623 
6.4 Calculation of transmission clock frequency...................................................................................................... 633 
6.5 Processing steps when an error occurs during clock synchronization serial communication of a slave selection 
input function..................................................................................................................................................... 634 
7 Operation of UART(UART0~UART2) Communication......................................................................................... 635 
7.1 UART Send ....................................................................................................................................................... 636 
7.2 UART Receive................................................................................................................................................... 645 
7.3 Calculation of Baud Rate................................................................................................................................... 652 
7.4 Processing steps when an error occurs during UART (UART0~UART2) communication................................. 656 
8 Operation of LIN Communication......................................................................................................................... 657 
8.1 LIN Send ........................................................................................................................................................... 657
8.2 LIN receiving...................................................................................................................................................... 660 
9 Operation of Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20,IIC21) Communication............................................. 665 
9.1 address segment sending ................................................................................................................................. 666 
9.2 data transmission .............................................................................................................................................. 671 
9.3 data receiving.................................................................................................................................................... 674 
9.4 Generation of Stop Condition ............................................................................................................................ 678 
9.5 Calculation of transfer rate ................................................................................................................................ 679 
9.6 Processing steps when an error occurs in a simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) communication 
process.............................................................................................................................................................. 681 
Chapter 20 serial interface IICA.......................................................................................... 682 

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1 The Function of Serial Interface IICA................................................................................................................... 682 
2 Structure of Serial Interface IICA......................................................................................................................... 685 
3 Register for controlling serial interface IICA......................................................................................................... 688 
3.1 Peripheral Enable Register 0 (PER0)................................................................................................................ 689 
3.2 IICA control register n0 (IICCTLn0)................................................................................................................... 689 
3.3 IICA status register n (IICSn)............................................................................................................................. 694 
3.4 IICA flag register n (IICFn)................................................................................................................................. 696 
3.5 IICA control register n1 (IICCTLn1)................................................................................................................... 698 
3.6 IICA Low level width setting register n (IICWLn)................................................................................................ 700 
3.7 IICA High Level Width Setting Register n (IICWHn).......................................................................................... 700 
3.8 Port mode register x (PMx)................................................................................................................................ 701 
4 Functions of I2C bus mode.................................................................................................................................. 702 
4.1 pin structure....................................................................................................................................................... 702 
4.2 Method for setting transmission clock through IICWLn register and IICWHn register ....................................... 703 
5 Definition and control method of I2C bus............................................................................................................. 704 
5.1 Start Condition................................................................................................................................................... 704 
5.2 Address ............................................................................................................................................................. 705 
5.3 Assignment of transmission Direction................................................................................................................ 705 
5.4 Acknowledge (ACK) .......................................................................................................................................... 706 
5.5 stop condition .................................................................................................................................................... 707 
5.6 waiting ............................................................................................................................................................... 708 
5.7 Waitinging Release Method............................................................................................................................... 710 
5.8 Generation Timing and Waiting Control of Interrupt Request (INTIICAn).......................................................... 711 
5.9 Method for detecting address matching............................................................................................................. 712 
5.10 error detection ................................................................................................................................................... 712 
5.11 extension code .................................................................................................................................................. 713 
5.12 arbitration .......................................................................................................................................................... 714 
5.13 wake-up function ............................................................................................................................................... 716 
5.14 communication reservation................................................................................................................................ 719 
5.15 Other Precautions.............................................................................................................................................. 723 
5.16 communication operation .................................................................................................................................. 724 
5.17 I2C Generation Sequence of Interrupt Requests (INTIICAn)............................................................................. 732 
6 Timing diagram.................................................................................................................................................... 753 
Chapter 21 CAN Controller.................................................................................................. 769 
1 Summary Description .......................................................................................................................................... 769 
1.1 feature ............................................................................................................................................................... 769 
1.2 Functional Overview.......................................................................................................................................... 770 
1.3 configuration...................................................................................................................................................... 771 
2 CAN protocol ....................................................................................................................................................... 772 
2.1 frame format...................................................................................................................................................... 772 
2.2 Frame Type....................................................................................................................................................... 773 
2.3 data frames and remote frames......................................................................................................................... 773 
2.4 error frame......................................................................................................................................................... 780 

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2.5 overload frame................................................................................................................................................... 781 
3 Features............................................................................................................................................................... 782 
3.1 bus priority setting ............................................................................................................................................. 782 
3.2 bit filling ............................................................................................................................................................. 782 
3.3 multi-master....................................................................................................................................................... 782 
3.4 multicast ............................................................................................................................................................ 782 
3.5 CAN Sleep Mode/CAN Stop Mode Features..................................................................................................... 782 
3.6 error control function.......................................................................................................................................... 783 
3.7 baud rate control................................................................................................................................................ 788 
4 Connection to target system................................................................................................................................ 792 
5 Internal register for CAN controller ...................................................................................................................... 793 
5.1 CAN controller configuration.............................................................................................................................. 793 
5.2 register access type........................................................................................................................................... 795 
5.3 register bit configuration .................................................................................................................................... 804 
6 Bit Settings/Clean-up........................................................................................................................................... 808 
7 control register..................................................................................................................................................... 810 
8 CAN controller initialization.................................................................................................................................. 848 
8.1 CAN module initialization................................................................................................................................... 848 
8.2 Initialization of message cache.......................................................................................................................... 848 
8.3 Redefining message caching............................................................................................................................. 848 
8.4 Transition from initialization to operation ........................................................................................................... 849 
8.5 Reset CAN module error counter C0ERC ......................................................................................................... 850 
9 message receiving............................................................................................................................................... 851 
9.1 message receiving............................................................................................................................................. 851 
9.2 read received data............................................................................................................................................. 852 
9.3 Receive history list feature ................................................................................................................................ 853 
9.4 mask function .................................................................................................................................................... 855 
9.5 multi-buffer receive block function..................................................................................................................... 857 
9.6 remote frame receiving...................................................................................................................................... 858 
10 message sending................................................................................................................................................. 859 
10.1 message sending .............................................................................................................................................. 859 
10.2 Send History List Feature.................................................................................................................................. 861 
10.3 Automatic Block Transfer (ABT)........................................................................................................................ 863 
10.4 Transmission abort handling.............................................................................................................................. 864 
10.5 remote frame transmission................................................................................................................................ 865 
11 power saving mode.............................................................................................................................................. 866 
11.1 CAN sleep mode ............................................................................................................................................... 866 
11.2 CAN Stop Mode................................................................................................................................................. 868 
11.3 Power-saving mode........................................................................................................................................... 869 
12 interrupt function.................................................................................................................................................. 870 
13 Diagnostic features and special operation modes ............................................................................................... 871 
13.1 Receive only mode............................................................................................................................................ 871 
13.2 single-shot mode............................................................................................................................................... 872 
13.3 self-test mode.................................................................................................................................................... 873 

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13.4 Receive/Send Operation in Operation Mode..................................................................................................... 874 
14 timestamp function............................................................................................................................................... 875 
14.1 timestamp function ............................................................................................................................................ 875 
15 Baud rate setting.................................................................................................................................................. 877 
15.1 Baud rate setting ............................................................................................................................................... 877 
15.2 Representative example of baud rate setting.................................................................................................... 881 
16 Operation of CAN controller................................................................................................................................. 885 
Chapter 22 IrDA.................................................................................................................... 910 
1 Features of IrDA .................................................................................................................................................. 910 
2 Register controlling IrDA...................................................................................................................................... 911 
2.1 Peripheral Enable Register 0 (PER0s). ............................................................................................................. 911 
2.2 IrDA control register (IRCR)............................................................................................................................... 912 
3 Running of IrDA................................................................................................................................................... 913 
3.1 Procedures for IrDA Communication................................................................................................................. 913 
3.2 Send.................................................................................................................................................................. 914 
3.3 Receive ............................................................................................................................................................. 914 
3.4 Selection of high level pulse width..................................................................................................................... 915 
4 Precautions when using IrDA............................................................................................................................... 915 
Chapter 23 Enhanced DMA................................................................................................. 916 
1 The Function of DMA........................................................................................................................................... 916 
2 Structure of DMA................................................................................................................................................. 918 
3 Register for controlling DMA................................................................................................................................ 919 
3.1 DMA controls the allocation of data areas and DMA vector table areas............................................................ 920 
3.2 Controlling Data Allocation ................................................................................................................................ 921 
3.3 vector table........................................................................................................................................................ 923 
3.4 Peripheral Enable Register 1 (PER1)................................................................................................................ 925 
3.5 DMA control register j(DMACRj) (j=0~39). ........................................................................................................ 925 
3.6 DMA block size register j(DMBLSj) (j=0~39). .................................................................................................... 927 
3.7 DMA transfer times register j(DMACTj) (j=0~39)............................................................................................... 928 
3.8 DMA transfer times reload register j (DMRLDj) (j=0~39)................................................................................... 929 
3.9 DMA source address register j(DMSARj) (j=0~39)............................................................................................ 930 
3.10 DMA destination address register j(DMDARj) (j=0~39)..................................................................................... 930 
3.11 DMA Boot Enable Register i (DMAENi) (i=0~4)................................................................................................ 931 
3.12 DMA base address register (DMABAR) ............................................................................................................ 933 
4 Operation of DMA................................................................................................................................................ 934 
4.1 Boot Source....................................................................................................................................................... 934 
4.2 normal mode...................................................................................................................................................... 935 
4.3 repetition mode.................................................................................................................................................. 938 
4.4 chain transmission............................................................................................................................................. 942 
5 Precautionswhen using DMA............................................................................................................................... 944 
5.1 DMA control data and vector table settings....................................................................................................... 944 
5.2 DMA controls the allocation of data areas and DMA vector table areas............................................................ 944 
5.3 The number of execution clocks for DMA.......................................................................................................... 945 

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5.4 Response time for DMA .................................................................................................................................... 946 
5.5 Start Source for DMA ........................................................................................................................................ 946 
5.6 Operation in standby mode ............................................................................................................................... 947 
Chapter 24 Coordination Controller(EVENTC) .................................................................. 948 
1 Features of EVENTC........................................................................................................................................... 948 
2 Structure of EVENTC........................................................................................................................................... 948 
3 control register..................................................................................................................................................... 949 
3.1 Output target selection register n(ELSELRn) (n=00~21)................................................................................... 950 
4 Operation of EVENTC ......................................................................................................................................... 953 
Chapter 25 Interrupt function.............................................................................................. 955 
1 Types of interrupt functionality............................................................................................................................. 955 
2 interrupt source and structure.............................................................................................................................. 955 
3 Register for controlling interrupt function ............................................................................................................. 962 
3.1 interrupt request flag register (IF00~IF31)......................................................................................................... 962 
3.2 interrupt mask register (MK00~MK31)............................................................................................................... 963 
1.1 external interrupt rising edge permit register (EGP0, EGP1), external interrupt falling edge permit register 
(EGN0, EGN1)................................................................................................................................................... 966 
4 Operation of interrupt handling ............................................................................................................................ 968 
4.1 Acceptance of maskable interrupt requests....................................................................................................... 968 
4.2 Acceptance of Unmaskable Interrupt Request .................................................................................................. 968 
Chapter 26 key interrupt function....................................................................................... 969 
1 Function of key interrupt ...................................................................................................................................... 969 
2 Structure of key break.......................................................................................................................................... 969 
3 Register for controlling key interrupt .................................................................................................................... 971 
3.1 Key Return Mode Register (KRM)..................................................................................................................... 971 
3.2 Port Mode Register (PMx)................................................................................................................................. 972 
Chapter 27 standby function............................................................................................... 973 
1 standby function................................................................................................................................................... 973 
2 sleep mode.......................................................................................................................................................... 974 
2.1 Sleep mode configuration.................................................................................................................................. 974 
2.2 Exit from Sleep Mode ........................................................................................................................................ 979 
3 deep sleep mode................................................................................................................................................. 979 
3.1 deep sleep mode configuration.......................................................................................................................... 979 
3.2 Exist form Deep sleep mode.............................................................................................................................. 982 
Chapter 28 reset function.................................................................................................... 982 
1 Register which identifies reset source ................................................................................................................. 987 
1.1 Reset control flag register (RESF)..................................................................................................................... 987 
Chapter 29 Power-on reset circuit...................................................................................... 990 
1 Function of power-on reset circuit........................................................................................................................ 990 
2 Structure of power-on reset circuit....................................................................................................................... 991 
3 Operation of power-on reset circuit...................................................................................................................... 991 

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Chapter 30 voltage detection circuit .................................................................................. 995 
1 Function of Voltage Detection Circuit................................................................................................................... 995 
2 Structure of voltage detection circuit.................................................................................................................... 996 
3 Register for controlling voltage detection circuit................................................................................................... 997 
1.1 Voltage detection register (LVIM) ...................................................................................................................... 997 
3.1 Voltage detection level register (LVIS) .............................................................................................................. 998 
4 Operation of voltage detection circuit................................................................................................................. 1001 
4.1 Settings when used as reset mode.................................................................................................................. 1001 
4.2 Settings when used as interrupt mode ............................................................................................................ 1003 
4.3 Settings when used as interrupt & reset mode................................................................................................ 1005 
2 Precautions for Voltage Detection Circuits......................................................................................................... 1011 
Chapter 31 Safety function................................................................................................ 1013 
1 Summary of Safety Features............................................................................................................................. 1013 
2 Register used by Safety function....................................................................................................................... 1014 
3 Operation of Safety functions............................................................................................................................. 1014 
3.1 Flash CRC Operation Function (High Speed CRC)......................................................................................... 1014 
3.1.1Flash CRC control register (CRC0CTL) ........................................................................................................ 1015 
3.1.2flash CRC operation result register (PGCRCL)............................................................................................. 1016 
3.2 CRC Operation Function (Universal CRC) ...................................................................................................... 1018 
3.2.1CRC input register (CRCIN).......................................................................................................................... 1018 
3.2.2CRC Data Register (CRCD).......................................................................................................................... 1019 
3.3 RAM Parity Error Detection ............................................................................................................................. 1020 
3.3.1RAM parity error control register (RPECTL).................................................................................................. 1020 
3.4 SFR Protection Features................................................................................................................................. 1022 
3.4.1SFR Protection Control Register (SFRGD)................................................................................................... 1022 
3.5 frequency detection function............................................................................................................................ 1023 
3.5.1Timer Input Select Register 0 (TIS0)............................................................................................................. 1023 
3.6 A/D Test Function............................................................................................................................................ 1024 
3.6.1A/D test register (ADTES)............................................................................................................................. 1026 
3.6.2Analog input channel assignment register (ADS).......................................................................................... 1026 
3.7 Digital output signal level detection function of input/output pin ...................................................................... 1027 
3.7.1Port mode selection register (PMS)............................................................................................................... 1027 
3.8 Product Unique Identity Register..................................................................................................................... 1028 
Chapter 32 temperature sensor........................................................................................ 1029 
1 Function of temperature sensor......................................................................................................................... 1029 
2 Register for temperature sensor........................................................................................................................ 1029 
2.1 temperature sensor calibration data register TSN25....................................................................................... 1029 
2.2 temperature sensor calibration data register TSN85....................................................................................... 1029 
3 Instructions for Using a Temperature Sensor .................................................................................................... 1030 
3.1 Principle of Using Temperature Sensor........................................................................................................... 1030 
3.2 Method for using temperature sensor.............................................................................................................. 1031 
Chapter 33 Option Bytes................................................................................................... 1032 

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1 Feature of option bytes...................................................................................................................................... 1032 
1.1 User Option Bytes (000C0H~000C2H/010C0H~010C2H) .............................................................................. 1032 
1.2 Flash Data Protection Option Bytes (000C3H/010C3H,50004H~500005H).................................................... 1034 
2 Format of user option bytes............................................................................................................................... 1035 
3 Format of Flash Data Protection Option bytes................................................................................................... 1041 
Chapter 34 FLASH control ................................................................................................ 1042 
1 FLASH Control Feature Description .................................................................................................................. 1042 
2 FLASH memory structure .................................................................................................................................. 1042 
3 Register controlling FLASH................................................................................................................................ 1043 
3.1 Flash write protection register (FLPROT)........................................................................................................ 1043 
3.2 FLASH Operation Control Register (FLOPMD1, FLOPMD2) .......................................................................... 1044 
3.3 Flash erase control register (FLERMD)........................................................................................................... 1045 
3.4 Flash Status Register (FLSTS)........................................................................................................................ 1046 
3.5 Flash Full Slice Erase Time Control Register (FLCERCNT)............................................................................ 1046 
3.6 Flash Page Erase Time Control Register (FLSERCNT).................................................................................. 1047 
3.7 Flash write time control register (FLPROCNT)................................................................................................ 1048 
4 FLASH operation method .................................................................................................................................. 1049 
4.1 Page Erase (sector erase)............................................................................................................................... 1049 
4.2 Full Chip Erase (chip erase)............................................................................................................................ 1050 
4.3 Programming (word program).......................................................................................................................... 1050 
1 flash read........................................................................................................................................................... 1051 
2 Precautions for FLASH Operations.................................................................................................................... 1051 
Appendix Revision Records................................................................................................ 1052 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Chapter 1 CPU

1.1 verview

This Chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+

kernel on which this product is built. Please refer to the ARM documentation for details.

1.2 Cortex-M0+ core features

⚫ARM Cortex-M0+ processors are 32-bit RISC cores with a 2-stage pipeline that supports privileged and

user modes

⚫Memory Protection Units (MPUs) support 8 separate Zone (region) protection

⚫single cycle hardware multiplier

⚫Nested Vector Interrupt Controller (NVIC)

◼1 Unshielded Interrupt (NMI)

◼Supports 32 Masking Interrupt Requests (IRQs)

◼4 interrupt priority

⚫The system timer SysTick is a 24-bit countdown timer that can be selected for fCLK or fIL count clocks

⚫vector table offset register (VTOR)

◼The software can write VTOR to relocate the start address of the vector table to a different location

◼The default value for this register is 0x0000_0000, with low 8-bit write ignore, read to zero, that is,

offset 256 bytes aligned

1.3 Debug features

⚫2-wire SWD debug interface

⚫Support for pausing, resuming, and single-step execution procedures

⚫Access processor's kernel register and special function register

⚫4 Hardware Breakpoints (BPUs)

⚫Unlimited software breakpoints (BKPT instruction)

⚫2 data observation points (DWT)

⚫Access memory during kernel execution

⚫Micro Trace Cache (MTB) provides a simple instruction execution trace scheme

- MTB shared with user SRAM (0x2000_0000-0x2000_2 FFF zone)

- The base address of the MTB control register is 0x4001_9000

Table of contents

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