Cmsemicon CMS80F751 Series User manual

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CMS80F661x 数据手册
CMS80F751x Reference Manual
Enhanced Flash 8-bit 1T 8051- Microcontroller
Rev. 1.05
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CMS80F751x Reference Manual
Contents
CMS80F751x Reference Manual .............................................................................................1
Contents ...................................................................................................................................2
1. Central Processing Unit（CPU）...................................................................................13
1.1 Reset Vector（0000H）............................................................................................................................................13
1.2 BOOT Partition ..........................................................................................................................................................13
1.3 Accumulator（ACC）................................................................................................................................................15
1.4 B Register（B）........................................................................................................................................................15
1.5 Stack Pointer Register（SP）...................................................................................................................................15
1.6 Data Pointer Register（DPTR0/DPTR1）.................................................................................................................15
1.7 Data Pointer Selection Register（DPS）..................................................................................................................16
1.8 Program Status Register（PSW）............................................................................................................................16
1.9 Program Counter（PC）...........................................................................................................................................17
1.10 Timing Access Register（TA）..................................................................................................................................17
2. Memory And Register Map..............................................................................................18
2.1 Program Memory FLASH ..........................................................................................................................................18
2.2 Non-volatile Data Memory Data FLASH....................................................................................................................19
2.3 General Data Register RAM......................................................................................................................................20
2.4 General External Data Register XRAM .....................................................................................................................22
2.5 Special Function Register Table SFR........................................................................................................................23
2.6 External Special Function Register XSFR.................................................................................................................25
3. Reset.................................................................................................................................33
3.1 Power-On Reset........................................................................................................................................................33
3.2 External Reset...........................................................................................................................................................35
3.3 LVR Low Voltage Reset.............................................................................................................................................35
3.4 Watchdog Reset (WDT) ............................................................................................................................................36
3.5 Software Reset..........................................................................................................................................................37
3.6 CONFIG Status Protection Reset..............................................................................................................................37
3.7 Power-On Configuration Monitoring Reset................................................................................................................37
4. Clock Structure ................................................................................................................38
4.1 System Clock Structure.............................................................................................................................................38
4.2Related registers .......................................................................................................................................................39
4.2.1 Oscillator Control Register CLKDIV ......................................................................................................................39
4.2.2 System Clock Switch Register SCKSEL ...............................................................................................................39
4.2.3 System Clock Status Register SCKSTAU .............................................................................................................40
4.2.4 System Clock Monitor Register SCM ....................................................................................................................41
4.2.5 Function Clock Control Register............................................................................................................................42
4.3 System Clock Switching ............................................................................................................................................44
4.4 System Clock Monitoring...........................................................................................................................................45
5. Power Management .........................................................................................................46
5.1 Power Management Register PCON.........................................................................................................................46
5.2 Power Monitoring Register LVDCON ........................................................................................................................47
5.3 IDLE Mode ................................................................................................................................................................47
5.4 STOP Sleep Mode.....................................................................................................................................................48

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5.4.1 Sleep And Wake-Up..............................................................................................................................................48
5.4.2 Wake Waiting Status .............................................................................................................................................48
5.4.3 Sleep And Wake-Up Time .....................................................................................................................................49
5.4.4 Reset Operation During Sleep ..............................................................................................................................49
5.4.5 Sleep Power Consumption In Debug Mode ..........................................................................................................49
5.4.6 Sleep Mode Application Example..........................................................................................................................50
6. Interrupt ............................................................................................................................51
6.1 Interruption Overview ................................................................................................................................................51
6.2 External Interruption ..................................................................................................................................................52
6.2.1 INT0/INT1 Interruption ..........................................................................................................................................52
6.2.2 GPIO Interruption ..................................................................................................................................................52
6.3 Interruption And Wake-Up From Sleep......................................................................................................................52
6.4 Interruption Register..................................................................................................................................................53
6.4.1 Interruption Mask Register ....................................................................................................................................53
6.4.1.1 Interruption Mask Register IE .......................................................................................................................53
6.4.1.2 Interruption Mask Register EIE2 ...................................................................................................................54
6.4.1.3 Timer2 Interruption Mask Register T2IE .......................................................................................................55
6.4.1.4 P0 Port Interrupt Control Register P0EXTIE .................................................................................................55
6.4.1.5 P1 Port Interrupt Control Register P1EXTIE .................................................................................................56
6.4.1.6 P2 Port Interrupt Control Register P2EXTIE .................................................................................................56
6.4.1.7 P5 Port Interrupt Control Register P5EXTIE .................................................................................................56
6.4.2 Interrupt Priority Control Register..........................................................................................................................57
6.4.2.1 Interrupt Priority Control Register IP .............................................................................................................57
6.4.2.2 Interrupt Priority Control Register EIP1.........................................................................................................58
6.4.2.3 Interrupt Priority Control Register EIP2.........................................................................................................58
6.4.2.4 Interrupt Priority Control Register EIP3.........................................................................................................59
6.4.3 Interrupt Flag Bit Register .....................................................................................................................................60
6.4.3.1 Timer0/1、INT0/1 Interrupt Flag Bit Register TCON.....................................................................................60
6.4.3.2 Timer2 Interrupt Flag Bit Register T2IF.........................................................................................................61
6.4.3.3 External Interrupt Flag Bit Register EIF2 ......................................................................................................61
6.4.3.4 SPI Interrupt Flag Bit Register SPSR............................................................................................................62
6.4.3.5 I2C Master Mode Interrupt Flag Bit Register I2CMCR/I2CMSR ...................................................................63
6.4.3.6 I2C Slave Mode Status Register I2CSSR .....................................................................................................63
6.4.3.7 UART Control Register SCONn ....................................................................................................................64
6.4.3.8 P0 Interrupt Flag Bit Register P0EXTIF ........................................................................................................64
6.4.3.9 P1 Interrupt Flag Bit Register P1EXTIF ........................................................................................................64
6.4.3.10 P2 Interrupt Flag Bit Register P2EXTIF ....................................................................................................65
6.4.3.11 P5 Interrupt Flag Bit Register P5EXTIF ....................................................................................................65
6.4.4 Clear Operation Of Interrupt Flag..........................................................................................................................66
6.4.5 Special Interrupt Flag Bits In Debug Mode............................................................................................................67
7. I/O Port..............................................................................................................................68
7.1 GPIO Function...........................................................................................................................................................68
7.1.1 PORTx Data Register Px ......................................................................................................................................68
7.1.2 PORTx Direction Register PxTRIS........................................................................................................................69
7.1.3 PORTx Open Drain Control Register PxOD..........................................................................................................69
7.1.4 PORTx Pull-up Resistor Control Register PxUP ...................................................................................................69
7.1.5 PORTx Pull-Down Resistor Control Register PxRD..............................................................................................70
7.1.6 PORTx Slope Control Register PxSR ...................................................................................................................70
7.1.7 PORTx Data Input Selection Register PxDS.........................................................................................................70
7.2 Reuse Function .........................................................................................................................................................71
7.2.1 Port Reuse Function Table ....................................................................................................................................71

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7.2.2 Port Reuse Function Configuration Register .........................................................................................................73
7.2.3 Port Input Function Allocation Register .................................................................................................................74
7.2.4 Communication Input Function Allocation Register ...............................................................................................76
7.2.5 External Port Interrupt Control Register ................................................................................................................77
7.2.6 Reuse Functions Application Notes.......................................................................................................................78
8. Watchdog Timer（WDT）................................................................................................79
8.1 Overview ...................................................................................................................................................................79
8.2 Related Register........................................................................................................................................................79
8.2.1 Watchdog Control Register WDCON ....................................................................................................................79
8.2.2 Watchdog Overflow Control Register CKCON ......................................................................................................80
8.3 WDT Interrupt............................................................................................................................................................81
8.3.1 Interruption Mask Register EIE2 ...........................................................................................................................81
8.3.2 Interrupt Priority Control Register EIP2 .................................................................................................................82
9. Timer 0/1（Timer0/1）.....................................................................................................83
9.1 Overview ...................................................................................................................................................................83
9.2 Related Register........................................................................................................................................................84
9.2.1 Timer0/1 Mode Register TMOD ............................................................................................................................84
9.2.2 Timer0/1 Control Register TCON ..........................................................................................................................85
9.2.3 Timer0 Low Bit Data Register TL0 ........................................................................................................................86
9.2.4 Timer0 High Bit Data Register TH0 .......................................................................................................................86
9.2.5 Timer1 Low Bit Data Register TL1 ........................................................................................................................86
9.2.6 Timer1 High Bit Data Register TH1 .......................................................................................................................86
9.2.7 Function Clock Control Register CKCON..............................................................................................................87
9.3 Timer0/1 Interrupt......................................................................................................................................................88
9.3.1 Interruption Mask Register IE................................................................................................................................88
9.3.2 Interrupt Priority Control Register IP .....................................................................................................................89
9.3.3 Timer0/1、INT0/1 Interrupt Flag Register TCON ..................................................................................................90
9.4 Timer0 Operating Mode.............................................................................................................................................91
9.4.1 T0 -Mode0（13-Bit Timing/Counting Mode）........................................................................................................91
9.4.2 T0 -Mode1（16-Bit Timing/Counting Mode）........................................................................................................91
9.4.3 T0 -Mode2（8-Bit Auto Reload Timing/Counting Mode）.....................................................................................92
9.4.4 T0 -Mode3（Two Separate 8-Bit Timer/Counters）..............................................................................................93
9.5 Timer1 Operating Mode.............................................................................................................................................94
9.5.1 T1 -Mode0（13-Bit Timing/Counting Mode）........................................................................................................94
9.5.2 T1 -Mode1（16-Bit Timing/Counting Mode）........................................................................................................94
9.5.3 T1 -Mode2（8-Bit Auto Reload Timing/Counting Mode）.....................................................................................95
9.5.4 T1 -Mode3（Stop Counting）...............................................................................................................................95
10. Timer 2（Timer2）...........................................................................................................96
10.1 Overview ...................................................................................................................................................................96
10.2 Related Register........................................................................................................................................................97
10.2.1 Timer2 Control Register T2CON ...........................................................................................................................97
10.2.2 Timer2 Low Bit Data Register TL2 ........................................................................................................................98
10.2.3 Timer2 High Bit Data Register TH2 .......................................................................................................................98
10.2.4 Timer2 Compare/Capture/Reload Register Low 8-Bit RLDL .................................................................................98
10.2.5 Timer2 Compare/Capture/Reload Register High 8-Bit RLDH................................................................................98
10.2.6 Timer2 Compare/Capture Channel1 Register Low 8-Bit CCL1 .............................................................................99

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10.2.7 Timer2 Compare/Capture Channel1 Register High 8-Bit CCH1............................................................................99
10.2.8 Timer2 Compare/Capture Channel2 Register Low 8-Bit CCL2 .............................................................................99
10.2.9 Timer2 Compare/Capture Channel2 Register High 8-Bit CCH2............................................................................99
10.2.10 Timer2 Compare/Capture Channel3 Register Low 8-Bit CCL3 .............................................................................99
10.2.11 Timer2 Compare/Capture Channel3 Register High 8-Bit CCH3..........................................................................100
10.2.12 Timer2 Compare Capture Control Register CCEN..............................................................................................100
10.3 Timer2 Interrupt.......................................................................................................................................................101
10.3.1 Interrupt Related Register ...................................................................................................................................101
10.3.1.1 Interrupt Mask Register IE ......................................................................................................................101
10.3.1.2 Timer2 Interrupt Mask Register T2IE ......................................................................................................102
10.3.1.3 Interrupt Priority Control Register IP .......................................................................................................103
10.3.1.4 Timer2 Interrupt Flag Register T2IF........................................................................................................104
10.3.2 Timer Interrupt.....................................................................................................................................................105
10.3.3 External Trigger Interrupt ....................................................................................................................................105
10.3.4 Compare Interrupt ...............................................................................................................................................105
10.3.5 Capture Interrupt .................................................................................................................................................105
10.4 Timer2 Function Description....................................................................................................................................106
10.4.1 Timing Mode .......................................................................................................................................................106
10.4.2 Reload Mode.......................................................................................................................................................106
10.4.3 Gate Control Timing Mode ..................................................................................................................................107
10.4.4 Event Counting Mode..........................................................................................................................................107
10.4.5 Compare Mode ...................................................................................................................................................107
10.4.5.1 Compare Mode0 .....................................................................................................................................108
10.4.5.2 Compare Mode1.....................................................................................................................................109
10.4.6 Capture Mode .....................................................................................................................................................110
10.4.6.1 Capture Mode0.......................................................................................................................................110
10.4.6.2 Capture Mode1....................................................................................................................................... 111
11. Timer 3/4（Timer3/4）................................................................................................... 112
11.1 Overview .................................................................................................................................................................112
11.2 Related Register......................................................................................................................................................113
11.2.1 Timer3/4 Control Register T34MOD....................................................................................................................113
11.2.2 Timer3 Low Bit Data Register TL3 ......................................................................................................................113
11.2.3 Timer3 High Bit Data Register TH3 .....................................................................................................................114
11.2.4 Timer4 Low Bit Data Register TL4 ......................................................................................................................114
11.2.5 Timer4 High Bit Data Register TH4 .....................................................................................................................114
11.3 Timer3/4 Interrupt....................................................................................................................................................115
11.3.1 Interrupt Mask Register EIE2 ..............................................................................................................................115
11.3.2 Interrupt Priority Control Register EIP2 ...............................................................................................................116
11.3.3 External Interrupt Flag Bit Register EIF2.............................................................................................................117
11.4 Timer3 Operation Mode...........................................................................................................................................118
11.4.1 T3 -Mode0（13-Bit Timing Mode）.....................................................................................................................118
11.4.2 T3 -Mode1（16-Bit Timing Mode）.....................................................................................................................118
11.4.3 T3 -Mode2（8-Bit Auto Reload Timing Mode）..................................................................................................119
11.4.4 T3 -Mode3（Two Separate 8-Bit Timer）...........................................................................................................120
11.5 Timer4 Operation Mode...........................................................................................................................................121
11.5.1 T4 -Mode0（13-Bit Timing Mode）.....................................................................................................................121
11.5.2 T4 -Mode1（16-Bit Timing Mode）.....................................................................................................................121
11.5.3 T4- Mode2（8-Bit Auto Reload Timing Mode）..................................................................................................122
11.5.4 T4- Mode3（Stop Counting）.............................................................................................................................122

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12. LSE_Timer ......................................................................................................................123
12.1 Overview .................................................................................................................................................................123
12.2 Related Registers....................................................................................................................................................123
12.2.1 LSE Timer Data Register Low 8-bit LSECRL ......................................................................................................123
12.2.2 LSE Timer Data Register High 8-bit LSECRH.....................................................................................................123
12.2.3 LSE Timer Control Register LSECON .................................................................................................................124
12.3 Interrupt And Sleep Wake-up ..................................................................................................................................125
12.4 Function Description................................................................................................................................................125
13. Wake-Up Timer（WUT）................................................................................................126
13.1 Overview .................................................................................................................................................................126
13.2 Related Registers....................................................................................................................................................126
13.2.1 WUTCRH Register..............................................................................................................................................126
13.2.2 WUTCRL Register...............................................................................................................................................126
13.3 Function Description................................................................................................................................................127
14. Baud Rate Timer（BRT）..............................................................................................128
14.1 Overview .................................................................................................................................................................128
14.2 Related Registers....................................................................................................................................................128
14.2.1 BRT Module Control Register BRTCON .............................................................................................................128
14.2.2 BRT Timer Data Is Loading The Low 8-bit Register BRTDL................................................................................128
14.2.3 BRT Timer Data Is Loading The High 8-bit Register BRTDH ..............................................................................129
14.3 Function Description................................................................................................................................................129
15. Cycle Redundancy Check（CRC）..............................................................................130
15.1 Overview .................................................................................................................................................................130
15.2 Related Registers....................................................................................................................................................130
15.2.1 CRC Data Input Register CRCIN ........................................................................................................................130
15.2.2 CRC Operation Result Low 8-bit Data Register CRCDL.....................................................................................130
15.2.3 CRC Operation Result High 8-bit Data Register CRCDH ...................................................................................130
15.3 Function Description................................................................................................................................................131
16. Multiplication/Division Unit（MDU）............................................................................132
16.1 Overview .................................................................................................................................................................132
16.2 Related Registers....................................................................................................................................................132
16.2.1 Operation Register MD0 .....................................................................................................................................133
16.2.2 Operation Register MD1 .....................................................................................................................................133
16.2.3 Operation Register MD2 .....................................................................................................................................134
16.2.4 Operation Register MD3 .....................................................................................................................................134
16.2.5 Operation Register MD4 .....................................................................................................................................134
16.2.6 Operation Register MD5 .....................................................................................................................................135
16.2.7 Operation Register ARCON ................................................................................................................................135
16.3 Function Description................................................................................................................................................136
16.3.1 32bit/16bit Division Operation .............................................................................................................................137
16.3.2 16bit/16bit Division Operation .............................................................................................................................137
16.3.3 16bit*16bit Multiplication Operation.....................................................................................................................138
16.3.4 32bit Shift Operation ...........................................................................................................................................138
16.3.5 32bit Normalization Operation.............................................................................................................................139
17. BUZZER ..........................................................................................................................140
17.1 Overview .................................................................................................................................................................140
17.2 Related Registers....................................................................................................................................................140

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17.2.1 BUZZER Control Register BUZCON...................................................................................................................140
17.2.2 BUZZER Frequency Control Register BUZDIV ...................................................................................................140
17.3 Function Description................................................................................................................................................141
18. Enhanced PWM Module ................................................................................................142
18.1 Overview .................................................................................................................................................................142
18.2 Characteristic ..........................................................................................................................................................142
18.3 Pin Configuration.....................................................................................................................................................143
18.4 Function Description................................................................................................................................................143
18.4.1 Functional Diagram .............................................................................................................................................143
18.4.2 Edge-aligned .......................................................................................................................................................144
18.4.3 Center-aligned.....................................................................................................................................................145
18.4.3.1 Symmetric counting ................................................................................................................................145
18.4.3.2 Asymmetric counting ..............................................................................................................................146
18.4.4 Complementary Mode.........................................................................................................................................148
18.4.5 Synchronize Mode ..............................................................................................................................................149
18.4.6 Mask Output........................................................................................................................................................149
18.4.7 Brake Function ....................................................................................................................................................149
18.5 PWM Related Registers ..........................................................................................................................................150
18.5.1 PWM Control Register PWMCON.......................................................................................................................150
18.5.2 PWM Output Enable Control Register PWMOE..................................................................................................150
18.5.3 PWM0/1 Clock Prescaler Control Register PWM01PSC ....................................................................................151
18.5.4 PWM2/3 Clock Prescaler Control Register PWM23PSC ....................................................................................151
18.5.5 PWM4/5 Clock Prescaler Control Register PWM45PSC ....................................................................................152
18.5.6 PWM Clock Division Control Register PWMnDIV(n=0-5)....................................................................................152
18.5.7 PWM Data load Enable Control Register PWMLOADEN....................................................................................152
18.5.8 PWM Output Polarity Control Register PWMPINV..............................................................................................153
18.5.9 PWM Counter Mode Control Register PWMCNTM.............................................................................................153
18.5.10 PWM Counter Enable Control Register PWMCNTE ...........................................................................................153
18.5.11 PWM Counter Mode Control Register PWMCNTCLR.........................................................................................154
18.5.12 PWM Period Data Low 8-bit Register PWMPnL (n=0-5) .....................................................................................154
18.5.13 PWM Period Data High 8-bit Register PWMPnH (n=0-5)....................................................................................154
18.5.14 PWM Compare Data Low 8-bit Register PWMDnL (n=0-5).................................................................................154
18.5.15 PWM Compare Data High 8-bit Register PWMDnH (n=0-5) ...............................................................................155
18.5.16 PWM Compare Data Low 8-bit Registers Down PWMDDnL (n=0-5) ..................................................................155
18.5.17 PWM Compare Data High 8-bit Registers Down PWMDDnH (n=0-5).................................................................155
18.5.18 PWM Dead Zone Enable Control Register PWMDTE.........................................................................................155
18.5.19 PWM0/1 Dead Zone Delay Data Register PWM01DT ........................................................................................156
18.5.20 PWM2/3 Dead Zone Delay Data Register PWM23DT ........................................................................................156
18.5.21 PWM4/5 Dead Zone Delay Data Register PWM45DT ........................................................................................156
18.5.22 PWM Mask Control Register PWMMASKE.........................................................................................................156
18.5.23 PWM Mask Data Register PWMMASKD.............................................................................................................157
18.5.24 PWM Brake Control Register PWMFBKC...........................................................................................................157
18.5.25 PWM Brake Data Register PWMFBKD...............................................................................................................158
18.6 PWM Interrupt .........................................................................................................................................................159
18.6.1 Interruption Mask Register EIE2 .........................................................................................................................159
18.6.2 Interrupt Priority Control Register EIP2 ...............................................................................................................160
18.6.3 PWM Period Interrupt Mask Register PWMPIE ..................................................................................................160
18.6.4 PWM Zero Interrupt Mask Register PWMZIE......................................................................................................161
18.6.5 PWM Up Compare Interrupt Mask Register PWMUIE ........................................................................................161
18.6.6 PWM Down Compare Interrupt Mask Register PWMDIE....................................................................................161
18.6.7 PWM Period Interrupt Flag Register PWMPIF ....................................................................................................161
18.6.8 PWM Zero Interrupt Flag Register PWMZIF .......................................................................................................162

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18.6.9 PWM Up Compare Interrupt Flag Register PWMUIF ..........................................................................................162
18.6.10 PWM Down Compare Interrupt Flag Register PWMDIF .....................................................................................162
19. Hardware LCD Driver.....................................................................................................163
19.1 Overview .................................................................................................................................................................163
19.2 Characteristic ..........................................................................................................................................................163
19.3 Related Register......................................................................................................................................................164
19.3.1 LCD Control Register LCDCON0 ........................................................................................................................164
19.3.2 LCD Control Register LCDCON1 ........................................................................................................................165
19.3.3 LCD Control Register LCDCON2 ........................................................................................................................165
19.3.4 LCD Control Register LCDCON3 ........................................................................................................................166
19.3.5 COM Port Enable Control Register LCDCOMEN................................................................................................166
19.3.6 SEG Port Enable Control Register LCDSEGEN0 ...............................................................................................167
19.3.7 SEG Port Enable Control Register LCDSEGEN1 ...............................................................................................167
19.3.8 SEG Port Enable Control Register LCDSEGEN2 ...............................................................................................167
19.3.9 SEG Data Register 6(n=0-19) .............................................................................................................................167
19.4 COM -SEG data-sheet ............................................................................................................................................168
19.4.1 1/4DUTY .............................................................................................................................................................168
19.4.2 1/5DUTY .............................................................................................................................................................169
19.4.3 1/6DUTY .............................................................................................................................................................170
19.4.4 1/8DUTY .............................................................................................................................................................171
20. Hardware LED Driver.....................................................................................................172
20.1 Overview .................................................................................................................................................................172
20.2 Characteristic ..........................................................................................................................................................172
20.3 Related Register......................................................................................................................................................172
20.3.1 LED Control Register LEDCON ..........................................................................................................................172
20.3.2 LED Clock Prescaler Data Register Low 8-bit LEDCLKL....................................................................................173
20.3.3 LED Clock Prescaler Data Register High 8-bit LEDCLKH ..................................................................................173
20.3.4 COM Port Effective Time Selection Register LEDCOMTIME..............................................................................173
20.3.5 COM Port Enable Control Register LEDCOMEN ................................................................................................174
20.3.6 SEG Port Enable Control Register LEDSEGEN0................................................................................................174
20.3.7 SEG Port Enable Control Register LEDSEGEN1................................................................................................174
20.3.8 SEG Port Enable Control Register LEDSEGEN2................................................................................................174
20.3.9 COM0 Corresponds To SEG Data Register LEDC0DATAn（n=0-2）................................................................175
20.3.10 COM1 Corresponds To SEG Data Register LEDC1DATAn（n=0-2）................................................................175
20.3.11 COM2 Corresponds To SEG Data Register LEDC2DATAn（n=0-2）................................................................176
20.3.12 COM3 Corresponds To SEG Data Register LEDC3DATAn（n=0-2）................................................................176
20.3.13 COM4 Corresponds To SEG Data Register LEDC4DATAn（n=0-2）................................................................177
20.3.14 COM5 Corresponds To SEG Data Register LEDC5DATAn（n=0-2）................................................................177
20.3.15 COM6 Corresponds To SEG Data Register LEDC6DATAn（n=0-2）................................................................178
20.3.16 COM7 Corresponds To SEG Data Register LEDC7DATAn（n=0-2）................................................................178
20.3.17 SEG Port P04-P07 Drive Current Control Register LEDSDRP0H.......................................................................179
20.3.18 SEG Port P10-P13 Drive Current Control Register LEDSDRP1L .......................................................................179
20.3.19 SEG Port P14-P17 Drive Current Control Register LEDSDRP1H.......................................................................180
20.3.20 SEG Port P20-P23 Drive Current Control Register LEDSDRP2L .......................................................................180
20.3.21 SEG Port P24-P27 Drive Current Control Register LEDSDRP2H.......................................................................181
20.3.22 COM Port Current Sink Selection Register P0DR...............................................................................................182
20.4 LED Driver Output Waveform..................................................................................................................................183
21. SPI...................................................................................................................................184

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21.1 Overview .................................................................................................................................................................184
21.2 SPI Port Configuration.............................................................................................................................................185
21.3 SPI Hardware Description .......................................................................................................................................186
21.4 SPI Related Register...............................................................................................................................................187
21.4.1 SPI Control Register SPCR.................................................................................................................................187
21.4.2 SPI Data Register SPDR ....................................................................................................................................188
21.4.3 Slave Select Control Register SSCR ..................................................................................................................188
21.4.4 SPI State Register SPSR ....................................................................................................................................189
21.5 SPI Master Model....................................................................................................................................................190
21.5.1 Write Collision Error ............................................................................................................................................191
21.6 SPI Slave Mode.......................................................................................................................................................192
21.6.1 Addressed Error ..................................................................................................................................................192
21.6.2 Write Collision Error ............................................................................................................................................192
21.7 SPI Clock Control Logic ..........................................................................................................................................194
21.7.1 SPI Clock Phase And Polarity Control.................................................................................................................194
21.7.2 SPI Transport Format..........................................................................................................................................194
21.7.3 CPHA=0 Transport Format..................................................................................................................................194
21.7.4 CPHA=1 Transport Format..................................................................................................................................195
21.8 SPI Data Transmission............................................................................................................................................196
21.8.1 SPI Transfer Start................................................................................................................................................196
21.8.2 SPI Transfer End.................................................................................................................................................196
21.9 SPI Timing Diagram ................................................................................................................................................197
21.9.1 Master Mode Transmission .................................................................................................................................197
21.9.2 Slave Mode Transmission ...................................................................................................................................197
21.10 SPI Interrupt ............................................................................................................................................................198
21.10.1 Interrupt Mask Register EIE2 ..............................................................................................................................198
21.10.2 Interrupt Priority Control Register EIP2 ...............................................................................................................199
21.10.3 Peripheral Interrupt Flag Register EIF2...............................................................................................................200
22. I2C Module ......................................................................................................................201
22.1 Overview .................................................................................................................................................................201
22.2 I2C Port Configuration..............................................................................................................................................202
22.3 I2C Master Mode .....................................................................................................................................................202
22.3.1 I2C Period Timer Register In Master Mode..........................................................................................................203
22.3.2 I2C Control And Status Register In Master Mode ................................................................................................203
22.3.3 I2C Slave Address Register .................................................................................................................................206
22.3.4 Sending And Receiving Data Register In I2C Master Control Mode ....................................................................206
22.4 I2C Slave Mode .......................................................................................................................................................207
22.4.1 I2C Own Address Register I2CSADR ..................................................................................................................207
22.4.2 I2C Control Register And Status Register Of I2C Slave Mode I2CSCR/I2CSSR .................................................207
22.4.3 Sending And Receiving Cached Register Of I2C Slave Mode I2CSBUF.............................................................208
22.5 I2C interrupt .............................................................................................................................................................209
22.5.1 Interrupt Mask Register EIE2 ..............................................................................................................................209
22.5.2 Interrupt Priority Control Register EIP2 ...............................................................................................................210
22.5.3 Peripheral Interrupt Flag Register EIF2...............................................................................................................211
22.6 I2C Transmission Method of Slave Mode.................................................................................................................212
22.6.1 Single Receiving .................................................................................................................................................212
22.6.2 Single Sending ....................................................................................................................................................212
22.6.3 Continuous Receiving .........................................................................................................................................213
22.6.4 Continuous Sending............................................................................................................................................213
23. UARTn Moudle ...............................................................................................................214
23.1 Overview .................................................................................................................................................................214

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23.2 UARTn Port Configuration.......................................................................................................................................214
23.3 UARTn Baud Rate...................................................................................................................................................215
23.3.1 Baud Rate Clock Source .....................................................................................................................................215
23.3.2 Baud Rate Calculation ........................................................................................................................................215
23.3.3 Baud Rate Deviation ...........................................................................................................................................216
23.4 UARTn Registers ....................................................................................................................................................218
23.4.1 UART0/1 Baud Rate Selection Register FUNCCR .............................................................................................218
23.4.2 UARTn Buffer Register SBUFn ...........................................................................................................................218
23.4.3 UART Control Register SCONn ..........................................................................................................................219
23.4.4 PCON Register ...................................................................................................................................................220
23.5 UARTn Interrupt ......................................................................................................................................................221
23.5.1 Interrupt Mask Register IE...................................................................................................................................221
23.5.2 Interrupt Priority Control Register IP ...................................................................................................................222
23.5.3 Interrupt Priority Control Register EIP3 ...............................................................................................................223
23.6 UARTn Mode...........................................................................................................................................................224
23.6.1 Mode 0 - Synchronous Mode..............................................................................................................................224
23.6.2 Mode 1 - 8-bit Asynchronous Mode (Variable Baud Rate)..................................................................................224
23.6.3 Mode 2 - 9-bit Asynchronous Mode (Fixed Baud Rate) ......................................................................................225
23.6.4 Mode 3 - 9-bit Asynchronous Mode (Variable Baud Rate)..................................................................................225
24. Analog To Digital Conversion (ADC)............................................................................226
24.1 Overview .................................................................................................................................................................226
24.2 ADC Configuration ..................................................................................................................................................227
24.2.1 Port Configuration ...............................................................................................................................................227
24.2.2 Channel Selection ...............................................................................................................................................227
24.2.3 ADC Reference Voltage ......................................................................................................................................227
24.2.4 Conversion Clock ................................................................................................................................................228
24.2.5 Result Formatting................................................................................................................................................228
24.3 ADC Hardware Triggered Start................................................................................................................................229
24.3.1 External Port Edge Trigger ADC..........................................................................................................................229
24.3.2 PWM Triggered ADC...........................................................................................................................................229
24.3.3 Hardware Trigger Delay Before Starting .............................................................................................................229
24.4 ADC Results Of Comparison...................................................................................................................................230
24.5 ADC Working Principle............................................................................................................................................230
24.5.1 Start Conversion .................................................................................................................................................230
24.5.2 Complete Conversion..........................................................................................................................................230
24.5.3 Terminate Conversion .........................................................................................................................................230
24.5.4 A/D Conversion Step...........................................................................................................................................231
24.5.5 Enter Sleep Mode During Conversion.................................................................................................................231
24.6 Related Register......................................................................................................................................................232
24.6.1 AD Control Register ADCON0.............................................................................................................................232
24.6.2 AD Control Register ADCON1.............................................................................................................................233
24.6.3 AD Control Register ADCON2.............................................................................................................................233
24.6.4 AD Channel Selection Register ADCCHS ...........................................................................................................234
24.6.5 AD Comparator Control Register ADCMPC ........................................................................................................234
24.6.6 AD Hardware Trigger Delay Data Register ADDLYL ...........................................................................................235
24.6.7 AD Data Register High Bits ADRESH，ADFM=0(Left-aligned) ..........................................................................235
24.6.8 AD Data Register Low Bits ADRESL，ADFM=0(Left-aligned)............................................................................235
24.6.9 AD Data Register High ADRESH，ADFM=1(Right-aligned) ...............................................................................236
24.6.10 AD Data Register Low ADRESH，ADFM=1(Right-aligned)................................................................................236
24.6.11 AD Comparator Data Register ADCMPH ............................................................................................................236

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24.6.12 AD Comparator Data Register ADCMPL.............................................................................................................236
24.6.13 AD Reference Voltage Control Register..............................................................................................................237
24.7 ADC Interrupt ..........................................................................................................................................................238
24.7.1 Interrupt Mask Register EIE2 ..............................................................................................................................238
24.7.2 Interrupt Priority Control Register EIP2 ...............................................................................................................239
24.7.3 External Interrupt Flag Bit Register EIF2.............................................................................................................240
25. Temperature Sensor......................................................................................................241
25.1 Overview .................................................................................................................................................................241
25.2 Register Description ................................................................................................................................................241
25.2.1 Temperature Sensor Control Register TS_REG..................................................................................................241
25.3 Functional Description.............................................................................................................................................241
25.3.1 Configuration.......................................................................................................................................................241
25.3.2 Functional Characteristic.....................................................................................................................................242
25.3.3 Calculation Formula ............................................................................................................................................243
26. TOUCH ............................................................................................................................244
26.1 Precautions For Using The Touch Module...............................................................................................................244
27. ACMP0/1 .........................................................................................................................245
27.1 Comparator Characteristics.....................................................................................................................................245
27.2 Comparator Structure..............................................................................................................................................245
27.3 Related Register......................................................................................................................................................247
27.3.1 Comparator Control Register CnCON0...............................................................................................................247
27.3.2 Comparator Control Register C0CON1...............................................................................................................248
27.3.1 Comparator Control Register C1CON1...............................................................................................................248
27.3.2 Comparator Control Register CnCON2...............................................................................................................248
27.3.3 Comparator Adjust Bit Select Register C0ADJE .................................................................................................249
27.3.4 Comparator Hysteresis Control Register CnHYS................................................................................................250
27.3.5 Comparator Reference Voltage Control Register CNVRCON.............................................................................250
27.3.6 Comparator Brake Control Register CNFBCON .................................................................................................251
27.4 Comparator Interrupt ...............................................................................................................................................252
27.4.1 Interrupt Priority Control Register EIP1 ...............................................................................................................252
27.4.2 Comparator Interrupt Mask Register CNIE..........................................................................................................252
27.4.3 Comparator Interrupt Flag Register CNIF ...........................................................................................................253
28. OP0/1...............................................................................................................................254
28.1 OP Amp Characteristics ..........................................................................................................................................254
28.2 OP Amp Structure ...................................................................................................................................................254
28.3 Related Register......................................................................................................................................................255
28.3.1 Op Amp Control Register OPnCON0 ..................................................................................................................255
28.3.2 Op Amp Control Register OPnCON1 ..................................................................................................................255
28.3.3 Op Amp Adjustment Bit Selection Register OPnADJE ........................................................................................256
29. Flash Memory.................................................................................................................257
29.1 Overview .................................................................................................................................................................257
29.2 Related Register......................................................................................................................................................258
29.2.1 FLASH Protection Lock Register MLOCK ...........................................................................................................258
29.2.2 FLASH Memory Data Register MDATA ...............................................................................................................258
29.2.3 FLASH Memory Low Address Register MADRL .................................................................................................258
29.2.4 FLASH Memory High Address Register MADRH ................................................................................................259
29.2.5 Program CRC Operation Result Data Register Low 8-bit PCRCDL....................................................................259
29.2.6 Program CRC Operation Result Data Register High 8-bit PCRCDH ..................................................................259
29.2.7 FLASH Memory Control Register MCTRL ..........................................................................................................260

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29.3 Function Description................................................................................................................................................261
30. Unique ID（UID）...........................................................................................................262
30.1 Overview .................................................................................................................................................................262
30.2 UID Register Description.........................................................................................................................................262
31. User Configuration ........................................................................................................265
32. Online Programming And Debugging..........................................................................267
32.1 Online Programming Mode......................................................................................................................................267
32.2 Online Debug Mode ................................................................................................................................................268
33. Instruction Description..................................................................................................269
33.1 Symbol Description .................................................................................................................................................269
33.2 List Of Instruction ....................................................................................................................................................270
34.Revision History ............................................................................................................273

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1. Central Processing Unit（CPU）
This series is a microcontroller with 8-bit 8051 frame structure. The CPU is the core component of the microcontroller, which
is composed of arithmetic units, controllers, and special register groups. The arithmetic unit module mainly implements data
arithmetic and logic operations, bit variable processing and data transfer operations; the controller module mainly decodes
instructions, and then sends out various control signals; the special register group is mainly used to indicate the memory address
of the current instruction to be executed , Store the operand and indicate the state after the instruction is executed. The special
register group mainly includes accumulator ACC, general register B, stack pointer SP, data pointer DPTR, program status
register PSW, program counter PC, etc.
1.1 Reset Vector（0000H）
The microcontroller has a word-length system reset vector (0000H). After a reset occurs, the program will restart from
0000H, and the system registers will all be restored to default values. The following program demonstrates how to define the
reset vector in FLASH.
Example: Define reset vector
ORG
0000H
; System Reset Vector
LJMP
START
ORG
0010H
;User Program Initiation
START:
…
;User Program
…
END
;End of Proceedings
1.2 BOOT Partition
The size of the program area is 32K*8Bit, and the program is divided into BOOT area and APROM area. The size of the
BOOT area is allocated by the user configuration register.
The chip is powered on, if the program starts from the BOOT area, it needs to meet: the address space allocation method
is 1/2/3 (set BOOT_1K/BOOT_2K/BOOT_4K through the CONFIG), otherwise the program will start from APROM area.
Take the BOOT area 1K space as an example: CONFIG configures BOOT_1K, after the chip is powered on and configured,
the program starts to run from address 7C00H. If the program needs to switch between the BOOT area and the APROM area,
write 0xAA/0x55 to the BOOT area control register BOOTCON (see register description for details), and then perform a software
reset or generate a watchdog reset.
During power-on reset, external reset, and voltage reset, the BOOTCON reset value is 0x00. Software reset and watchdog
reset cannot clear this register.

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BOOT Control Register（BOOTCON）
F691H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
BOOTCON
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit0
D<7:0>:
BOOT area control bit (this register can only be written when the chip is configured as
BOOT_1K/BOOT_2K/BOOT_4K);
0x55=
If you switch from APROM area to BOOT area, you need to write 0x55 to it, then perform
software reset or generate watchdog reset;
0xAA=
If you switch from the BOOT area to the APROM area, you need to write 0xAA to it, and
then perform a software reset or generate a watchdog reset;
Other=
Invalid.
For example: After the chip is powered on and started from the BOOT area, use the software reset method to switch to the
APROM area, and the configuration is as follows:
1) BOOTCON register needs to write AAH
MOV DPTR,# BOOTCON
MOV A,#0AAH
MOVX @DPTR,A
2) Perform software reset
MOV TA,#0AAH
MOV TA,#055H
MOV WDCON,#080H
For example: Use the software reset method, and then switch from the APROM area to the BOOT area, the configuration
is as follows:
1) BOOTCON register needs to write 55H
MOV DPTR，# BOOTCON
MOV A,#055H
MOVX @DPTR,A
2) Perform software reset
MOV TA,#0AAH
MOV TA,#055H
MOV WDCON,#080H
Note: When the BOOT function is valid, the APROM program needs to ensure that the PC will not overflow (overflow means
that the PC exceeds the address range of the APROM). If the PC overflows, the system may operate abnormally.

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1.3 Accumulator（ACC）
ALU is an 8Bit wide arithmetic logic unit, and all the mathematics and logic operations of the MCU are completed through
it. It can add, subtract, shift and logic operations on data; ALU also controls the status bit (in the PSW status register) to indicate
the status of the result of the operation.
The ACC register is an 8Bit register, and the result of the ALU operation can be stored here.
1.4 B Register（B）
The B register is used when using multiplication and division instructions. If you don't use multiplication and division
instructions, they can also be used as general-purpose registers.
1.5 Stack Pointer Register（SP）
SP Register points to the address of the stack, after a reset, it goes to its initial values 0x07, it means that the stack area
starts with the 08H of the RAM address. The value of the SP can be modified. If the stack area is set to 0xC0, the value of SP
needs to be set to 0xBF after the system is reset.
Operations affecting SP:PUSH, LCALL, ACALL, POP, RET, RETI and interrupt access.
The PUSH instruction occupies one byte in the stack, LCALL, ACALL and interrupt access occupy two.
Using the PUSH instruction will automatically save the current value of the operated register to RAM.
1.6 Data Pointer Register（DPTR0/DPTR1）
The data pointer is mainly used in MOVX and MOVC instructions, and its function is to locate the addresses of XRAM and
ROM. There are two data pointer registers DPTR0 and DPTR1 inside the chip, selected by DPS register.
Each set of pointers includes two 8-bit registers: DPTR0={DPH0,DPL0}; DPTR1={DPH1,DPL1};
For example, the assembly code for operating XRAM is as follows:
MOV
DPTR,#0001H
MOV
A,#5AH
MOVX
@DPTR,A
;Write the data in A into the XRAM address 0001H

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1.7 Data Pointer Selection Register（DPS）
Data Pointer Selection Register DPS
0x86
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DPS
ID1
ID0
TSL
AU
--
--
--
SEL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7~Bit6
ID<1:0>:
Self-subtract/ self-add function selection.
00=
DPTR0 add 1 or DPTR1 add 1;
01=
DPTR0 minus 1 or DPTR1 add 1;
10=
DPTR0 add 1 or DPTR1 minus 1;
11=
DPTR0 minus 1or DPTR1 minus 1.
Bit5
TSL:
Flip selection enable;
1=
After the DPTR command is executed, the SEL will flip automatically;
0=
DPTR related instructions do not affect SEL.
Bit4
AU:
Self-add / self-subtract enable;
1=
After the MOVX @ DPTR or MOVC @ DPTR instructions are allowed to run, the
operation
of self-add / self-subtract (depends on ID1 - ID0) is performed.
0=
DPTR related instructions does not affect SEL.
Bit3~Bit1
--
Reserved, all must be 0.
Bit0
SEL:
Data pointer selection;
1=
Select DPTR1;
0=
Select DPTR0.
1.8 Program Status Register（PSW）
Program Status Register PSW
0xD0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PSW
CY
AC
F0
RS1
RS0
OV
--
P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset value
0
0
0
0
0
0
0
0
Bit7
CY:
Carry flag;
1=
Carry;
0=
No carry.
Bit6
AC:
Auxiliary Carry Flag (half carry flag bit );
1=
Carry;
0=
No carry.
Bit5
F0:
General Purpose Flag.
Bit4~Bit3
RS<1:0>:
Work Register BANK Select;
00=
Select Bank0;
01=
Select Bank1;

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10=
Select Bank2;
11=
Select Bank3.
Bit2
OV:
Overflow Flag;
1=
Arithmetic or logical operation has overflow;
0=
Arithmetic or logical operation has no overflow.
Bit1
--
Reserved, must be 0.
Bit0
P:
Parity;
1=
The highest bit of the result is carried.
0=
The highest bit of the result does not carry.
1.9 Program Counter（PC）
Program Counter(PC) controls the order in which instructions are executed in the program memory Flash, it can address
the entire range of Flash. After obtaining the script, the PC will automatically add 1 to point to the address of the next script. But
if operations such as jump, conditional jump, subroutine call, initialization reset, interrupt, interrupt return, subroutine return are
performed, the PC will load the address related to the instruction instead of the address of the next instruction.
When a conditional jump instruction is encountered and the jump condition is met. The next instruction read will be discarded
during the current instruction execution, and an empty instruction operation cycle will be inserted before the correct instruction
can be obtained. On the contrary, the next instruction will be executed sequentially.
1.10 Timing Access Register（TA）
Timing Access Register TA
0x96
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TA
TA7
TA6
TA5
TA4
TA3
TA2
TA1
TA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
0
0
0
0
0
0
0
0
Bit7~Bit0
TA<7:0>:
timing access control.
Some protected registers must perform the following operations on TA before they
can be written.
MOV
TA, #0AAH
MOV
TA, #055H
No other instructions can be inserted in the middle, and this sequence needs to
be re-executed when it is modified again.
Protected register:
WDCON，CLKDIV，SCKSEL.

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2. Memory And Register Map
This series of micro-controllers has the following types of memories:
◆Maximum 32KB FLASH program memory (shared by APROM area and BOOT area).
◆Maximum 1KB non-volatile data memory (Data FLASH).
◆Maximum 256B general-purpose internal data memory (RAM).
◆Maximum 2KB general-purpose external data memory (XRAM).
◆Special function register SFR (BANK0 and BANK1).
◆External special function register XSFR.
2.1 Program Memory FLASH
The program memory FLASH is used to store the source program and table data, and the program counter PC is used as
the address pointer. The PC is a 16-bit program counter, so the address space that can be addressed is 64KB, but this chip has
only 32K bytes of program storage space.
The block diagram of the FLASH space allocation structure is shown in the figure below:
FLASH: 32KB
APROM area
BOOT area
7FFFH
0000H
After the chip is reset, the CPU starts to execute from 0000H. Each interrupt is assigned a fixed address in the program
memory, and the interrupt causes the CPU to jump to this address and start executing the service program.
For example, external interrupt 1 is assigned address 0013H. If external interrupt 1 is used, its service program must start
from 0013H. If this interrupt is not used, its service address will be used as a normal program storage address.

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2.2 Non-volatile Data Memory Data FLASH
The non-volatile data memory Data FLASH can be used to store important data such as constant data, calibration data,
protection and safety-related information. The data stored in this area has the characteristic that the data will not be lost when
the chip is powered off or suddenly or unexpectedly. The block diagram of the Data FLASH space allocation structure is shown
in the figure below:
03FFH
DataFLASH
1KB
0000H
The reading, writing, and erasing operations of Data FLASH memory are realized through the FLASH control interface.

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2.3 General Data Register RAM
The internal data memory is divided into 3 parts: low 128Bytes, high 128Bytes, and special function register SFR. The
structure diagram of RAM space allocation is shown in the figure below:
Upper 128bytes
Internal RAM
(Indirect Addressing)
FFH
80H
Lower 128bytes
Internal RAM
(Direct or Indirect
Addressing)
7FH
00H
Special Function Registers
128bytes
(Direct Addressing)
FFH
80H
The high 128Bytes and SFR shown in the figure above occupy the same area (80H~FFH), but they are independent.
Directly address the storage space (SFR) higher than 7FH and indirectly address the storage space higher than 7FH (high
128Bytes) into different storage spaces. SFR is divided into two pages, BANK0 and BANK1, each page is 128Bytes, occupying
the same address area, and entering different storage spaces through the paging register selection.
The lower 128Bytes space register allocation shown in the figure above is shown in the figure below. The lowest 32 bytes
(00H~1FH) constitute 4 register groups, each group of 8 storage units, with R0~R7 as the unit number, used to store operands
and intermediate results. After reset, group 0 is selected by default. If another register group is selected, it needs to be
determined by changing the program state. The 16Bytes (20H~2FH) behind the register group constitute a bit-addressable
storage space. The RAM unit in this area can be operated by byte or directly on each bit in the unit. For the remaining 80 storage
units (30H~7FH), users can set the stack area and store intermediate data.