Cmsemicon BAT32A237 User manual

BAT32A237 User's Guide |Documentation Usage Instructions
www.mcu.com.cn 1 / 1037 V1.00
BAT32A237 User Manual
Ultra-low power 32-bit microcontroller based on ARM® Cortex®-M0+
Rev1.00
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BAT32A237 User's Guide |Documentation Usage Instructions
www.mcu.com.cn 2 / 1037 V1.00
Documentation Instructions
This manual is the technical reference manual for the BAT32A237 microcontroller product. The technical
reference manual is the application instruction material on how to use this series of products, including the
structure, function description, working mode and register configuration of each functional module.
The technical reference manual is a description of all functional modules of this series of products. If you want
to know the feature description of the product (that is, the functional configuration), you can refer to the respective
data sheet.
The data sheet information is as follows：
BAT32A237xx：BAT32A237_datasheet_vx.x. pdf
Usually in the early stage of chip selection, you shall first check the data sheet to evaluate whether the product
can meet the functional requirements of the design; after basically selecting the required product, you need to check
the technical reference manual to determine whether the working mode of each functional module does meet the
requirement；When determining the selection and entering the programming design stage, you need to read the
technical reference manual in detail to understand the specific implementation and register configuration of each
function. Refer to the data sheet for information on voltages, currents, drive capabilities, and pin assignments when
designing hardware。
For a detailed description of the Cortex-M0+ core, SysTick timer and NVIC, please refer to the respective ARM
documents.

BAT32A237 user manual | Chapter 1 CPU
www.mcu.com.cn 3 / 1037 V1.00
Chapter 1 CPU
1.1 verview
This Chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+
kernel on which this product is built. Please refer to the ARM documentation for details.
1.2 Cortex-M0+ core features
⚫ARM Cortex-M0+ processors are 32-bit RISC cores with a 2-stage pipeline that supports privileged and
user modes
⚫Memory Protection Units (MPUs) support 8 separate Zone (region) protection
⚫single cycle hardware multiplier
⚫Nested Vector Interrupt Controller (NVIC)
◼1 Unshielded Interrupt (NMI)
◼Supports 32 Masking Interrupt Requests (IRQs)
◼4 interrupt priority
⚫The system timer SysTick is a 24-bit countdown timer that can be selected for fCLK or fIL count clocks
⚫vector table offset register (VTOR)
◼The software can write VTOR to relocate the start address of the vector table to a different location
◼The default value for this register is 0x0000_0000, with low 8-bit write ignore, read to zero, that is,
offset 256 bytes aligned
1.3 Debug features
⚫2-wire SWD debug interface
⚫Support for pausing, resuming, and single-step execution procedures
⚫Access processor's kernel register and special function register
⚫4 Hardware Breakpoints (BPUs)
⚫Unlimited software breakpoints (BKPT instruction)
⚫2 data observation points (DWT)
⚫Access memory during kernel execution
⚫Micro Trace Cache (MTB) provides a simple instruction execution trace scheme
- MTB shared with user SRAM (0x2000_0000-0x2000_2 FFF zone)
- The base address of the MTB control register is 0x4001_9000

BAT32A237 user manual | Chapter 1 CPU
www.mcu.com.cn 4 / 1037 V1.00
Figure 1-1 Debug Block Diagram for Cortex-M0+
Note: SWD does not work in Deep Sleep mode, please debug in active and sleep mode.
bus matrix
Cortex
-
M0+
core
SW
-
DP
Bridge
NVIC
DWT
BPU
MTB
system bus
Cortex
-
M0+
debug support
MCU
debug support
SWDIO
SWCLK
DBGMCU
AHB
-
AP

BAT32A237 user manual | Chapter 1 CPU
www.mcu.com.cn 5 / 1037 V1.00
1.4 SWD interface pin
2 GPIO of the product can be used as SWD interface pins that are present in all packages.
Table 1-1 SWD Debug Port Pin
When you do not use the SWD feature, you can disable the SWD by setting the debug stop control register
(DBGSTOPCR).
Bit no.
31
30
29
28
27
26
25
24
DBGSTOPCR
-
-
-
-
-
-
-
SWDIS
Default
0
0
0
0
0
0
0
0
Bit no.
23
22
21
20
19
18
17
16
DBGSTOPCR
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit no.
15
14
13
12
11
10
9
8
DBGSTOPCR
-
-
-
-
-
-
-
-
Default
0
0
0
0
0
0
0
0
Bit no.
7
6
5
4
3
2
1
0
DBGSTOPCR
-
-
-
-
-
-
FRZEN1
FRZEN0
Default
0
0
0
0
0
0
0
0
SWDIS
SWD Debug Interface Disable
0
SWD debug interface enable. P40 cannot be used as a GPIO in the state where the debugger is connected
(because the ENO and DOUT for that IOBUF are now controlled by the debugger)
1
The SWD debug interface is disabled. P40 can be used as GPIO
FRZEN0
In the state where the debugger is connected and the CPU is in the debug state (HALED=1), the timer is the
peripheral module action/stop note 1
0
peripheral action
1
peripheral stop
FRZEN1
In the state where the debugger is connected and the CPU is in the debug state (HALED=1), the
communication system peripheral module action/stop note 2
0
peripheral action
1
peripheral stop
Note 1: The timer system peripheral module of the product includes: Universal timer unit Timer4, timer A, timer B,
timer C, and timer M
Note 2: The communication system peripheral module of this product includes: Communication Serial
Communication Unit, Serial IICA
SWD port name
Debug Function
pin assignment
SWCLK
serial clock
P137
SWDIO
Serial Data Input/Output
P40

BAT32A237 user manual | Chapter 1 CPU
www.mcu.com.cn 6 / 1037 V1.00
1.5 ARM reference document
The built-in debugging features in the Cortex®-M0+ kernel are part of the ARM® CoreSight design suite. For
documentation, refer to:
⚫Cortex®-M0+ Technical Reference Manual (TRM)
⚫ARM® Debug Interface V5
⚫ARM® CoreSight Design Kit Version r1p1 Technical Reference Manual
⚫ARM® CoreSi-M0+ Technical Reference Manual

BAT32A237 user manual | Chapter 2 Pin function
www.mcu.com.cn 7 / 1037 V1.00
Chapter 2 Pin function
2.1 port function
Refer to datasheet for each product family.
2.2 port multiplex
Refer to datasheet for each product family.

BAT32A237 user manual | Chapter 2 Pin function
www.mcu.com.cn 8 / 1037 V1.00
2.3 Register for controlling port function
Control the port through the following registers.
Port Mode Registers (PMxx)
Port Registers (Pxx)
Pull-up resistor selection registers (PUxx)
Port Input Mode Registers (PIMx)
Port Output Mode Registers (POMx)
Port Mode Control Registers (PMCxx)
Peripheral I/O Redirection Registers (PIORx)
Global Digital Input Disable Register (GDIDIS)
Note: The assigned registers and bits differ depending on the product. Refer to for registers and bits allocated by each
productTable 2-1. You must set an initial value for unassigned bits.
Table 2-1 PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and bits (1/2)
Port
bit name
64
pin
48
pin
44
pin
40
pin
32
pin
24
pin
PMxx
register
Pxx
register
PUxx
register
PIMxx
register
POMxx
register
PMCxx
register
Port 0
0
PM00
P00
PU00

POM00
PMC00Note 1
○
○
○
○
○
○
1
PM01
P01
PU01
PIM01

PMC01Note 1
○
○
○
○
○
○
2
PM02
P02
PU02

POM02
PMC02
○





3
PM03
P03
PU03
PIM03
POM03
PMC03
○





4
PM04
P04
PU04
PIM04
POM04
PMC04
○





5
PM05
P05
PU05



○





6
PM06
P06
PU06



○





Port 1
0
PM10
P10
PU10
PIM10
POM10
PMC10
○
○
○
○
○
○
1
PM11
P11
PU11

POM11
PMC11
○
○
○
○
○
○
2
PM12
P12
PU12


PMC12Note 2
○
○
○
○
○
○
3
PM13
P13
PU13

POM13
PMC13Note 2
○
○
○
○
○
○
4
PM14
P14
PU14
PIM14
POM14
PMC14Note 2
○
○
○
○
○
○
5
PM15
P15
PU15
PIM15
POM15

○
○
○
○
○
○
6
PM16
P16
PU16
PIM16


○
○
○
○
○

7
PM17
P17
PU17
PIM17
POM17

○
○
○
○
○

Port 2
0
PM20
P20



PMC20
○
○
○
○
○
○
1
PM21
P21



PMC21
○
○
○
○
○
○
2
PM22
P22



PMC22
○
○
○
○
○
○
3
PM23
P23



PMC23
○
○
○
○
○

4
PM24
P24



PMC24
○
○
○
○


5
PM25
P25



PMC25
○
○
○
○


6
PM26
P26



PMC26
○
○
○



7
PM27
P27



PMC27
○
○
○



Note: 1. Products with 24-48 pins only.
2. Products with 24-64 pins only.

BAT32A237 user manual | Chapter 2 Pin function
www.mcu.com.cn 9 / 1037 V1.00
Table 2-2: PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and bits (2/2)
Port
bit name
64
pin
48
pin
44
pin
40
pin
32
pin
24
pin
PMxx
register
Pxx
register
PUxx
register
PIMxx
register
POMxx
register
PMCxx
register
Port 3
0
PM30
P30
PU30
PIM30
POM30

○
○
○
○
○

1
PM31
P31
PU31
PIM30 Note 1
POM31 Note 1

○
○
○
○
○

Port 4
0
PM40
P40
PU40



○
○
○
○
○
○
1
PM41
P41
PU41



○
○
○



2
PM42
P42
PU42



○





3
PM43
P43
PU43



○





Port 5
0
PM50
P50
PU50
PIM50
POM50

○
○
○
○
○
○
1
PM51
P51
PU51

POM51

○
○
○
○
○
○
2
PM52
P52
PU52



○





3
PM53
P53
PU53



○





4
PM54
P54
PU54



○





5
PM55
P55
PU55
PIM55
POM55

○





Port 6
0
PM60
P60




○
○
○
○


1
PM61
P61




○
○
○
○


2
PM62
P62




○
○
○



3
PM63
P63




○
○
○



Port 7
0
PM70
P70
PU70



○
○
○
○
○

1
PM71
P71
PU71

POM71

○
○
○



2
PM72
P72
PU72



○
○
○
○
○
○
3
PM73
P73
PU73



○
○
○
○
○
○
4
PM74
P74
PU74
PIM74 Note 1
POM74

○
○

○
○

5
PM75
P75
PU75



○
○

○


6
PM76
P76
PU76



○





7
PM77
P77
PU77



○





Port 12
0
PM120
P120
PU120


PMC120
○
○
○
○
○

1

P121




○
○
○
○
○
○
2

P122




○
○
○
○
○
○
3

P123




○
○
○
○


4

P124




○
○
○
○


Port 13
0

P130




○
○




6
PM136
P136
PU136



○
○

○
○
○
7
PM137
P137
PU137



○
○
○
○
○
○
Port 14
0
PM140
P140
PU140



○
○

○


1
PM141
P141
PU141



○





6
PM146
P146
PU146


PMC146
○
○
○



7
PM147
P147
PU147


PMC147
○
○
○
○
○
○
Note: 1. Products with 32 pins only.

BAT32A237 user manual | Chapter 2 Pin function
www.mcu.com.cn 10 / 1037 V1.00
2.3.1 Port Mode Register (PMxx)
This is a register that sets the port input/output in bits. After the reset signal is generated, the values of these
registers become "FFH". When using a port pin as a pin for a multiplexing function, it must be configured according
to reference to "2.5 Register settings when using multiplexing function.
Register address = base address + offset address; The PM register has a base address of 0x40040000 and
the offset address is shown in the figure below.
Figure 2-1 Port mode register format
symbol
7
6
5
4
3
2
1
0
offset
After
Reset
R/W
PM0
1
PM06
PM05
PM04
PM03
PM02
PM01
PM00
0x320
FFH
R/W
PM1
PM17
PM16
PM15
PM14
PM13
PM12
PM11
PM1 0
0x321
FFH
R/W
PM2
PM27
PM26
PM25
PM24
PM23
PM22
PM21
PM20
0 x322
FFH
R/W
PM3
1
1
1
1
1
1
PM31
PM3 0
0x323
FFH
R/W
PM4
1
1
1
1
PM43
PM42
PM 41
PM4 0
0x324
FFH
R/W
PM5
1
1
PM55
PM54
PM53
PM52
PM 51
PM50
0x325
FFH
R/W
PM6
1
1
1
1
PM63
PM62
PM61
PM60
0x326
FFH
R/W
PM7
PM77
PM76
PM75
PM74
PM73
PM72
PM 71
PM70
0x327
FFH
R/W
PM12
1
1
1
1
1
1
1
PM120
0x32C
FFH
R/W
PM13
PM137
PM136
1
1
1
1
1
PM130
0x32D
FEH
R/W
PM14
PM147
PM146
1
1
1
1
PM141
PM140
0x32E
FFH
R/W
PMmn
Selection of Input/Output Modes of Pmn Pins (m=0~7,12~14, n=0~7)
0
Output mode (used as output port (output buffer ON))
1
Input mode (used as input port (output buffer OFF))
Note: You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.2 Port Register (Pxx)
This is a register that sets the value of the port output latch in bits. The pin level is read in the input mode and
the output latch value of the port is read in the output mode. After the reset signal is generated, the values of these
registers change to '00H'.
Register address = base address + offset address; The base address of the port register is 0x40040000 and
the offset address is shown below. Figure 2-2 Port register format
symbol
7
6
5
4
3
2
1
0
Address
After Reset
R/W
P0
0
P06
P05
P04
P03
P02
P01
P00
0x300
00H (Output Latch)
R/W
P1
P17
P16
P15
P14
P13
P12
P11
P10
0x301
00H (Output Latch)
R/W
P2
P27
P26
P25
P24
P23
P22
P21
P20
0x302
00H (Output Latch)
R/W
P3
0
0
0
0
0
0
P31
P30
0x303
00H (Output Latch)
R/W
P4
0
0
0
0
P43
P42
P41
P40
0x304
00H (Output Latch)
R/W
P5
0
0
P55
P54
P53
P52
P51
P50
0x305
00H (Output Latch)
R/W
P6
0
0
0
0
P63
P62
P61
P60
0x306
00H (Output Latch)
R/W
P7
P77
P76
P75
P74
P73
P72
P71
P70
0x307
00H (Output Latch)
R/W
P12
0
0
0
P124
P123
P122
P121
P120
0x30C
indefinite value
R/W Note
1
P13
P137
P136
0
0
0
0
0
P130
0x30D
00H (Output Latch)
R/W
P14
P147
P146
0
0
0
0
P141
P140
0x30E
00H (Output Latch)
R/W
Pmn
m=0~7,12~14, n=0~7
Control of output data (output mode)
Reading of input data (input mode)
0
Output "0".
Input low level.
1
Output "1".
Input high level.
Note: 1. P121~P124 is a read only bit.
2. You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.3 Pull-up resistance selection register (PUxx)
Selection register for internal pull-up resistance. Internal pull-up resistors can only be used in bit units if the
POMmn bit is '0' and set to the input mode (PMmn=1). For the bit set to the output mode, the internal pull-up resistor
is not connected regardless of the setting of the pull-up resistor selection register. The same is true when the output
pin used as the multiplexing function or set as the analog function.
After the reset signal is generated, the values of these registers become '00H' (only PU4 is '01H' and PU13 is
'80H').
register address = base address + offset address; The PU register has a base address of 0x40040000 and the
offset address is shown in the figure below.
Figure 2-3: Format of pull-up resistor selection register
symbol
7
6
5
4
3
2
1
0
offset
After
Reset
R/W
PU0
0
PU06
PU05
PU04
PU03
PU02
PU01
PU00
0x030
00H
R/W
PU1
PU17
PU1 6
PU15
PU14
PU13
PU12
PU11
PU1 0
0x031
00H
R/W
PU3
0
0
0
0
0
0
PU31
PU30
0x033
00H
R/W
PU4
0
0
0
0
PU43
PU42
PU41
PU4 0
0x034
01H
R/W
PU5
0
0
PU55
PU54
PU53
PU52
PU51
PU50
0x035
00H
R/W
PU7
PU77
PU7-6
PU7-5
PU7-4
PU7-3
PU7-2
PU7-1
PU70
0x037
00H
R/W
PU12
0
0
0
0
0
0
0
PU120
0x03C
00H
R/W
PU13
PU137
PU136
0
0
0
0
0
0
0x03D
80H
R/W
PU14
PU147
PU146
0
0
0
0
PU141
PU140
0x03E
00H
R/W
PUMN
Selection of internal pull-up resistance of Pmn pin (m=0,1,3~5,7,12~14,n=0~7)
0
The internal pull-up resistor is not connected.
1
Connect the internal pull-up resistor.
Note: You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.4 Port input mode register (PIMxx)
This is a register that sets the input buffer in bits. The TTL input buffer can be selected in serial communication
with external devices of different potentials. After the reset signal is generated, the values of these registers change
to '00H'.
register address = base address + offset address; The PIM register has a base address of 0x40040000 and
the offset address is shown in the figure below.
Figure 2-4: Format of port input mode register
symbol
7
6
5
4
3
2
1
0
offset
After Reset
R/W
PIM0
0
0
0
PIM04
PIM03
0
PIM01
0
0x040
00H
R/W
PIM1
PIM17
PIM16
PIM15
PIM14
0
0
0
PIM1 0
0x041
00H
R/W
PIM3
0
0
0
0
0
0
PIM31
Note 1
PIM3 0
0x043
00H
R/W
PIM5
0
0
PIM55
0
0
0
0
PIM5 0
0x045
00H
R/W
PIM7
0
0
0
PIM74
Note 1
0
0
0
0
0x047
00H
R/W
PIMmn
Selection of input buffer for Pmn pin (m=0,1,3,5,7, n=0~7)
0
Schmidt input buffer
1
TTL input buffer
Note: 1. Products with 32 pins only.
2. You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.5 Port output mode register (POMxx)
This is a register that sets the output mode in bits. When serial communication is performed with external
devices of different potentials and simple I2C communication is performed with external devices of same potential,
N channel drain open output mode is selected for SDAxx pin.
After the reset signal is generated, the values of these registers change to '00H'.
Register address = base address + offset address; The POM register has a base address of 0x40040000 and
the offset address is shown in the figure below.
Note: The internal pull-up resistor is not connected to the bit where the N-channel drain open-circuit output mode
(POMmn=1) is set.
Figure2-5 Port output mode register format
symbol
7
6
5
4
3
2
1
0
offset
After Reset
R/W
POM0
0
0
0
POM04
POM03
POM02
0
POM00
0 x050
00H
R/W
POM1
POM17
0
POM15
POM14
POM13
0
POM11
POM1 0
0 x051
00H
R/W
POM3
0
0
0
0
0
0
POM31
Note 1
POM3 0
0 x053
00H
R/W
POM5
0
0
POM55
0
0
0
POM51
POM5 0
0 x055
00H
R/W
POM7
0
0
0
POM74
0
0
POM71
0
0 x057
00H
R/W
POMmn
Selection of Output Mode of Pmn Pin (m=0,1,3,5,7, n=0~7)
0
Normal output mode
1
N-channel drain open-circuit output mode
Note: 1. Products with 32 pins only.
2. You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.6 Port mode control register (PMCxx)
A digital input/output or analog input that is set in bits by the PMC register.
After the reset signal is generated, the values of these registers become "FFH".
register address = base address + offset address; The PMC register has a base address of 0x40040000 and
the offset address is shown in the figure below.
Figure2-6: Port mode control register format
symbol
7
6
5
4
3
2
1
0
offset
After
Reset
R/W
PMC0
1
1
1
PMC04
PMC03
PMC02
PMC01
Note 1
PMC00
Note 1
0 x06 0
FFH
R/W
PMC1
1
1
1
1
1
1
PMC11
PMC1
0
0 x06 1
FFH
R/W
PMC2
PMC27
PMC26
PMC25
PMC24
PMC23
PMC22
PMC21
PMC20
0 x062
FFH
R/W
PMC12
1
1
1
1
1
1
1
PMC120
0x06C
FFH
R/W
PMC14
PMC147
PMC146
1
1
1
1
1
1
0x06E
FFH
R/W
PMCmn
Digital input/output of Pmn pin or selection of analog input (m=0,1,2,12,14, n=0~7)
0
Digital Input/Output (multiplexing function other than analog input)
1
analog input
NOTE: 1. Products with 32-48 pins only.
2. You must set an initial value for unassigned bits.

BAT32A237 user manual | Chapter 2 Pin function
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2.3.7 Peripheral I/O Redirection Register 0 (PIOR0)
This is register 0 that sets the ability to allow or prohibit peripheral I/O redirection. The peripheral I/O
redirection function switches ports to which multiplexing is assigned.
After the reset signal is generated, the value of this register changes to "00H".
Figure 2-7: Format of Peripheral I/O Redirection Register 0 (PIOR0)
Address: 0x40040877 After reset: 00H R/W
symbol 7 6 5 4 3 2 1 0
PIOR0
PIOR0
Features
64pin
48pin
44pin
40pin
32pin
24pin
Set Values
Set Values
Set Values
Set Values
Set Values
Set Values
0
1
0
1
0
1
0
1
0
1
0
1
bit7(PIOR07)
INTP8
P74/P42
P00
P74
P00
INTP10
P76/P05
P01
must be set to 0 (initial value)
INTP11
P77/P06
P20
bit6(PIOR06)
RxD2
must be set to 0
(initial value)
P14
P14
P14
P14
P14
P14
P14
P14
P14
P14
TxD2
P13
P10
P13
P10
P13
P10
P13
P10
P13
P10
SCL20
P15
-
P15
-
P15
-
P15
-
P15
-
SDA20
P14
-
P14
-
P14
-
P14
-
P14
-
SDI20
P14
-
P14
-
P14
-
P14
-
P14
-
SDO20
P13
-
P13
-
P13
-
P13
-
P13
-
SCLK20
P15
-
P15
-
P15
-
P15
-
P15
-
bit5(PIOR05)
RXD1
P01
P73
P01
P73
P01
P73
P01
P73
P01
P73
TXD1
P00
P72
P00
P72
P00
P72
P00
P72
P00
P72
bit4(PIOR04)
CLKBUZ1
P141
P55
must be set to 0 (initial value)
INTP5
P16
P12
bit3(PIOR03)
CLKBUZ0
P140
P31
P140
P31
-
P31
P140
P31
bit2(PIOR02)
SCLA0
P60
P14
P60
P14
P60
P14
P60
P14
P31
P14
P01
P14
SDAA0
P61
P15
P61
P15
P61
P15
P61
P15
P74
P15
P00
P15
bit1(PIOR01)
INTP10
P76
P05
P01
P01
P01
P01
P01
P01
P01
P01
must be set
to 0 (initial
value)
INTP11
P77
P06
P20
P20
P20
P20
P20
P20
P20
P20
RXD2
P14
P76
must be set to 0 (initial value)
TXD2
P13
P77
SCL20
P15
-
SDA20
P14
-
SDI20
P14
-
SDO20
P13
-
SCLK20
P15
-
TXD0
P51
P17
P51
P17
P51
P17
P51
P17
P51
P17
RXD0
P50
P16
P50
P16
P50
P16
P50
P16
P50
P16
SCL00
P30
-
P30
-
P30
-
P30
-
P30
-
SDA00
P50
-
P50
-
P50
-
P50
-
P50
-
SDO00
P51
P17
P51
-
P51
-
P51
-
P51
-
SDI00
P50
P16
P50
-
P50
-
P50
-
P50
-
SCLK00
P30
P55
P30
-
P30
-
P30
-
P30
-
bit0(PIOR00)
INTP1
P50
P52
must be set to 0 (initial value)
PIOR07
PIOR06
PIOR05
PIOR04
PIOR03
PIOR02
PIOR01
PIOR00

BAT32A237 user manual | Chapter 2 Pin function
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INTP2
P51
P53
INTP3
P30
P54
INTP4
P31
P55
INTP8
P74
P42
INTP9
P75
P43

BAT32A237 user manual | Chapter 2 Pin function
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2.3.8 Peripheral I/O Redirection Register 1 (PIOR1)
This is setting to allow or disable peripheral I/O redirection feature register 1. The peripheral I/O redirection
function switches ports to which multiplexing is assigned.
After the reset signal is generated, the value of this register changes to "00H".
Figure 2-8: Format of Peripheral I/O Redirection Register 1 (PIOR1)
Address: 0x40040879H After reset: 00H R/W
symbol 7 6 5 4 3 2 1 0
PIOR1
PIOR13
PIOR12
Selection of Timer ATAO Pin
0
0
Multiplexed with P30 (32-64 pin products).
0
1
Multiplexed with P50.
1
0
Multiplexed with P00.
1
1
Setting is prohibited.
PIOR11
PIOR10
Selection of Timer ATAIO Pin
0
0
Multiplexed with P01.
0
1
Multiplexed with P31 (32-64 pin products).
1
0
Multiplexed with P41 (limited to 48, 64-pin products).
Other pin products are prohibited from setting.
1
1
Multiplexed with P06 (limited to 64-pin products).
Other pin products are prohibited from setting.
0
0
0
0
PIOR13
PIOR12
PIOR11
PIOR10

BAT32A237 user manual | Chapter 2 Pin function
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2.3.9 Peripheral I/O Redirection Register 2 (PIOR2)
This is setting to enable or disable peripheral I/O redirection feature register 2. The peripheral I/O redirection
function switches ports to which multiplexing is assigned. After the reset signal is generated, the value of this
register changes to "00H".
Figure 2-9: Format of Peripheral I/O Redirection Register 2 (PIOR2)
Address: 0x40040875 After reset: 00H R/W
symbol 7 6 5 4 3 2 1 0
PIOR2
PIOR2
Features
64pin
48pin
44pin
40pin
32pin
24pin
Set Values
Set Values
Set Values
Set Values
Set Values
Set Values
0
1
0
1
0
1
0
1
0
1
0
1
bit7(PIOR27)
TMIOC0
x
x
x
x
x
x
x
x
x
x
P16
P13
bit6(PIOR26)
TMIOD0
P15
P17
P15
P17
P15
P17
P15
P17
P15
P17
-
-
bit5(PIOR25)
TMIOD1
P11
P51
P11
P51
P11
P51
P11
P51
P11
P51
P11
P51
bit4(PIOR24)
TMIOC1
P13
P50
P13
P50
P13
P50
P13
P50
P13
P50
P13
P50
bit3(PIOR23)
TMIOB1
P10
P30
P10
P30
P10
P30
P10
P30
P10
P30
-
-
bit2(PIOR22)
TMIOA1
P12
P16
P12
P16
P12
P16
P12
P16
P12
P16
-
-
bit1(PIOR21)
VCOUT1
P31
P70
P31
P70
P31
P70
P31
P70
P31
P70
P147
P72
bit0(PIOR20)
VCOUT0
P120
P71
P120
P71
P120
P71
P120
P70
P120
P73
P12
P73
Note: x indicates that the bit must be set to the initial value of 0.
PIOR27
PIOR26
PIOR25
PIOR24
PIOR 23
PIOR22
PIOR21
PIOR20

BAT32A237 user manual | Chapter 2 Pin function
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2.3.10 Peripheral I/O Redirection Register 3 (PIOR3)
This is setting to enable or disable peripheral I/O redirection feature register 3. The peripheral I/O redirection
function switches ports to which multiplexing is assigned. After the reset signal is generated, the value of this
register changes to "00H".
Figure 2-10:Format of Peripheral I/O Redirection Register 3 (PIOR3)
Address: 0x4004087C After reset: 00H R/W
symbol 7 6 5 4 3 2 1 0
PIOR3
PIOR3
Features
64pin
48pin
44pin
Set Values
Set Values
Set Values
0
1
0
1
0
1
bit5(PIOR35)
TXD0
PIOR34 Control
P12
PIOR34 Control
P12
PIOR34 Control
P12
RXD0
PIOR34 Control
P11
PIOR34 Control
P11
PIOR34 Control
P11
bit4(PIOR34)
TXD0
PIOR01 Control
P40
PIOR01 Control
P40
PIOR01 Control
P40
RXD0
PIOR01 Control
P137
PIOR01 Control
P137
PIOR01 Control
P137
bit3(PIOR33)
CRXD0
P03
P50
P01
P50
P01
P50
CTXD0
P02
P51
P00
P51
P00
P51
bit2(PIOR32)
VCOUT1
Output L
PIOR21 Control
Output L
PIOR21 Control
Output L
PIOR21
Control
bit1(PIOR31)
VCOUT0
Output L
PIOR20 Control
Output L
PIOR20 Control
Output L
PIOR20
Control
bit0(PIOR30)
IrRXD
×
×
×
×
×
×
IrTXD
×
×
×
×
×
×
PIOR3
Features
40pin
32pin
24pin
Set Values
Set Values
Set Values
0
1
0
1
0
1
bit5(PIOR35)
TXD0
PIOR34 Control
P12
PIOR34 Control
P12
PIOR34 Control
P12
RXD0
PIOR34 Control
P11
PIOR34 Control
P11
PIOR34 Control
P11
bit4(PIOR34)
TXD0
PIOR01 Control
P40
PIOR01 Control
P40
PIOR01 Control
P40
RXD0
PIOR01 Control
P137
PIOR01 Control
P137
PIOR01 Control
P137
bit3(PIOR33)
CRXD0
P01
P50
P01
P50
P01
P50
CTXD0
P00
P51
P00
P51
P00
P51
bit2(PIOR32)
VCOUT1
Output L
PIOR21
Control
Output L
PIOR21 Control
Output L
PIOR21
Control
bit1(PIOR31)
VCOUT0
Output L
PIOR20
Control
Output L
PIOR20 Control
Output L
PIOR20
Control
bit0(PIOR30)
IrRXD
×
×
×
×
P14
P01
IrTXD
×
×
×
×
P13
P00
PIOR37
PIOR36
TMIA0
TMIOB0
TMIOC0
TMIOD0
TMIA1
TMIOB1
TMIOC1
TMIOD1
0
0
P17
P14
P16
P15
P12
P1 0
P1 3
P1 1
0
1
P17
P12
P16
P15
P1 1
P1 0
P14
P1 3
1
0
P17
P15
P16
P14
P1 3
P12
P1 1
P1 0
1
1
Disable setting
Note: x indicates that the bit must be set to the initial value of 0.
PIOR37
PIOR36
PIOR35
PIOR34
PIOR33
PIOR32
PIOR31
0