Texas Instruments AM243 Series User manual

User’s Guide
AM243x LaunchPad™ Development Kit User's Guide
ABSTRACT
The AM243x LaunchPad™ development kit is a simple and inexpensive hardware evaluation module (EVM) for
the Texas Intruments Sitara™ AM243x series of microcontrollers (MCUs). This EVM provides an easy way to
start developing on the AM243x MCUs with on-board emulation for programming and debugging as well as
buttons and LEDs for a simple user interface. The LaunchPad also features two independent BoosterPack XL
expansion connectors, on-board Controller Area Network (CAN) transciever, two RJ45 Ethernet ports, and an
on-board XDS110 debug probe.
Table of Contents
1 Preface: Read This First.........................................................................................................................................................3
1.1 If You Need Assistance...................................................................................................................................................... 3
1.2 Important Usage Notes...................................................................................................................................................... 3
2 Kit Overview............................................................................................................................................................................ 4
2.1 Kit Contents........................................................................................................................................................................5
2.2 Key Features......................................................................................................................................................................5
2.3 Component Identification................................................................................................................................................... 6
2.4 BoosterPacks..................................................................................................................................................................... 7
2.5 Compliance........................................................................................................................................................................ 7
3 Board Setup.............................................................................................................................................................................7
3.1 Power Requirements..........................................................................................................................................................7
3.1.1 Power Input Using USB Type-C Connector.................................................................................................................7
3.1.2 Power Status LED's ....................................................................................................................................................9
3.1.3 Power Tree................................................................................................................................................................ 10
3.1.4 Power Sequence........................................................................................................................................................11
3.2 Push Buttons.................................................................................................................................................................... 11
3.3 Boot Mode Selection........................................................................................................................................................ 12
4 Hardware Description...........................................................................................................................................................13
4.1 Functional Block Diagram................................................................................................................................................ 13
4.2 BoosterPack Headers...................................................................................................................................................... 14
4.2.1 Pinmux for BoosterPack............................................................................................................................................ 16
4.3 GPIO Mapping................................................................................................................................................................. 25
4.4 Reset................................................................................................................................................................................27
4.5 Clock................................................................................................................................................................................ 28
4.6 Memory Interface............................................................................................................................................................. 29
4.6.1 QSPI Interface........................................................................................................................................................... 29
4.6.2 Board ID EEPROM....................................................................................................................................................30
4.7 Ethernet Interface.............................................................................................................................................................31
4.7.1 Ethernet PHY Strapping............................................................................................................................................ 32
4.7.2 Ethernet PHY - Power, Clock, Reset, Interrupt..........................................................................................................34
4.7.3 LED indication in Ethernet RJ45 Connector.............................................................................................................. 34
4.8 USB 2.0 Interface.............................................................................................................................................................35
4.9 I2C Interface.....................................................................................................................................................................35
4.10 Industrial Application LEDs............................................................................................................................................ 36
4.11 UART Interface...............................................................................................................................................................37
4.12 eQEP Interface...............................................................................................................................................................38
4.13 CAN Interface.................................................................................................................................................................40
4.14 FSI Interface...................................................................................................................................................................41
4.15 JTAG Emulation............................................................................................................................................................. 43
4.16 Test Automation Interface.............................................................................................................................................. 44
4.17 SPI Interface.................................................................................................................................................................. 46
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5 References............................................................................................................................................................................ 80
5.1 Reference Documents..................................................................................................................................................... 80
5.2 Other TI Components Used in This Design..................................................................................................................... 80
6 Revision History................................................................................................................................................................... 80
A E3 Design Changes..............................................................................................................................................................81
List of Figures
Figure 2-1. AM243x LaunchPad Board....................................................................................................................................... 4
Figure 2-2. System Architecture.................................................................................................................................................. 5
Figure 2-3. AM243x LaunchPad Top Component Identification.................................................................................................. 6
Figure 2-4. AM243x LaunchPad Bottom Component Identification.............................................................................................6
Figure 3-1. Type-C CC Configuration.......................................................................................................................................... 8
Figure 3-2. USB Type-C Power Input.......................................................................................................................................... 8
Figure 3-3. Power Status LED's...................................................................................................................................................9
Figure 3-4. Power Tree Diagram of AM243x LaunchPad.......................................................................................................... 10
Figure 3-5. Power Sequence..................................................................................................................................................... 11
Figure 3-6. Boot-Mode DIP Switch............................................................................................................................................ 12
Figure 4-1. AM243x LaunchPad Functional Block Diagram...................................................................................................... 13
Figure 4-2. BoosterPack Header Pinout.................................................................................................................................... 14
Figure 4-3. Site #2 BoosterPack Header................................................................................................................................... 15
Figure 4-4. 80 Pin BoosterPack Pinout......................................................................................................................................16
Figure 4-5. Reset Architecture...................................................................................................................................................27
Figure 4-6. Clock Architecture................................................................................................................................................... 28
Figure 4-7. QSPI Interface.........................................................................................................................................................29
Figure 4-8. Board ID EEPROM..................................................................................................................................................30
Figure 4-9. Ethernet Connection................................................................................................................................................31
Figure 4-10. CPSW or PRG RGMII1 Ethernet Data Mux.......................................................................................................... 32
Figure 4-11. Ethernet PHY Strapping for RGMII1 PHY............................................................................................................. 33
Figure 4-12. Ethernet PHY Strapping for RGMII2 PHY............................................................................................................. 33
Figure 4-13. USB 2.0 Interface.................................................................................................................................................. 35
Figure 4-14. I2C Interface..........................................................................................................................................................35
Figure 4-15. Industrial Application LEDs................................................................................................................................... 36
Figure 4-16. UART Interface......................................................................................................................................................37
Figure 4-17. eQEP Interface......................................................................................................................................................38
Figure 4-18. eQEP1 Header...................................................................................................................................................... 38
Figure 4-19. eQEP2 Header...................................................................................................................................................... 39
Figure 4-20. eQEP2 or MCAN0 Mux Selection Circuit.............................................................................................................. 39
Figure 4-21. CAN Interface........................................................................................................................................................40
Figure 4-22. MCAN Transceiver and Header............................................................................................................................ 40
Figure 4-23. FSI Interface..........................................................................................................................................................41
Figure 4-24. FSI Header............................................................................................................................................................ 42
Figure 4-25. FSI or BoosterPack Mux Selection Circuit............................................................................................................ 42
Figure 4-26. JTAG Interface.......................................................................................................................................................43
Figure 4-27. Micro-B USB Connection for JTAG....................................................................................................................... 43
Figure 4-28. Test Automation Header........................................................................................................................................44
Figure 4-29. SPI Connection From SoC to BoosterPack Connector......................................................................................... 46
List of Tables
Table 3-1. Current Sourcing Capability and State of USB Type-C Cable.................................................................................... 8
Table 3-2. Power Status LED's.................................................................................................................................................... 9
Table 3-3. LaunchPad Push Buttons..........................................................................................................................................11
Table 3-4. Boot-Mode Selection Table ...................................................................................................................................... 12
Table 4-1. BoosterPack Power Sourcing for BoosterPack Site #2............................................................................................ 15
Table 4-2. Pinmux Options for J1/J3 Connector - Site 1............................................................................................................17
Table 4-3. Net Name in Schematic and Package Signal Name for J1/J3 Connector................................................................ 18
Table 4-4. Pinmux Options for J2/J4 Connector - Site 1............................................................................................................19
Table 4-5. Net Name in Schematic and Package Signal Name for J2/J4 Connector................................................................ 20
Table 4-6. Pinmux Options for J5/J7 Connector - Site 2............................................................................................................21
Table 4-7. Net Name in Schematic and Package Signal Name for J5/J7 Connector................................................................ 22
Table 4-8. Pinmux Options for J6/J8 Connector - Site 2............................................................................................................23
Table 4-9. Net Name in Schematic and Package Signal Name for J6/J8 Connector................................................................ 24
Table 4-10. GPIO Mapping Table...............................................................................................................................................25
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Table 4-11. Clock Frequency Table............................................................................................................................................28
Table 4-12. Board ID Memory Header Information.................................................................................................................... 30
Table 4-13. Ethernet PHY Strapping Values..............................................................................................................................34
Table 4-14. FSI Header Pin Description.................................................................................................................................... 41
Table 4-15. Test Automation Signal Description........................................................................................................................ 44
Table 4-16. Test Automation Header Pinout.............................................................................................................................. 45
Table A-1. E3 RJ45 Connector.................................................................................................................................................. 81
Table A-2. E3 GPIO Mapping.................................................................................................................................................... 81
Table A-3. E3 Ethernet PHY Signal Mapping............................................................................................................................ 82
Table A-4. E3 LED ACT Signal Resistor Mounting.................................................................................................................... 82
Trademarks
LaunchPad™, Sitara™, and E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
1 Preface: Read This First
1.1 If You Need Assistance
If you have any feedback or questions, support for the Sitara MCUs and the AM243x LaunchPad development
kit is provided by the TI Product Information Center (PIC) and the TI E2E™ Forum. Contact information for the
PIC can be found on the TI website. Additional device-specific information can be found in the Section 5.1.
1.2 Important Usage Notes
Note
The AM243x LaunchPad requires a 5 V, 3A power supply in order to function. While a USB type-C
cable is included, A 5 V, 3A power supply is not included in the kit and must be ordered separately.
The Belkin USB-C Wall Charger is known to work with the LaunchPad and the supplied type-C cable.
For more information on power requirements go to Section 3.1. If there is an error in the power input
then the red LED (LD9) will glow continuously. For more information about the power status LED's,
see Section 3.1.2.
Note
The JTAG connection through the micro-B USB port needs to be made after power is supplied to the
LaunchPad by the USB type-C connection. The JTAG may not connect if the micro-B USB connection
is made before the 5 V, 3A connection is made. For more information on JTAG emulation go to
Section 4.15 .
Note
For E1 and E2 revisions of the AM243x LaunchPad, some output signals are not able to propagate
to the BoosterPack headers. Any pinmux configuration that is an output signal for balls R21, T19,
U18, U20, V20 of the SoC will be gated by the isolation buffer U32 because the DIR pin of the buffer
is low (only allowing data transfer from side B to A). The signals that not able to propagate to the
BoosterPack headers include: UART2_RTSn, EHRPWM2_A, EHRPWM2_B, as well as any GPIO
signals on the listed pins.
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2 Kit Overview
Figure 2-1. AM243x LaunchPad Board
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Figure 2-2 shows the overall top level architecture of the AM243x LaunchPad.
Figure 2-2. System Architecture
2.1 Kit Contents
The Sitara AM243x Series LaunchPad Development Kit contains the following items:
• AM243x Sitara Series LaunchPad development board
• USB type-C cable
Note
The maximum length of the IO cables shall not exceed 3 meters.
2.2 Key Features
The AM243x LaunchPad has the following features:
• AM2434 (ALX) MCU
• PCB dimensions: 7.7 inch (195.58 mm) x 2.3 inch (58.42 mm)
• Powered through 5 V, 3A USB type-C input
• Two RJ45 Ethernet ports capable of 1Gb or 100Mb speeds
• On-board XDS110 debug probe
• Four push buttons:
– PORz Reset
– MCU warm reset
– SoC warm reset
– User interrupt
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• LED indicators for:
– Power status
– User testing
– Ethernet connection
– Industrial application
• CAN connectivity with on-board CAN transceiver
• Two independent Enhanced Quadrature Encoder Pulse (QEP)-based encoder connectors
• Separate FSI connector
• Two independent BoosterPack XL (40 pin) standard connectors featuring stackable headers to maximize
expansion through the BoosterPack ecosystem
• Test automation header
• On-Board Memory:
– 512 Mb QSPI flash
– 1 Mb I2C EEPROM
2.3 Component Identification
Figure 2-3. AM243x LaunchPad Top Component Identification
Figure 2-4. AM243x LaunchPad Bottom Component Identification
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2.4 BoosterPacks
The AM243x LaunchPad development kit provides an easy and inexpensive way to develop applications with the
AM243x Series microcontroller. BoosterPacks are add-on boards that follow a pin-out standard created by Texas
Instruments. The TI and third-party ecosystem of BoosterPacks greatly expands the peripherals and potential
applications that you can easily explore with the AM243x LaunchPad.
You can also build your own BoosterPack by following the design guidelines on TI’s website. Texas Instruments
even helps you promote your BoosterPack to other members of the community. TI offers a variety of avenues for
you to reach potential customers with your solutions.
2.5 Compliance
All components selected meet RoHS and REACH compliance.
Components installed on the product are sensitve to Electrostatic Discharge (ESD). It is recommended this
product be used in an ESD controlled environment. This may include a temperature and/or humidity controlled
environment to limit the buildup of ESD. It is also recommended to use ESD protection such as wrist straps and
ESD mats when interfacing with the product.
The product is used in the basic electromagnetic environment as in laboratory conditions, and the applied
standard is as per EN IEC 61326-1:2021.
3 Board Setup
3.1 Power Requirements
The AM243x LaunchPad is powered from a 5 V, 3A USB type-C input. The following sections describe the
power distribution network topology that supplied the AM243x LaunchPad, it is supporting components and the
reference voltages.
3.1.1 Power Input Using USB Type-C Connector
The AM243x LaunchPad is powered through a USB type-C connection. The USB Type-C source should be
capable of providing 3A at 5 V and should advertise the current sourcing capability through CC1 and CC2
signals. On AM243x LP, the CC1 and CC2 from USB type-C connector are interfaced to the port controller IC
(TUSB320LAIRWBR). This device uses the CC pins to determine port attach and detach, cable orientation, role
detection, and port control for Type-C current mode. The CC logic detects the Type-C current mode as default,
medium, or high depending on the role detected.
The Port pin is pulled down to ground with a resistor to configure it as upward facing port (UFP) mode.
VBUS detection is implemented to determine a successful attach in UFP mode. The OUT1 and OUT2 pins are
connected to a NOR gate. Active low on both the OUT1 and OUT2 pins advertises high current (3A) in the
attached state which enables the VUSB_5V0 power switch to provide the VSYS_5V0 supply which powers other
regulators and LDOs.
In UFP mode, the port controller IC constantly presents pull-down resistors on both CC pins. The port controller
IC also monitors the CC pins for the voltage level corresponding to the Type-C mode current advertisement
by the connected DFP. The port controller IC de-bounces the CC pins and waits for VBUS detection before
successfully attaching. As a UFP, the port controller device detects and communicates the advertised current
level of the DFP to the system through the OUT1 and OUT2 GPIOs.
The AM243x LP power requirement is 5 V at 3A and if the source is not capable of providing the required
power, the output at the NOR gate becomes low that disables the VUSB_5V0 power switch. Therefore, if the
power requirement is not met, all power supplies except VCC3V3_TA will remain in the off state. The board gets
powered on completely only when the source can provide 5 V at 3A.
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Figure 3-1. Type-C CC Configuration
Table 3-1. Current Sourcing Capability and State of USB Type-C Cable
OUT1 OUT2 Advertisement
H H Default current in unattached state
H L Default current in attached state
L H Medium current (1.5A) in attached state
L L High current (3.0A) in attached state
The AM243x LaunchPad includes a power solution based on discrete regulators for each of the power rails.
During the initial stage of the power supply, 5 V supplied by the type-C USB connector is used to generate all of
the necessary voltages required by the LaunchPad.
Figure 3-2. USB Type-C Power Input
Discrete DC-DC buck regulators and LDOs are used to generate the supplies required for the AM243x system
on a chip (SoC) and other peripherals
Two DC-DC buck regulators (TPS62822) are used to generate the 3.3 V main supply and VDD_CORE_0V85
from the 5 V input supply.
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3.1.2 Power Status LED's
Multiple power-indication LED's are provided on-board to indicate to users the output status of major supplies.
The LED's indicate power across various domains as shown in Table 3-2.
Table 3-2. Power Status LED's
Name Default Status Operation Function
LD9 OFF VSYS_5V0_ERR Power error indication for voltage - VUSB_5V0
LD7 ON VSYS_5V0 Power indicator for voltage - VSYS_5V0
LD6 ON VSYS_3V3 Power indicator for voltage -VSYS_3V3
LD8 ON VDD_CORE_0V85 Power indicator for voltage - VDD_CORE_0V85
LD11 OFF XDS110_PROG_STAZ1 LED will glow after XDS configuration
LD10 OFF XDS110_PROG_STAZ2
Figure 3-3. Power Status LED's
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3.1.3 Power Tree
Figure 3-4. Power Tree Diagram of AM243x LaunchPad
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3.1.4 Power Sequence
Figure 3-5. Power Sequence
3.2 Push Buttons
The LaunchPad supports multiple user push buttons that provide reset inputs and user interrupts to the
processor.
Table 3-3 lists the push buttons that are placed on the top side of the AM243x LaunchPad board.
Table 3-3. LaunchPad Push Buttons
SL # Push Button Signal Function
1 SW1 MCU_PORz PORz Reset input
2 SW2 MCU_RESETz MCU warm reset input
3 SW3 SoC_RESET_REQz SoC warm reset input
4 SW4 USER_INTn User interrupt input
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3.3 Boot Mode Selection
BOOTMODE[9:3] for the AM243x are selected by a DIP switch (SW4) or the test automation header. The
remaining BOOTMODE[2:0] and BOOTMODE[12:10] are selected through the use of resistors. The test
automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. For more
details about the test automation header, see Section 4.16. The supported boot modes are as follows:
• QSPI
• MMC - μSDCard (no direct support)
• Universal asynchronous receiver/transmitter (UART)
• USB-DFU
• No-boot
Table 3-4. Boot-Mode Selection Table
Boot Modes Supported SW4.1 SW4.2 SW4.3 SW4.4 SW4.5 SW4.6 SW4.7
QSPI Flash 0 1 0 0 0 1 0
MMC1/SD Card 0 0 0 1 0 0 1
UART 1 1 1 0 0 0 0
USB -DFU 0 1 0 1 0 0 0
No Boot 1 1 1 1 0 0 0
Figure 3-6. Boot-Mode DIP Switch
Note
SW4.8 of the DIP switch remains unused.
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4 Hardware Description
4.1 Functional Block Diagram
Figure 4-1. AM243x LaunchPad Functional Block Diagram
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4.2 BoosterPack Headers
Figure 4-2. BoosterPack Header Pinout
The AM243x LaunchPad supports two fully independent BoosterPack XL connectors. BoosterPack site #1
(J1/J3, J2/J4) is located in between the SoC and the bootmode DIP switch. BoosterPack site #2 (J5/J7, J6/J8)
is located in between the SoC and the RJ45 connectors. The GPIO pin numbers as well as the the BoosterPack
compliant features are listed in Figure 4-2. Each GPIO has multiple functions available through the GPIO mux.
The signals connected from the SoC to the BoosterPack headers include:
• SPI0 and SPI3
• UART0 and UART2
• I2C0 and I2C1
• MMC1
• ADC0
• EHRPWM0_A/B and EHRPWM1_A/B
• GPIO's
• 5 V and 3.3 V power supplies
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A BoosterPack that is connected to site #1 will be powered by the AM243x. A BoosterPack that is connected to
site #2 can either be powered by the AM243x or have it's power sourced from the Boosterpack itself depending
on whether or not the 0Ω resistors (R161, R163) are mounted. The resistors are mounted by default as shown in
Figure 4-3, the AM243x will provide the VSYS_3V3 and VSYS_5V0 source voltage for the BoosterPack. When
left unpopulated, the BoosterPack will be required to source its own power.
Note
Sourcing power to the LaunchPad from the BoosterPack should not be attempted.
Table 4-1. BoosterPack Power Sourcing for BoosterPack Site #2
Function
Mount R161 and R163
(Default) Unmount R161 and R163
Power to BoosterPack sourced from LaunchPad ✔
Power to BoosterPack sourced from the BoosterPack ✔
Figure 4-3. Site #2 BoosterPack Header
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4.2.1 Pinmux for BoosterPack
Figure 4-4. 80 Pin BoosterPack Pinout
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The various pinmux options in different modes for Booterpack Connector pins are given below. The default modes of the pins are shown in Figure 4-2
and in bold in the tables below.
Table 4-2. Pinmux Options for J1/J3 Connector - Site 1
Connect
or
Pinout Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J1.1
J3.21
J1.2 ADC_AIN0 GPIO1_8
0
J3.22
J1.3 GPMC0_ADC0 FSI_RX2_CLK UART2_RXD EHRPWM0_SYNC
I
TRC_CLK GPIO0_1
5
J3.23 ADC0_AIN2 GPIO1_8
2
J1.4 GPMC0_AD1 FSI_RX2_D0 UART2_TXD EHRPWM0_SYNC
0
TRC_CTL GPIO0_1
6
PRG0_PWM2_TZ_O
UT
J3.24 ADC0_AIN3 GPIO1_8
3
J1.5 PRG0_PRU0_GP
O12
PRG0_PRU0_GPI1
2
PRG0_RGMII1_TD1 PRG0_PWM0_A0 GPIO1_1
2
GPMC0_A14
J3.25 ADC_AIN4 GPIO1_8
4
J1.6 ADC0_AIN1 GPIO1_8
1
J3.26 ADC0_AIN5 GPIO1_8
5
J1.7 PRG0_PRU0_GP
O16
PRG0_PRU0_GPI1
6
PRG0_RGMII1_TXC PRG0_PWM0_A2 SPI3_CLK GPIO1_1
6
GPMC0_A4
J3.27 ADC0_AIN6 GPIO1_8
6
J1.8 PRG0_PRU0_GP
O18
PRG0_PRU0_GPI1
8
PRG0_IEP0_EDC_LATCH
_IN0
PRG0_PWM0_TZ
_IN
CPTS0_HW1TSPU
SH
CP_GEMAC_CPTS0_HW1TSP
USH
HRPWM8_A GPIO1_1
8
UART4_CT
Sn
GPMC0_A5 UART2_RX
D
J3.28 ADC0_AIN7 GPIO1_8
7
J1.9 I2C1_SCL CPTS0_HW1TSPU
SH
TIMER_IO0 SPI2_CS1 DDR0_IO_PLL_TESTOUT0P DDR0_IO_PLL_TESTOUT1P GPIO1_6
6
J3.29 MCAN0_TX UART4_RXD TIMER_IO2 SYNC2_OUT SPI4_CS1 GPIO1_6
0
EQEP2_I UART0_DTRn
J1.10 I2C1_SDA CPTS0_HW2TSPU
SH
TIMER_IO1 SPI2_CS2 DDR0_IO_PLL_REFCLK_TES
T0P
DDR0_IO_PLL_REFCLK_TES
T1P
GPIO1_6
7
J3.30 MCAN0_RX UART4_TXD TIMER_IO3 SYNC3_OUT SPI4_CS2 GPIO1_6
1
EQEP2_S UART0_RIn
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Table 4-3. Net Name in Schematic and Package Signal Name for J1/J3 Connector
Connector Pinout Net Name in Schematic Package Signal Name
J1.1 VSYS_3V3
J3.21 VSYS_5V0
J1.2 BP_ADC0_AINN0 ADC_AIN0
J3.22 DGND
J1.3 MAIN_UART2_RXD GPMC0_AD0
J3.23 BP_ADC0_AIN2 ADC0_AIN2
J1.4 MAIN_UART2_TXD GPMC0_AD1
J3.24 BP_ADC0_AIN3 ADC0_AIN3
J1.5 GPIO1_12 PRG0_PRU0_GPO12
J3.25 BP_ADC0_AIN4 ADC0_AIN4
J1.6 BP_ADC0_AIN1 ADC0_AIN1
J3.26 BP_ADC0_AIN5 ADC0_AIN5
J1.7 SPI3_CLK PRG0_PRU-_GPO16
J3.27 BP_ADC0_AIN6 ADC0_AIN6
J1.8 GPIO1_18 PRG0_PRU0_GPO18
J3.28 BP_ADC0_AIN7 ADC0_AIN7
J1.9 SOC_I2C1_SCL I2C1_SCL
J3.29 SYNC2_OUT MCAN0_TX
J1.10 SOC_I2C1_SDA I2C1_SDA
J3.30 SYNC3_OUT MCAN0_RX
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Table 4-4. Pinmux Options for J2/J4 Connector - Site 1
Connector
Pinout
Net Name in
Schematic
Package Signal
Name Mode0 Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Mode7 Mode8 Mode9 Mode10
J4.40 EHRPWM0_A GPMC0_AD3 GPMC0_AD3 FSI_RX3_CLK UART3_RXD EHRPWM0_A TRC_DATA1 GPIO0_18 PRG0_PWM2_
A0
J2.20 DGND
J4.39 EHRPWM0_B GPMC0_AD4 GPMC0_AD4 FSI_RX3_D0 UART3_TXD EHRPWM0_B TRC_DATA2 GPIO0_82 PRG0_PWM2_
B0
J2.19 GPIO1_3 PRG0_PRU0_G
PO3
PRG0_PRU0_G
PO3
PRG0_PRU0_G
PI3
PRG0_RGMII1_
RD3
PRG0_PWM3_
A2
GPIO1_3 UART3_CTSn
J4.38 EHRPWM1_A GPMC0_AD5 GPMC0_AD5 FSI_RX3_D1 UART3_RTSn EHRPWM1_A TRC_DATA3 GPIO0_83 PRG0_PWM2_
A1
J2.18 SPI3_CS0 PRG0_PRU0_G
PO17
PRG0_PRU0_G
PO17
PRG0_PRU0_G
PI17
PRG0_IEP0_E
DC_SYNC_OU
T1
PRG0_PWM0_
B2
CPTS0_TS_SY
NC
CP_GEMAC_C
PTS0_TS_SYN
C
SPI3_CS0 GPIO1_17 TIMER_IO11 GPMC0_A17
J4.37 EHRPWM1_B GPMC0_AD6 GPMC0_AD6 FSI_RX4_D0 UART4_RXD EHRPWM1_B TRC_DATA4 GPIO0_21 PRG0_PWM2_
B1
J2.17 GPIO1_4 PRG0_PRU0_G
PO4
PRG0_PRU0_G
PO4
PRG0_PRU0_G
PI4
PRG0_RGMII1_
RX_CTL
PRG0_PWM2_
B0
GPIO1_4 GPMC0_A1 UART3_TXD
J4.36 EHRPWM2_A GPMC0_AD8 GPMC0_AD8 FSI_RX0_CLK UART2_CTSn EHRPWM2_A TRC_DATA6 GPIO0_23 PRG0_PWM2_
A2
J2.16 BP_CONN_1_P
ORZ
J4.35 EHRPWM2_B GPMC0_AD9 GPMC0_AD9 FSI_RX0_D0 UART3_CTSn EHRPWM2_B TRC_DATA7 GPIO0_24 PRG0_PWM2_
B2
J2.15 SPI3_D0 PRG0_PRU0_G
PO13
PRG0_PRU0_G
PO13
PRG0_PRU0_G
PI13
PRG0_RGMII1_
TD2
PRG0_PWM0_
B0
SPI3_D0 GPIO1_13 GPMC0_A15
J4.34 EHRPWM0_TZ
N_IN0
GPMC0_AD2 GPMC0_AD2 FSI_RX2_D1 UART2_RTSn EHRPWM_TZn
_IN0
TRC_DATA0 GPIO0_17 PRG0_PWM2_
TZ_IN
J2.14 SPI3_D1 PRG0_PRU0_G
PO14
PRG0_PRU0_G
PO14
PRG0_PRU0_G
PI14
PRG0_RGMII1_
TD3
PRG0_PWM0_
A1
SPI3_D1 GPIO1_14 GPMC0_A3
J4.33 GPIO1_0 PRG0_PRU0_G
PO0
PRG0_PRU0_G
PO0
PRG0_PRU0_G
PI0
PRG0_RGMII1_
RD0
PRG0_PWM3_
A0
GPIO1_0 UART2_CTSn
J2.13 GPIO1_5 PRG0_PRU0_G
PO5
PRG0_PRU0_G
PO5
PRG0_PRU0_G
PI5
PRG0_PWM3_
B2
GPIO1_5 UART3_RTSn
J4.32 GPIO1_1 PRG0_PRU0_G
PO1
PRG0_PRU0_G
PO1
PRG0_PRU0_G
PI1
PRG0_RGMII1_
RD1
PRG0_PWM3_
B0
GPIO1_1 UART2_TXD
J2.12 SPI3_CS1 PRG0_PRU0_G
PO15
PRG0_PRU0_G
PO15
PRG0_PRU0_G
PI15
PRG0_RGMII1_
TX_CTL
PRG0_PWM0_
B1
SPI3_CS1 GPIO1_15 GPMC0_A16
J4.31 GPIO1_2 PRG0_PRU0_G
PO2
PRG0_PRU0_G
PO2
PRG0_PRU0_G
PI2
PRG0_RGMII1_
RD2
PRG0_PWM2_
A0
GPIO1_2 GPMC0_A0 UART2_RTSn
J2.11 GPIO1_20 PRG0_PRU1_G
PO0
PRG0_PRU1_G
PO0
PRG0_PRU1_G
PI0
PRG0_RGMII2_
RD0
GPIO1_20 EQEP0_A UART5_CTSn
www.ti.com Hardware Description
SPRUJ12B – AUGUST 2021 – REVISED OCTOBER 2022
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AM243x LaunchPad™ Development Kit User's Guide 19
Copyright © 2022 Texas Instruments Incorporated

Table 4-5. Net Name in Schematic and Package Signal Name for J2/J4 Connector
Connector Pinout Net Name in Schematic Package Signal Name
J4.40 EHRPWM0_A GPMC0_AD3
J2.20 DGND
J4.39 EHRPWM0_B GPMC0_AD4
J2.19 GPIO1_3 PRG0_PRU0_GPO3
J4.38 EHRPWM1_A GPMC0_AD5
J2.18 SPI3_CS0 PRG0_PRU0_GPO17
J4.37 EHRPWM1_B GPMC0_AD6
J2.17 GPIO1_4 PRG0_PRU0_GPO4
J4.36 EHRPWM2_A GPMC0_AD8
J2.16 BP_CONN_1_PORZ
J4.35 EHRPWM2_B GPMC0_AD9
J2.15 SPI3_D0 PRG0_PRU0_GPO13
J4.34 EHRPWM0_TZN_IN0 GPMC0_AD2
J2.14 SPI3_D1 PRG0_PRU0_GPO14
J4.33 GPIO1_0 PRG0_PRU0_GPO0
J2.13 GPIO1_5 PRG0_PRU0_GPO5
J4.32 GPIO1_1 PRG0_PRU0_GPO1
J2.12 SPI3_CS1 PRG0_PRU0_GPO15
J4.31 GPIO1_2 PRG0_PRU0_GPO2
J2.11 GPIO1_20 PRG0_PRU1_GPO0
Hardware Description www.ti.com
20 AM243x LaunchPad™ Development Kit User's Guide SPRUJ12B – AUGUST 2021 – REVISED OCTOBER 2022
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Copyright © 2022 Texas Instruments Incorporated