Cmsemicon BAT32A2 9 Series User manual

BAT32A2x9 User Manual | Chapter 1 CPU
www.mcu.com.cn 1 / 1149 Rev.1.00
BAT32A2x9 User Manual
An ultra-low-power 32-bit microcontroller based on the ARM®Cortex®-M0+
Rev 1.00
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Documentation Instructions
This manual is a technical reference manual for BAT32A239/BAT32A279 microcontroller products, and the
technical reference manual is an application note on how to use this series of products, including the structure,
functional description, and function description of each functional module. Details such as operating modes and
register configuration.
The Technical Reference Manual is a description of all functional modules in this series of products, please
refer to the data sheet for the description of the characteristics of the product (i.e. the function carrying situation).
The data sheet information is as follows:
BAT32A239xx: BAT32A239_datasheet_vx.xx. pdf
BAT32A279xx: BAT32A279_datasheet_vx.xx. pdf
Usually in the early stage of chip selection, the first thing to see is to look at the data sheet to evaluate whether
the product can meet the functional requirements of the design; After basically selecting the required product, it is
necessary to check the technical reference manual to determine whether the working mode of each functional
module meets the requirements; When determining that the selection enters the programming design phase, a
detailed technical reference manual is required to understand the specific implementation of each function and the
register configuration. Refer to the data sheet when designing your hardware for information such as voltage,
current, drive capability, and pin assignment.
For a detailed description of the Cortex-M0+ core, SysTick timer, and NVIC, please refer to the documentation
for the corresponding ARM.

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BAT32A2x9 User Manual Chapter List
BAT32A239xx
BAT32A279xx
Chapter 1: CPU
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Chapter 2: Pin Functions
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Chapter 3: System structure
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Chapter 4: Clock generation circuit
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Chapter 5: Hardware Divider
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Chapter 6: Universal timer unit Timer4/8
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Chapter 7: TimerA
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Chapter 8: TimerB
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Chapter 9: TimerC
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Chapter 10: TimerM
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Chapter 11: Real-Time Clock
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Chapter 12: 15-Bit Interval Timer
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Chapter 13: Clock output/buzzer output control circuitry
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Chapter 14: Watchdog Timer
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Chapter 15: A/D Converter
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Chapter 16: D/A Converters
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Chapter 17: Comparator
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Chapter 18: Programmable Gain Amplifier
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Chapter 19: Universal Serial Communication Unit
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Chapter 20: Serial Interface IICA
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Chapter 21: Serial Interface SPI
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Chapter 22: CAN Control
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Chapter 23: LCD Bus Interface
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Chapter 24: Enhanced DMA
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Chapter 25: Linkage Controller
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Chapter 26: Interrupt function
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Chapter 27: Key Interrupt Function
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Chapter 28: Standby Function
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Chapter 29: Reset Function
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Chapter 30: Power-on Reset Circuit
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Chapter 31: Voltage Detection Circuit
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Chapter 32: Safety Functions
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Chapter 33: Temperature sensor and internal reference voltage
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Chapter 34: Option Bytes
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Chapter 35: Flash Control
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Index
Documentation Instructions...............................................................................................................................2
Chapter 1CPU.................................................................................................................................................25
1.1 overview.........................................................................................................................................25
1.2 Cortex-M0+ core features..............................................................................................................25
1.3 Debug features..............................................................................................................................25
1.4 SWD interface pin..........................................................................................................................27
1.5 ARM reference documentation......................................................................................................28
Chapter 2Pin function .....................................................................................................................................29
2.1 Port capabilities .............................................................................................................................29
2.2 Port multiplexing function ..............................................................................................................29
2.3 Registers that control port functionality.........................................................................................30
2.3.1 Port Mode Register (PMxx)......................................................................................................33
2.3.2 Port register (Pxx).....................................................................................................................34
2.3.3 Port Set Control Register (PSETxx).........................................................................................35
2.3.4 Port Clear Control Register (PCLRxx)......................................................................................36
2.3.5 Pull-up resistor selection register (PUxx).................................................................................37
2.3.6 Port input mode register (PIMxx)..............................................................................................38
2.3.7 Port output mode register (POMxx)..........................................................................................39
2.3.8 Port Mode Control Register (PMCxx).......................................................................................40
2.3.9 Port read-back register (PREADxx). ........................................................................................41
2.3.10 Peripheral I/O redirect register 0 (PIOR0)................................................................................42
2.3.11 Peripheral I/O redirect register 1 (PIOR1)................................................................................43
2.3.12 Peripheral I/O redirect register 2(PIOR2).................................................................................44
2.3.13 Peripheral I/O redirect register 3(PIOR3).................................................................................45
2.3.14 Peripheral I/O redirect register 4 (PIOR4)................................................................................46
2.3.15 Global Digital Input Disable Register (GDIDIS)........................................................................47
2.4 Unused pin handling......................................................................................................................48
2.5 Register settings when using the multiplexing function ................................................................49
2.5.1 Basic principle when using the multiplexing feature ................................................................49
2.5.2 Examples of register settings using the port function and the multiplexing function...............50
Chapter 3System structure.............................................................................................................................69
3.1 overview.........................................................................................................................................69
3.2 System address partition...............................................................................................................70
3.3 Peripheral address assignment.....................................................................................................72
Chapter 4Clock generation circuit...................................................................................................................73
4.1 Function of the clock generation circuit.........................................................................................73
4.2 Structure of the clock generation circuit........................................................................................75

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4.3 Control Registers of the clock generation circuit...........................................................................78
4.3.1 Clock operating mode control register (CMC)..........................................................................78
4.3.2 System Clock Control Register (CKC). ....................................................................................80
4.3.3 Clock Operating State Control Register (CSC)........................................................................81
4.3.4 PLL Control Register (PLLCR) for System Clock.....................................................................82
4.3.5 The state register (OSTC) of the oscillation settling time counter ...........................................83
4.3.6 Oscillation settling time selection register (OSTS)...................................................................85
4.3.7 Peripheral enable registers 0, 1, 2, 3 (PER0, PER1, PER2, P ER2 PER3)............................86
4.3.8 Subsystem clock supply mode control register (OSMC)..........................................................92
4.3.9 Frequency Selection Register (HOCODIV) for high-speed internal oscillators .......................93
4.3.10 Trimming Register (HIOTRM) for high-speed internal oscillator..............................................94
4.3.11 Subsystem Clock Select Register (SUBCKSEL) .....................................................................95
4.3.12 Master System Clock Control Register (MCKC)......................................................................96
4.4 System clock oscillation circuit......................................................................................................97
4.4.1 X1 oscillation circuit..................................................................................................................97
4.4.2 XT1 oscillation circuit................................................................................................................97
4.4.3 High-speed internal oscillator.................................................................................................101
4.4.4 Low-speed internal oscillator..................................................................................................101
4.5 Clock generation circuit operation...............................................................................................102
4.6 Clock control................................................................................................................................104
4.6.1 Example of setting up a high-speed internal oscillator...........................................................104
4.6.2 Example of setting up the X1 oscillation circuit......................................................................106
4.6.3 Example of setting up the XT1 oscillation circuit....................................................................107
4.6.4 State transition graph of the CPU clock .................................................................................108
4.6.5 Conditions before CPU clock transfer and processing after transfer.....................................114
4.6.6 Time required to switch between the CPU clock and the master system clock ....................116
4.6.7 Conditions before clock oscillation stops................................................................................117
4.7 High-speed internal vibration correction function........................................................................118
4.7.1 High-speed internal vibration self-adjustment function..........................................................118
4.7.2 Register description................................................................................................................119
4.7.3 Description of the operation....................................................................................................120
4.7.4 Precautions for use.................................................................................................................123
4.8 Vibration stop detection circuit ....................................................................................................124
4.8.1 Vibration stops the function of the detection circuit................................................................124
4.8.2 Composition of the vibration-stop detection circuit.................................................................124
4.8.3 The register used by the oscillator stops detection circuit .....................................................125
4.8.4 The operation of the vibration stop detection circuit ..............................................................127
4.8.5 Precautions for vibration stop detection function...................................................................128
Chapter 5Hardware divider...........................................................................................................................129

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5.1 Features.......................................................................................................................................129
5.2 Feature description......................................................................................................................129
5.3 Registers for the hardware divider ..............................................................................................129
5.3.1 DIVIDEND...............................................................................................................................130
5.3.2 Divider (DIVISAR)...................................................................................................................130
5.3.3 Quotient ..................................................................................................................................130
5.3.4 REMAINDER ..........................................................................................................................130
5.3.5 Status register (STATUS).......................................................................................................131
Chapter 6Universal timer unit Timer4/8........................................................................................................132
6.1 Functions of the universal timer unit............................................................................................134
6.1.1 Stand-alone channel operation function.................................................................................134
6.1.2 Multi-channel linkage operation function................................................................................136
6.1.3 8-bit timer operation function (channel 1 and channel 3 of unit 0 only).................................137
6.1.4 LIN-bus support function (limited to channel 3 of unit 0)........................................................137
6.2 Structure of a universal timer unit................................................................................................138
6.2.1 List of general-purpose timer unit registers............................................................................141
6.2.2 Timer count register mn (TCRmn)..........................................................................................144
6.2.3 Timer data register mn (TDRmn)............................................................................................146
6.3 Control registers of the universal timer unit.................................................................................147
6.3.1 Peripheral enable register 0 (PER0). .....................................................................................148
6.3.2 Timer clock selection register m (TPSm)...............................................................................149
6.3.3 Timer mode register mn (TMRmn).........................................................................................152
6.3.4 Timer status register mn (TSRmn).........................................................................................156
6.3.5 Timer channel enable status register m (TEm)......................................................................157
6.3.6 Timer channel start register m(TSm)......................................................................................158
6.3.7 Timer channel stop register m(TTm)......................................................................................159
6.3.8 Timer input and output selection register (TIOS0).................................................................160
6.3.9 Timer output enable register m (TOEm).................................................................................161
6.3.10 Timer output register m (TOm)...............................................................................................162
6.3.11 Timer output level register m(TOLm). ....................................................................................163
6.3.12 Timer output mode register m (TOMm)..................................................................................164
6.3.13 Input Select Control Register (ISC)........................................................................................165
6.3.14 Noise filter enable registers (NFEN1/NFEN2)........................................................................166
6.3.15 Registers that control the function of the timer input/output pin ports....................................167
6.4 The basic rules of the universal timer unit...................................................................................168
6.4.1 The basic rules of the multi-channel linkage operation function............................................168
6.4.2 Timer channel start register m(TSm)......................................................................................170
6.4.3 The basic rules for the 8-bit timer to operate the function (limited to Channel 1 and Channel 3
of Unit 0). 171

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6.5 The operation of the counter.......................................................................................................172
6.5.1 Count clock (fTCLK). ..............................................................................................................172
6.5.2 The start timing of the counter................................................................................................174
6.5.3 The operation of the counter ..................................................................................................175
6.6 Control of the channel output (TOmn pin)...................................................................................180
6.6.1 Structure of the TOmn pin output circuit.................................................................................180
6.6.2 Output setting of the TOmn pin..............................................................................................181
6.6.3 Considerations for channel output operation .........................................................................182
6.6.4 one-time operation of the TOmn bit........................................................................................186
6.6.5 About the timer interrupt and TOmn pin output when starting to count.................................187
6.7 Control of the timer input (TImn)..................................................................................................188
6.7.1 Structure of the TImn pin input circuit.....................................................................................188
6.7.2 Noise filters.............................................................................................................................188
6.7.3 Considerations when operating channel input.......................................................................189
6.8 Stand-alone channel operation of the universal timer unit..........................................................190
6.8.1 Operation as an interval timer/square wave output................................................................190
6.8.2 Run as an external event counter ..........................................................................................194
6.8.3 Operation as a divider.............................................................................................................197
6.8.4 Operation as input pulse interval measurements...................................................................200
6.8.5 Operation as input signal high and low level width measurements.......................................203
6.8.6 Runs as a delay counter.........................................................................................................207
6.9 Multi-channel linkage operation function of the universal timer unit...........................................210
6.9.1 Operation as a single-trigger pulse output function................................................................210
6.9.2 Operates as a PWM function..................................................................................................217
6.9.3 Operation as a multi-PWM output function.............................................................................224
6.10 Considerations when using a universal timer unit.......................................................................232
6.10.1 Considerations when using timer outputs..............................................................................232
Chapter 7Timer A..........................................................................................................................................233
7.1 Function of timer A.......................................................................................................................233
7.2 Structure of timer A......................................................................................................................234
7.3 Controls the registers of timer A..................................................................................................235
7.3.1 Peripheral enable register 1 (PER1). .....................................................................................236
7.3.2 The subsystem clock provides a mode control register (OSMC)...........................................237
7.3.3 Timer A counts register 0 (TA0).............................................................................................238
7.3.4 Timer A controls register 0 (TACR0)......................................................................................239
7.3.5 Timer AI/O control register 0 (TAIOC0)..................................................................................240
7.3.6 Timer A controls register 0 (TAMR0)......................................................................................242
7.3.7 Timer A event pin select register 0 (TAISR0).........................................................................243
7.3.8 Port mode register x (PMx).....................................................................................................244

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7.4 Operation of timer A ....................................................................................................................245
7.4.1 Overrides to reload registers and counters............................................................................245
7.4.2 Timer mode.............................................................................................................................246
7.4.3 Pulse output mode..................................................................................................................247
7.4.4 Event counter pattern.............................................................................................................248
7.4.5 Pulse width measurement mode............................................................................................250
7.4.6 Pulse period measurement mode ..........................................................................................251
7.4.7 Collaboration with EVENTC ...................................................................................................252
7.4.8 Output settings for each mode ...............................................................................................252
7.5 Considerations when using Timer A............................................................................................253
7.5.1 Start and stop control of counting...........................................................................................253
7.5.2 Access to flags (TEDGF bits and TUNDF bits of the TACR0 register)..................................253
7.5.3 Access to the Counting register..............................................................................................253
7.5.4 Change in Operational mode..................................................................................................254
7.5.5 Setup steps for TAO pins and TAIO pins...............................................................................255
7.5.6 When timer A is not used .......................................................................................................255
7.5.7 Timer A runs the stop of the clock..........................................................................................255
7.5.8 Setup steps for deep sleep mode (event counter mode).......................................................256
7.5.9 Functional limitations in deep sleep mode (event counter mode only)..................................256
7.5.10 Forced count stop via the TSTOP bit.....................................................................................256
7.5.11 Digital filters............................................................................................................................256
7.5.12 The case where fIL is selected as the count source..............................................................256
Chapter 8Timer B..........................................................................................................................................257
8.1 Function of timer B.......................................................................................................................257
8.2Structure of timer B......................................................................................................................258
8.3 Control registers of timer B..........................................................................................................259
8.3.1 Peripheral enables register 1 (PER1).....................................................................................260
8.3.2 Timer B mode register (TBMR). .............................................................................................261
8.3.3 Timer B counts the control register (TBCNTC)......................................................................262
8.3.4 Timer B Control Register (TBCR)...........................................................................................263
8.3.5 Timer B interrupt enable register (TBIER)..............................................................................264
8.3.6 Timer B status register (TBSR)..............................................................................................265
8.3.7 Timer BI/O Control Register (TBIOR).....................................................................................268
8.3.8 Timer B counter (TB)..............................................................................................................270
8.3.9 Timer B universal registers A, B, C, D (TBGRA, TBGRB, TBGRC, TBGRD)........................271
8.3.10 Port registers and port mode registers...................................................................................273
8.4 Operation of timer B ....................................................................................................................274
8.4.1 Common things about multiple patterns and features ...........................................................274
8.4.2 Timer mode (input capture function) ......................................................................................279

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8.4.3 Timer mode (output comparison function)..............................................................................282
8.4.4 PWM mode.............................................................................................................................286
8.4.5 Phase count mode..................................................................................................................290
8.5 Timer B interrupt..........................................................................................................................293
8.6 Considerations when using timer B.............................................................................................295
8.6.1 Phase difference, overlap, and pulse width in phase count mode.........................................295
8.6.2 Switching modes.....................................................................................................................295
8.6.3 Count the switching of the source..........................................................................................295
8.6.4 Setup steps for TBIO0 pins and TBIO1 pins..........................................................................296
8.6.5 External clocks TBBCLK0 and TBBCLK1..............................................................................296
8.6.6 Read and write access to SFR...............................................................................................296
8.6.7 Stop counting when the input snap runs................................................................................297
Chapter 9Timer C .........................................................................................................................................298
9.1 Function of timer C ......................................................................................................................298
9.2 Structure of timer C .....................................................................................................................299
9.3 Control registers of timer C..........................................................................................................300
9.3.1 Peripheral enable register 1 (PER1). .....................................................................................300
9.3.2 Timer C count register (TC)....................................................................................................301
9.3.3 Timer C count buffer register (TCBUF)..................................................................................301
9.3.4 Timer C controls register 1 (TCCR1)......................................................................................302
9.3.5 Timer C controls register 1 (TCCR2)......................................................................................303
9.3.6 Timer C status register (TCSR)..............................................................................................304
9.4 Operation of timer C....................................................................................................................305
9.4.1 Count the sources...................................................................................................................305
9.4.2 Timer C starts counting the actions........................................................................................305
9.4.3 Timer C counts stopped actions.............................................................................................308
9.4.4 Enter the capture motion........................................................................................................309
9.4.5 Timer C counts the reset action..............................................................................................310
9.4.6 Interrupt of timer C..................................................................................................................312
9.5 Precautions when using Timer C ................................................................................................313
9.5.1 Read and write registers.........................................................................................................313
9.5.2 Overflow interruption...............................................................................................................313
9.5.3 Input capture and timer C count reset action.........................................................................313
9.5.4 Timer C and Timer M, comparator 1 are linked .....................................................................313
Chapter 10 Timer M...........................................................................................................................314
10.1 Function of timer M......................................................................................................................314
10.2 Structure of timer M.....................................................................................................................315
10.3 Control register of timer M...........................................................................................................316
10.3.1 Peripheral enable register 1 (PER1). .....................................................................................317

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10.3.2 Timer M EVENTC register (TMELC)......................................................................................318
10.3.3 Timer M Start Register (TMSTR)............................................................................................319
10.3.4 Timer M mode register (TMMR).............................................................................................320
10.3.5 Timer M PWM function select register (TMPMR)...................................................................321
10.3.6 Timer M function control register (TMFCR)............................................................................322
10.3.7 Timer M output master enable register 1 (TMOER1).............................................................323
10.3.8 Timer M output main enable register 2 (TMOER2)................................................................324
10.3.9 Timer M output control register (TMOCR)..............................................................................325
10.3.10 The timer M digital filter function selects register i (TMDFi) (i=0, 1)........................................328
10.3.11 Timer M controls register i (TMCRi) (i=0, 1)............................................................................330
10.3.12 Timer M I/O control register Ai (TMIORAi)(i =0, 1).................................................................335
10.3.13 Timer M I/O control register Ci (TMIORCi)(i=0, 1)..................................................................337
10.3.14 Timer M status register 0 (TMSR0)........................................................................................339
10.3.15 Timer M status register 1 (TMSR1)........................................................................................345
10.3.16 Timer M interrupt enable register i (TMIERi) (i=0, 1)..............................................................351
10.3.17 The timer MPWM function outputs level control register i (TMPOCRi) (i=0, 1). .....................352
10.3.18 Timer M counter i(TMi) (i=0, 1)...............................................................................................353
10.3.19 Timer M General Purpose registers Ai, Bi, Ci, Di...................................................................355
10.3.20 Port mode registers (PMxx, PMCxx)......................................................................................364
10.4 Common things about multiple patterns......................................................................................365
10.4.1 Counting sources....................................................................................................................365
10.4.2 The buffer operation ...............................................................................................................366
10.4.3 Synchronous Operation..........................................................................................................369
10.4.4 Forced cutoff of the pulse output............................................................................................370
10.4.5 Event inputs from the Event Linkage Controller (EVENTC)...................................................372
10.4.6 Event output to the Event Linkage Controller (EVENTC)/Data Transfer Controller (DMA)...372
10.5 Operation of timer M....................................................................................................................373
10.5.1 Enter the capture function ......................................................................................................373
10.5.2 Output comparison function....................................................................................................378
10.5.3 PWM function..........................................................................................................................384
10.5.4 Reset synchronous PWM mode.............................................................................................388
10.5.5 Complementary PWM mode ..................................................................................................391
10.5.6 PWM3 mode...........................................................................................................................395
10.6 Timer M interrupt.........................................................................................................................398
10.7 Considerations when using timer M............................................................................................401
10.7.1 Read and write access to SFR...............................................................................................401
10.7.2 Switching modes.....................................................................................................................401
10.7.3 Counting sources....................................................................................................................402
10.7.4 Enter the capture function ......................................................................................................402

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10.7.5 Configuration steps (i=0, 1) for TMIOAi, TMIOBi, TMIOCi, TMIODi pins ..............................402
10.7.6 External clock TMCLK............................................................................................................403
10.7.7 Complementary PWM mode ..................................................................................................403
10.8 PWMOP.......................................................................................................................................408
10.8.1 Features of PWMOP...............................................................................................................409
10.8.2 Registers for PWMOP ............................................................................................................409
10.8.3 Operation of PWMOP.............................................................................................................416
10.8.4 Precautions.............................................................................................................................437
Chapter 11 Real-time clock..............................................................................................................438
11.1 The function of a real-time clock .................................................................................................438
11.2 The structure of the real-time clock.............................................................................................438
11.3 Control Registers the real-time clock ..........................................................................................440
11.3.1 Peripheral enable register 0 (PER0). .....................................................................................441
11.3.2 Real-time clock selection register (RTCCL)...........................................................................442
11.3.3 Real-time clock control register 0 (RTCC0). ..........................................................................443
11.3.4 Real-time clock control register 1 (RTCC1). ..........................................................................444
11.3.5 Clock Error Correction Register (SUBCUD)...........................................................................446
11.3.6 Seconds Count Register (SEC)..............................................................................................447
11.3.7 Minute Count Register (MIN)..................................................................................................447
11.3.8 Hour Count Register (HOUR).................................................................................................448
11.3.9 Day count register (DAY)........................................................................................................450
11.3.10 Week Count Register (WEEK). ..............................................................................................451
11.3.11 Month count register (MONTH)..............................................................................................452
11.3.12 Year Count Register (YEAR)..................................................................................................452
11.3.13 Alarm clock minute register (ALARMWM)..............................................................................453
11.3.14 Alarm hour register (ALARMWH)...........................................................................................453
11.3.15 Alarm Clock Week Register (ALARMWW).............................................................................453
11.3.16 Port mode registers and port registers...................................................................................454
11.4 Operation of a real-time clock .....................................................................................................455
11.4.1 The operation of the real-time clock begins...........................................................................455
11.4.2 Start the transfer of sleep mode after running........................................................................456
11.4.3 Read and write to the real-time clock counter........................................................................457
11.4.4 Alarm settings for the real-time clock.....................................................................................459
11.4.5 1Hz output of the real-time clock............................................................................................460
11.4.6 An example of clock error correction for a real-time clock.....................................................461
Chapter 12 15-bit interval timer........................................................................................................463
12.1 1Function of 5-bit interval timer...................................................................................................463
12.2 Structure of the 15-bit interval timer..............................................................................................463
12.3 control Registers of the 15-bit interval timer................................................................................464

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12.3.1 Peripheral enable register 0 (PER0). .....................................................................................464
12.3.2 Real-time clock selection register (RTCCL)...........................................................................465
12.3.3 Control Register (ITMC) for 15-bit interval timers ..................................................................466
12.4 15-bit interval timer operation......................................................................................................467
12.4.1 Operation sequence of the 1 5-bit interval timer....................................................................467
12.4.2 After returning from sleep mode, the operation of the counter begins and then transition to
sleep mode again....................................................................................................................................468
Chapter 13 Clock output/buzzer output control circuitry..................................................................469
13.1 the function of controls circuitry of Clock output/buzzer output ..................................................469
13.2 Structure of the clock output/buzzer output control circuit..........................................................470
13.3 control Registers of the clock output/buzzer output control circuitry...........................................470
13.3.1 Clock output select register n (CKSn)....................................................................................470
13.3.2 Control Registers of the clock output/buzzer output pin port function...................................472
13.4 the operation of Clock output/buzzer output controls circuitry....................................................473
13.4.1 Operation of the output pins...................................................................................................473
13.5 Considerations for clock output/buzzer output control circuitry ..................................................473
Chapter 14 Watchdog timer.............................................................................................................474
14.1 The function of the watchdog timer.............................................................................................474
14.2 Structure of the watchdog timer ..................................................................................................474
14.3 Control registers of the watchdog timer ......................................................................................476
14.3.1 The Watchdog Timer's enable Register (WDTE)...................................................................476
14.3.2 LockUP Control Register (LOCKCTL) and its Protection Register (PRCR)..........................477
14.3.3 WDTCFG Configuration Register (WDTCFG0/1/2/3)............................................................478
14.4 Operation of the watchdog timer.................................................................................................479
14.4.1 Operational control of the watchdog timer..............................................................................479
14.4.2 Setting of the watchdog timer overflow timer.........................................................................480
14.4.3 The setting during which the watchdog timer window is open...............................................481
14.4.4 Setting of watchdog timer interval interrupts..........................................................................482
14.4.5 Operation of the watchdog timer during LOCKUP.................................................................482
14.4.6 WDTCFG is not configured when the watchdog timer is running..........................................482
Chapter 15 A/D converter.................................................................................................................483
15.1 Functions of the A/D converter....................................................................................................483
15.2 Control registers of the A/D converter.........................................................................................485
15.2.1 Peripheral enable register 0 (PER0). .....................................................................................486
15.2.2 The mode register 0 (ADM0) of the A/D converter.................................................................487
15.2.3 The mode register 1 (ADM1) of the A/D converter.................................................................492
15.2.4 The mode register 2 (ADM2) of the A/D converter.................................................................493
15.2.5 The A/D converter's trigger mode register (ADTRG).............................................................494
15.2.6 Analog input channel specified register (ADS).......................................................................495

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15.2.7 12-bit A/D conversion result register (ADCR). .......................................................................498
15.2.8 8-bit A/D conversion result register (ADCRH)........................................................................499
15.2.9 The conversion result compares the upper limit value of the set register (ADUL)................500
15.2.10 The conversion results compare the lower limit value set register (ADLL)............................500
15.2.11 A/D Sampling Time Control Register (ADNSMP). .................................................................501
15.2.12 A/D sampling time extended register (ADSMPWAIT)............................................................502
15.2.13 A/D Test Register (ADTES)....................................................................................................503
15.2.14 A/D status register (ADFLG)...................................................................................................504
15.2.15 A/D Charge and Discharge Control Register (ADNDIS)........................................................505
15.2.16 Registers that control the pin function of the analog input pins.............................................506
15.3 Input voltage and conversion result.............................................................................................507
15.4 The operating mode of the A/D converter...................................................................................508
15.4.1 Software-triggered mode (selection mode, continuous conversion mode)............................508
15.4.2 Software-triggered mode (select mode, single-shot conversion mode).................................509
15.4.3 Software trigger mode (scan mode, continuous conversion mode).......................................510
15.4.4 Software trigger mode (scan mode, single-shot conversion mode).......................................511
15.4.5 Hardware-triggered no-wait mode (select mode, continuous transition mode).....................512
15.4.6 Hardware-triggered no-wait mode (select mode, single-shot transition mode).....................513
15.4.7 Hardware-triggered no-wait mode (scan mode, continuous transition mode).......................514
15.4.8 Hardware-triggered no-wait mode (scan mode, single-shot conversion mode)....................515
15.4.9 Hardware-triggered wait mode (selection mode, continuous transition mode)......................516
15.4.10 Hardware-triggered wait mode (select mode, single-shot transition mode) ..........................517
15.4.11 Hardware-triggered wait mode (scan mode, continuous transition mode)............................518
15.4.12 Hardware-triggered wait mode (scan mode, single-shot transition mode)............................519
15.5 Setup flowchart for the converter ................................................................................................520
15.5.1 The setting of the software trigger mode................................................................................520
15.5.2 The hardware triggers the setting of no wait mode................................................................521
15.5.3 Hardware triggers the setting of wait mode............................................................................522
15.5.4 Select the setting for the output voltage/internal reference voltage of the temperature sensor
523
15.5.5 The setting of the test mode...................................................................................................524
Chapter 16 D/A converter.................................................................................................................525
16.1 The functionality of the D/A converter.........................................................................................525
16.2 The structure of the D/A converter..............................................................................................526
16.3 Registers that control the D/A converter .....................................................................................527
16.3.1 Peripheral enable register 1 (PER1). .....................................................................................527
16.3.2 The mode register (DAM) of the D/A converter......................................................................528
16.3.3 The D/A conversion value sets register i (DACSi)(i=0, 1)......................................................528
16.3.4 The event output target selection register n (ELSELRn), n=00~21........................................529

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16.3.5 Registers that control the function of the analog input pin port..............................................529
16.4 Operation of the D/A converter....................................................................................................530
16.4.1 Normal mode of operation......................................................................................................530
16.4.2 Operation of real-time output mode........................................................................................531
16.4.3 The output timing of the D/A conversion values.....................................................................532
16.5 Considerations when using D/A converters................................................................................533
Chapter 17 Comparator....................................................................................................................534
17.1 The functionality of the comparator.............................................................................................534
17.2 The structure of the comparator..................................................................................................535
17.3 Control registers of the comparator.............................................................................................537
17.3.1 Peripheral enable register 1 (PER1). .....................................................................................538
17.3.2 Comparator Mode Setting Register (COMPMDR).................................................................539
17.3.3 Comparator Filter Control Register (COMPFIR)....................................................................540
17.3.4 Comparator Output Control Register (COMPOCR)...............................................................542
17.3.5 The comparator has a built-in reference control register (CVRCTL).....................................544
17.3.6 The comparator has a built-in reference voltage selection register (CiRVM)........................545
17.3.7 The input signal of comparator 0 selects the control register (CMPSEL0)............................546
17.3.8 The input signal of comparator 1 selects the control register (CMPSEL1)............................547
17.3.9 Hysteresis control register (CMP0HY) for comparator 0........................................................548
17.3.10 Hysteresis control register (CMP1HY) for comparator 1........................................................549
17.3.11 Registers that control the function of the analog input pin port..............................................550
17.4 Run the instructions.....................................................................................................................551
17.4.10 The digital filter of comparator i (i=0, 1)..................................................................................553
17.4.11 Comparator i interrupt (i=0, 1)................................................................................................553
17.4.12 The event signal output to the linkage controller (EVENTC).................................................554
17.4.13 The output of comparator i (i=0, 1).........................................................................................555
17.4.14 Stop and provision of the comparator clock...........................................................................555
Chapter 18 Programmable Gain Amplifier (PGA)............................................................................556
18.1 Programmable gain amplifier function.........................................................................................556
18.2 Structure of a programmable gain amplifier................................................................................557
18.3 Register of a programmable gain amplifier.................................................................................558
18.3.1 Peripheral enable register 1 (PER1). .....................................................................................558
18.3.2 Programmable Gain Amplifier Control Register (PGAnCTL).................................................559
18.3.3 Registers that control the function of the analog input pin port..............................................559
18.4 Operation of a programmable gain amplifier...............................................................................560
18.4.1 The start-up procedure for the programmable gain amplifier.................................................560
18.4.2 The stop-run step of the programmable gain amplifier..........................................................561
Chapter 19 Universal serial communication unit .............................................................................562

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19.1 Functions of the Universal Serial Communication Unit...............................................................563
19.1.1 3 wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI21, SSPI30, SSPI31) ..563
19.1.2 UART (UART0～UART3).......................................................................................................564
19.1.3 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31)........................................565
19.2 The structure of a universal serial communication unit...............................................................566
19.2.1 Shift Register (SCI0)...............................................................................................................569
19.2.2 The serial data register mn (SDRmn) is either 8 bits low or 9 bits low (SCI0).......................569
19.2.3 Shift Register (SCI1/SCI2)......................................................................................................571
19.2.4 Serial data register mn(SDRmn) (SCI1/SCI2)........................................................................571
19.3 Control registers of the universal serial communication unit ......................................................573
19.3.1 Peripheral enable register 0/2 (PER0/PER2).........................................................................575
19.3.2 Serial clock selection register m (SPSm)...............................................................................576
19.3.3 Serial mode register mn (SMRmn).........................................................................................577
19.3.4 Serial communication runs the set register mn (SCRmn)......................................................579
19.3.5 Serial data register mn(SDRmn) (SCI0 i.e. m=0)...................................................................582
19.3.6 Serial data register mn(SDRmn) (SCI1/SCI2 i.e. m=1/2).......................................................583
19.3.7 The serial flag clears the trigger register mn (SIRmn)...........................................................584
19.3.8 Serial status register mn (SSRmn).........................................................................................585
19.3.9 Serial channel start register m(SSm). ....................................................................................587
19.3.10 Serial channel stop register m(STm)......................................................................................588
19.3.11 Serial channel enable status register m (SEm)......................................................................589
19.3.12 Serial output enable register m (SOEm). ...............................................................................590
19.3.13 Serial output register m(SOm)................................................................................................591
19.3.14 Serial output level register m(SOLm).....................................................................................592
19.3.15 Input Switch Control Register (ISC). ......................................................................................594
19.3.16 Noise filter enable register 0 (NFEN0). ..................................................................................595
19.3.17 Registers that control serial input/output pin port functions...................................................596
19.4 Run stop mode ............................................................................................................................597
19.4.1 Case when the operation is stopped on a unit basis .............................................................597
19.4.2 Case of stop operation by channel.........................................................................................598
19.5 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20, SSPI20, SSPI20, SSPI20,
Operation of SSPI21, SSPI30, SSPI31) communication..........................................................................599
19.5.1 Master send............................................................................................................................600
19.5.2 Master receive........................................................................................................................608
19.5.3 Sending and receiving of the master......................................................................................616
19.5.4 Slave sending .........................................................................................................................624
19.5.5 Slave receive..........................................................................................................................632
19.5.6 Slave sending and receiving...................................................................................................638
19.5.7 Calculate the transmit clock frequency...................................................................................647
19.5.8 In 3-wire serial I/O (SSPI00, SSPI01, SSPI10, SSPI11, SSPI20 , SSPI21, SSPI30, SSPI31)

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Processing steps when an error occurs during communication.............................................................649
19.6 The operation of the clock synchronization serial communication of the slave selection input
function 650
19.6.1 Slave sending .........................................................................................................................653
19.6.2 Slave receive..........................................................................................................................663
19.6.3 Slave sending and receiving...................................................................................................670
19.6.4 Calculate the transmit clock frequency...................................................................................680
19.6.5 The processing step when an error occurs during clock synchronization serial communication
with the slave selection input function.....................................................................................................681
19.7 Operation of UART (UART0~UART3) communication...............................................................682
19.7.1 UART sends............................................................................................................................683
19.7.2 UART receives........................................................................................................................692
19.7.3 Calculation of baud rate..........................................................................................................699
19.7.4 The processing step when an error occurs during UART (UART0~UART3) communication
703
19.8 Operation of LIN communications...............................................................................................704
19.8.1 LIN sends................................................................................................................................704
19.8.2 LIN receives............................................................................................................................707
19.9 Simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, Operation of IIC21, IIC30, IIC31) communication
712
19.9.1 The address segment is sent .................................................................................................713
19.9.2 Data sending...........................................................................................................................718
19.9.3 Data reception ........................................................................................................................721
19.9.4 Stop conditions generation.....................................................................................................725
19.9.5 Calculation of the transfer rate ...............................................................................................726
19.9.6 In simple I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21, IIC30, IIC31) Processing steps when
an error occurs during communication....................................................................................................728
Chapter 20 Serial interface IICA ......................................................................................................729
20.1 The serial interface IICA functions ..............................................................................................729
20.1.1 Run stop mode .......................................................................................................................729
20.1.2 I2 C-bus mode (supports multi-master)..................................................................................729
20.1.3 Wake-up mode .......................................................................................................................729
20.2 Structure of the serial interface IICA...........................................................................................732
20.2.1 IICA shift register n (IICAn).....................................................................................................733
20.2.2 Slave address register n(SVAn). ............................................................................................734
20.2.3 SO latches ..............................................................................................................................734
20.2.4 Wake-up control circuitry........................................................................................................734
20.2.5 Serial clock counter ................................................................................................................734
20.2.6 Interrupt request signal generation circuit..............................................................................734
20.2.7 Serial clock control circuitry....................................................................................................734
20.2.8 Serial clock wait control circuit................................................................................................734

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20.2.9 Ack generation circuit, stop condition detection circuit, start condition detection circuit, Ack
detection circuit........................................................................................................................................734
20.2.10 Data hold time correction circuit.............................................................................................734
20.2.11 Start conditional generation circuitry......................................................................................734
20.2.12 Stop condition generation circuitry.........................................................................................734
20.2.13 Bus status detection circuitry..................................................................................................734
20.3 Controls registers of the serial interface IICA..............................................................................736
20.3.1 Peripheral enable register 0/1 (PER0/1). ...............................................................................737
20.3.2 IICA control register n0 (IICCTLn0)........................................................................................737
20.3.3 IICA status register n (IICSn)..................................................................................................742
20.3.4 IICA flag register n (IICFn)......................................................................................................745
20.3.5 IICA control register n1 (IICCTLn1)........................................................................................747
20.3.6 IICA low-level width setting register n (IICWLn).....................................................................749
20.3.7 IICA high level width setting register n (IICWHn)...................................................................749
20.3.8 Port mode register x (PMx).....................................................................................................750
20.4 The functionality of I2C-bus mode...............................................................................................751
20.4.1 Pin structure............................................................................................................................751
20.4.2 The method of transmitting the clock is set by the IICWLn register and the IICWHn register
752
20.5 Definition and control method of theI2C-bus...............................................................................753
20.5.1 Start conditions.......................................................................................................................754
20.5.2 address...................................................................................................................................755
20.5.3 The designation of the transmission direction........................................................................755
20.5.4 Ack (ACK)...............................................................................................................................756
20.5.5 Stop Conditions ......................................................................................................................757
20.5.6 await........................................................................................................................................758
20.5.7 method of release from wait state ..........................................................................................760
20.5.8 Generation timing and waiting control of interrupt requests (INTIICAn)................................761
20.5.9 The detection method for address matching..........................................................................762
20.5.10 Detection of errors..................................................................................................................762
20.5.11 Extension code.......................................................................................................................763
20.5.12 arbitration................................................................................................................................764
20.5.13 Wake-up function....................................................................................................................766
20.5.14 Communication appointments................................................................................................769
20.5.15 Other considerations...............................................................................................................772
20.5.16 Communication operation.......................................................................................................773
20.5.17 Timing of the generation of I2C interrupt requests (INTIICAn)..............................................781
20.6 Timing diagram............................................................................................................................802
Chapter 21 Serial interface SPI........................................................................................................817

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21.1 The serial interface SPI functions................................................................................................817
21.2 Structure of the serial interface SPI.............................................................................................817
21.3 Registers that control the serial interface SPI.............................................................................818
21.3.1 Peripheral enable register 2 (PER2). .....................................................................................819
21.3.2 SPI Operating Mode Register (SPIMn)..................................................................................820
21.3.3 SPI clock selection register (n)...............................................................................................821
21.3.4 SPI status register (SPISn).....................................................................................................822
21.3.5 Transmit buffer register (SDROn). .........................................................................................823
21.3.6 Receive buffer register (SDRIn).............................................................................................823
21.3.7 The SPI pin functions the control register..............................................................................824
21.4 Serial interface for operation of the SPI......................................................................................825
21.4.1 The sending and receiving of the master...............................................................................826
21.4.2 The reception of the master....................................................................................................829
21.4.3 Slave sending and receiving...................................................................................................832
21.4.4 Slave reception.......................................................................................................................835
Chapter 22 CAN control...................................................................................................................838
22.1 Summary description...................................................................................................................838
22.1.1 features...................................................................................................................................838
22.1.2 Feature overview....................................................................................................................839
22.1.3 Configuration ..........................................................................................................................840
22.2 CAN protocol ...............................................................................................................................841
22.2.1 Frame format..........................................................................................................................841
22.2.2 Frame type..............................................................................................................................842
22.2.3 Data frames and remote frames.............................................................................................842
22.2.4 Error frame..............................................................................................................................849
22.2.5 Overload frames.....................................................................................................................850
22.3 function ........................................................................................................................................851
22.3.1 Bus prioritization.....................................................................................................................851
22.3.2 Bit padding..............................................................................................................................851
22.3.3 Multi-master............................................................................................................................851
22.3.4 Multicast..................................................................................................................................851
22.3.5 CAN sleep mode /CAN stop mode function...........................................................................851
22.3.6 Error control function ..............................................................................................................852
22.3.7 Baud rate control function.......................................................................................................857
22.4 The connection to the target system...........................................................................................861
22.5 Internal registers of the CAN controller.......................................................................................862
22.5.1 CAN controller configuration...................................................................................................862
22.5.2 Register access type ..............................................................................................................864
22.5.3 Register bit configuration........................................................................................................880

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22.6 Bit setting/clear function ..............................................................................................................884
22.7 Control registers ..........................................................................................................................885
22.7.1 Peripheral clock selection register (PER0/PER2)..................................................................885
22.7.2 CAN Global Module Control Register (CnGMCTRL).............................................................886
22.7.3 CAN Global Module Clock Selection Register (CnGMCS)....................................................888
22.7.4 CAN Global Automatic Block Transfer Control Register (CnGMABT)...................................889
22.7.5 CAN Global Automatic Block Delay Setting Register (CnGMABTD).....................................891
22.7.6 CAN module mask registers (CnMASKaL, CnMASKaH) (a=1, 2, 3, or4)..............................892
22.7.7 CAN Module Control Register (CnCTRL)...............................................................................894
22.7.8 CAN Module Last Error Code Register (CnLEC)...................................................................898
22.7.9 CAN Module Information Register (CnINFO).........................................................................899
22.7.10 CAN Module Error Counter Register (CnERC)......................................................................900
22.7.11 CAN Module Interrupt Enable Register (CnIE). .....................................................................901
22.7.12 CAN Module Interrupt Status Register (CnINTS)...................................................................903
22.7.13 CAN Module Bit Rate Scaling Register (CnBRP). .................................................................904
22.7.14 CAN Module Bit Rate Register (CnBTR)................................................................................905
22.7.15 CAN module last entered the pointer register (CnLIPT)........................................................907
22.7.16 CAN module receive History List Register (CnRGPT)...........................................................908
22.7.17 CAN module last output pointer register (CnLOPT)...............................................................909
22.7.18 CAN module send History List Register (CnTGPT)...............................................................910
22.7.19 CAN Module Timestamp Register (CnTS).............................................................................911
22.7.20 CAN message data byte register (CnMDBxm) (x=0 to 7), (CnMDBzm) (z=01, 23, 45, 67)..913
22.7.21 CAN message data length register m (CnMDLCm)...............................................................915
22.7.22 CAN Message Configuration Register (CnMCONFm)...........................................................916
22.7.23 CAN message ID register m (CnMIDLm and CnMIDHm)......................................................917
22.7.24 CAN message control register m (CnMCTRLm)....................................................................918
22.7.25 Serial communication pin select register 1 (PIOR3)..............................................................921
22.7.26 Port mode registers 0/4/5/6 (PM0/4/5/6)................................................................................921
22.8 CAN controller initialization..........................................................................................................922
22.8.1 CAN module initialization........................................................................................................922
22.8.2 Initialization of the packet cache ............................................................................................922
22.8.3 Redefine the message cache.................................................................................................922
22.8.4 Transition from initialization mode to operating mode ...........................................................923
22.8.5 Resets the CAN Module Error Counter cnERC .....................................................................924
22.9 Message reception ......................................................................................................................925
22.9.1 Message reception .................................................................................................................925
22.9.2 Receive data reads.................................................................................................................926
22.9.3 Receive history list function....................................................................................................927
22.9.4 Blocking function.....................................................................................................................929

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22.9.5 Multi-buffer receive block capability .......................................................................................930
22.9.6 Remote frame reception.........................................................................................................931
22.10 Message sending.........................................................................................................................932
22.10.1 Message sending....................................................................................................................932
22.10.2 Send history list function.........................................................................................................934
22.10.3 Automatic Block Transfer (ABT).............................................................................................936
22.10.4 Transfer abort processing.......................................................................................................937
22.10.5 Remote frame transfer............................................................................................................938
22.11 Power-saving mode.....................................................................................................................939
22.11.1 CAN sleep mode.....................................................................................................................939
22.11.2 CAN stop mode ......................................................................................................................941
22.11.3 Example of power saving mode .............................................................................................942
22.12 Interrupt function..........................................................................................................................943
22.13 Diagnostic functions and special operating modes.....................................................................944
22.13.1 Receive mode only.................................................................................................................944
22.13.2 Single-shot mode....................................................................................................................945
22.13.3 Self-test mode.........................................................................................................................946
22.13.4 Receive/send operations in operation mode..........................................................................947
22.14 Timestamp function.....................................................................................................................948
22.14.1 Timestamp function ................................................................................................................948
22.15 Baud rate setting..........................................................................................................................950
22.15.1 Baud rate setting.....................................................................................................................950
22.15.2 A representative example of baud rate settings.....................................................................954
22.16 The operation of the CAN controller............................................................................................958
Chapter 23 LCD bus interface..........................................................................................................983
23.1 Functions of the LCD bus interface.............................................................................................983
23.2 LCD bus interface configuration..................................................................................................984
23.2.1 LCD bus interface data register (LBDATA, LBDATAL)..........................................................985
23.2.2 LCD bus interface read data registers (LBDATAR, LBDATARL). .........................................986
23.3 Control registers for the LCD bus interface.................................................................................987
23.3.1 Peripheral enable register 1 (PER1). .....................................................................................987
23.3.2 LCD Bus Interface Mode Register (LBCTL)...........................................................................988
23.3.3 LCB bus interface periodic control register (LBCYC).............................................................989
23.3.4 The LCB bus interface waits for control registers (LBWST)..................................................989
23.3.5 Pin-mode control registers......................................................................................................990
23.4 Runtime order..............................................................................................................................991
23.4.1 Timing relationships................................................................................................................991
23.4.2 LCD bus interface status........................................................................................................992
23.4.3 Write the LCD bus...................................................................................................................993