Texas Instruments MSPM0G350 Series User manual

MSPM0G350x Automotive Mixed-Signal Microcontrollers With CAN-FD Interface
1 Features
• Qualified for automotive applications
•Core
– Arm® 32-bit Cortex®-M0+ CPU with memory
protection unit, frequency up to 80 MHz
•Operating characteristics
– Extended temperature: –40°C up to 125°C
– Wide supply voltage range: 1.62 V to 3.6 V
•Memories
– Up to 128KB of flash memory with error
correction code (ECC)
– Up to 32KB of SRAM with hardware parity
•High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADCs) with up to
17 external channels
• 14-bit effective resolution at 250-ksps with
hardware averaging
– One 12-bit 1-MSPS digital-to-analog converter
with integrated output buffer (DAC)
– Two zero-drift zero-crossover chopper op-amps
(OPA)
• 0.5-µV/°C drift with chopping
• Integrated programmable gain stage, up to
32x
– One general-purpose amplifier (GPAMP)
– Three high-speed comparators (COMP) with 8-
bit reference DACs
• 32-ns propagation delay in high-speed
mode
• Support low-power mode operation down to
0.7 µA
– Programmable analog connections between
ADC, OPAs, COMP and DAC
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
– Integrated supply monitor
•Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 467 µA at 4 MHz
– STOP: 46 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 80 nA with IO wake-up capability
•Intelligent digital peripherals
– 7-channel DMA controller
– Math accelerator supports DIV, SQRT, MAC
and TRIG computations
– Seven timers supports up to 22 PWM channels
• One 16-bit general-purpose timer
• One 16-bit general-purpose timer supports
QEI
• Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
• One 32-bit high-resolution general-purpose
timer
• Two 16-bit advanced timers with deadband
support up to 12 PWM channels
– Two window-watchdog timers
– RTC with alarm and calendar mode
•Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
– Two I2C interfaces support up to FM+
(1 Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPIs, one SPI supports up to 32 Mbits/s
– One Controller Area Network (CAN) interface
supports CAN 2.0 A or B and CAN-FD
•Clock system
– Internal 4- to 32-MHz oscillator with up to
±1.2% accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz low-frequency oscillator
(LFOSC) with ±3% accuracy
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
•Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
– True random number generator (TRNG)
– AES encryption with 128 or 256-bit key
•Flexible I/O features
– Up to 60 GPIOs
• Two 5-V tolerant IOs
• Two high-drive IOs with 20-mA drive
strength
•Development support
– 2-pin serial wire debug (SWD)
•Package options
– 64-pin LQFP
– 48-pin LQFP, VQFN
– 32-pin VQFN
– 28-pin VSSOP
– 24-pin VQFN
•Family members (also see Device Comparison)
– MSPM0G3505: 32KB flash, 16KB RAM
– MSPM0G3506: 64KB flash, 32KB RAM
ADVANCE INFORMATION
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.

– MSPM0G3507: 128KB flash, 32KB RAM
•Development kits and software (also see Tools
and Software)
–LP-MSPM0G3507 LaunchPad™ development
kit
– MSP Software Development Kit (SDK)
•Automotive qualification
– AEC-Q100 Grade 1 (-40°C to 125°C)
– 24 , 32 and 48 -pin QFN with wettable flanks
option
2 Applications
•Automotive body electronics and Lighting
•Automotive Gateway
•Steering Wheel Systems
•Automotive Motor Control
•DC to AC Inverters
•Automotive Interior Lighting
•Door handle modules
•Kick to open modules
•Vehicle Occupancy Detection
•Seat Comfort Module
3 Description
MSPM0G350x microcontrollers (MCUs) are part of the MSP highly integrated, ultra-low-power 32-bit MCU
family based on the enhanced Arm® Cortex®-M0+ 32-bit core platform operating at up to 80-MHz frequency.
These cost-optimized MCUs offer high-performance analog peripheral integration, support extended temperature
ranges from -40°C to 125°C, and operate with supply voltages ranging from 1.62 V to 3.6 V.
The MSPM0G350x devices provide up to 128KB embedded flash program memory with built-in error correction
code (ECC) and up to 32KB SRAM with hardware parity option. These MCUs also incorporate a memory
protection unit, 7-channel DMA, math accelerator, and a variety of high-performance analog peripherals such
as two 12-bit 4-Msps ADCs, configurable internal shared voltage reference, one 12-bit 1-Msps DAC, three
high speed comparators with built-in reference DACs, two zero-drift zero-crossover op-amps with programmable
gain, and one general-purpose amplifier. These devices also offer intelligent digital peripherals such as two
16-bit advanced control timers, five general-purpose timers (with one 16-bit general-purpose timer for QEI
interface, two 16-bit general-purpose timers for STANDBY mode, and one 32-bit general-purpose timer), two
windowed-watchdog timers, and one RTC with alarm and calendar modes. These devices provide data integrity
and encryption peripherals (AES, CRC, TRNG) and enhanced communication interfaces (four UART, two I2C,
two SPI, CAN 2.0/FD).
The TI MSPM0 family of low-power MCUs consists of devices with varying degrees of analog and digital
integration allowing for customers find the MCU that meets their project's needs. The MSPM0 MCU platform
combines the Arm Cortex-M0+ platform with a holistic ultra-low-power system architecture, allowing system
designers to increase performance while reducing energy consumption.
MSPM0G350x MCUs are supported by an extensive hardware and software ecosystem with reference designs
and code examples to get the design started quickly. Development kits include a LaunchPad available for
purchase. TI also provides a free MSP Software Development Kit (SDK), which is available as a component of
Code Composer Studio™ IDE desktop and cloud version within the TI Resource Explorer. MSPM0 MCUs are
also supported by extensive online collateral, training with MSP Academy, and online support through the TI
E2E™ support forums.
For complete module descriptions, see the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference
Manual.
CAUTION
System-level ESD protection must be applied in compliance with the device-level ESD specification
to prevent electrical overstress or disturbing of data or code memory. See MSP430™ System-Level
ESD Considerations for more information. The principles in this application note are applicable to
MSPM0 MCUs.
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4 Functional Block Diagram
Figure 4-1 shows the MSPM0G350x functional block diagram.
SPI0
SPI1
CPU SUB SYSTEM
Arm
Cortex-M0+
fmax = 80 MHz
NVIC
MPU
SWD + MTB
IOPORT
AHB BUS (MCLK)
FLASH
Up to 128KB
SRAM
Up to 32KB
ROM
BCR, BSL
CPU-ONLY PD1 PERIPHERAL BUS (MCLK)
DMA
7-ch
PD1 PERIPHERAL BUS (MCLK)
AES
CRC
TRNG
UART3
GPIO
tIOBUSt
PD0 PERIPHERAL BUS (ULPCLK)
12b ADC0
12b ADC1
TIMG0
TIMG8
UART0
I2C0
I2C1
IOMUX
PMCU (SYSCTL)
GPAMP
FLASHCTL
ULPCLK
ULPCLK
PD1, CPU ACCESS ONLY
PD1, CPU/DMA ACCESS
PD1/PD0, CPU/DMA ACCESS
PD0, CPU/DMA ACCESS
LEGEND
EVENTRTC
WWDT0
WWDT1
CAN-FD
TIMA0
TIMA1
TIMG6
TIMG7
TIMG12
32-bit
UART1
UART2
VREF
PD0 PERIPHERAL BUS (ULPCLK)
OPA0
OPA1
COMP0
COMP1
COMP2
TEMP SENSOR
SYSOSC
SYSPLL
LFXT
HFXT
LFOSC
CKM
LDO
PMU
BOR
POR
VBOOST
12b DAC0
DEBUG
RTC_OUT
TX, RX,
CTS, RTS
TX, RX,
CTS, RTS
SDA, SCL
2-CH
IN+, IN-,
OUT
DAC_OUT
IN+, IN-,
OUT
IN+, IN-,
OUT
VREF+,
VREF-
A0_x
A1_x
2-CH
2-CH
2-CH
2-CH
FAULT
4-CH
FAULT
POCI, PICO,
SCK, CSx
TX, RX,
CTS, RTS
TX, RX
PAx, PBx
LFXIN, LFXOUT
HFXIN, HFXOUT
ROSC
CLK_OUT, FCC_IN
VDD, VSS
VCORE, NRST
Each COMPx includes an 8b
reference DAC; COMP0 and
COMP1 reference DACs connect
to OPA0 and OPA1, respectively
2-CH
QEI/HALL
MATHACL
SWCLK,
SWDIO
Figure 4-1. MSPM0G350x Functional Block Diagram
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................2
3 Description.......................................................................2
4 Functional Block Diagram.............................................. 3
5 Device Comparison.........................................................5
6 Pin Configuration and Functions...................................6
6.1 Pin Diagrams.............................................................. 6
6.2 Pin Attributes.............................................................11
6.3 Signal Descriptions................................................... 14
6.4 Connections for Unused Pins................................... 26
7 Specifications................................................................ 27
7.1 Absolute Maximum Ratings...................................... 27
7.2 ESD Ratings............................................................. 27
7.3 Recommended Operating Conditions.......................27
7.4 Thermal Information..................................................28
7.5 Supply Current Characteristics................................. 30
7.6 Power Supply Sequencing........................................31
7.7 Flash Memory Characteristics.................................. 32
7.8 Timing Characteristics...............................................33
7.9 Clock Specifications..................................................34
7.10 Digital IO................................................................. 37
7.11 Analog Mux VBOOST............................................. 39
7.12 ADC........................................................................ 39
7.13 Temperature Sensor............................................... 41
7.14 VREF...................................................................... 41
7.15 Comparator (COMP)...............................................42
7.16 DAC........................................................................ 43
7.17 GPAMP................................................................... 44
7.18 OPA.........................................................................45
7.19 I2C.......................................................................... 47
7.20 SPI.......................................................................... 48
7.21 UART...................................................................... 50
7.22 TIMx........................................................................51
7.23 TRNG......................................................................51
7.24 Emulation and Debug............................................. 51
8 Detailed Description......................................................52
8.1 CPU.......................................................................... 52
8.2 Operating Modes...................................................... 52
8.3 Power Management Unit (PMU)...............................54
8.4 Clock Module (CKM).................................................54
8.5 DMA..........................................................................55
8.6 Events.......................................................................56
8.7 Memory.....................................................................57
8.8 Flash Memory........................................................... 60
8.9 SRAM........................................................................61
8.10 GPIO.......................................................................61
8.11 IOMUX.................................................................... 61
8.12 ADC........................................................................ 61
8.13 Temperature Sensor............................................... 62
8.14 VREF...................................................................... 62
8.15 COMP..................................................................... 63
8.16 DAC........................................................................ 64
8.17 OPA.........................................................................64
8.18 GPAMP................................................................... 65
8.19 TRNG......................................................................65
8.20 AES.........................................................................65
8.21 CRC........................................................................ 66
8.22 MATHACL...............................................................66
8.23 UART...................................................................... 66
8.24 I2C.......................................................................... 67
8.25 SPI.......................................................................... 67
8.26 CAN-FD.................................................................. 67
8.27 WWDT.................................................................... 68
8.28 RTC.........................................................................68
8.29 Timers (TIMx)..........................................................68
8.30 Device Analog Connections....................................71
8.31 Input/Output Diagrams............................................72
8.32 Serial Wire Debug Interface....................................73
8.33 Bootstrap Loader (BSL).......................................... 73
8.34 Device Factory Constants ......................................73
8.35 Identification............................................................74
9 Applications, Implementation, and Layout................. 75
9.1 Typical Application.................................................... 75
10 Device and Documentation Support..........................76
10.1 Getting Started and Next Steps.............................. 76
10.2 Device Nomenclature..............................................76
10.3 Tools and Software................................................. 77
10.4 Documentation Support.......................................... 78
10.5 Support Resources................................................. 78
10.6 Trademarks.............................................................78
10.7 Electrostatic Discharge Caution..............................78
10.8 Glossary..................................................................78
11 Mechanical, Packaging, and Orderable
Information.................................................................... 79
12 Revision History ......................................................... 79
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5 Device Comparison
The following table summarizes the features of each device that is described in this data sheet.
Table 5-1. Device Comparison
DEVICE NAME (1) (4) FLASH /SRAM
(KB) QUAL(2) MATH ACCEL
ADC /
CHAN COMP DAC OPA GPAMP UART/I2C/SPI CAN TIMA TIMG GPIO PACKAGE [PACKAGE SIZE] (3)
MSPM0G3505xPM 32 / 16
Q Y 2 / 17 3 1 2 1 4 / 2 / 2 1 2 5 60 64 LQFP
[12 mm × 12 mm]
MSPM0G3506xPM 64 / 32
MSPM0G3507xPM 128 / 32
MSPM0G3505xPT 32 / 16
Q Y 2 / 16 3 1 2 1 4 / 2 / 2 1 2 5 44 48 LQFP
[9 mm × 9 mm]
MSPM0G3506xPT 64 / 32
MSPM0G3507xPT 128 / 32
MSPM0G3505xRGZ 32 / 16
Q Y 2 / 16 3 1 2 1 4 / 2 / 2 1 2 5 44 48 VQFN
[7 mm × 7 mm](5)
MSPM0G3506xRGZ 64 / 32
MSPM0G3507xRGZ 128 / 32
MSPM0G3505xRHB 32 / 16
Q Y 2 / 11 3 1 2 1 4 / 2 / 2 1 2 5 28 32 VQFN
[5 mm × 5 mm] (5)
MSPM0G3506xRHB 64 / 32
MSPM0G3507xRHB 128 / 32
MSPM0G3505xRGE 32 / 16
Q Y 2 / 9 3 1 2 1 4 / 2 / 2 1 2 5 20 24 VQFN
[4 mm × 4 mm](5)
MSPM0G3506xRGE 64 / 32
MSPM0G3507xRGE 128 / 32
MSPM0G3505xDGS28 32 / 16
Q Y 2 / 11 3 1 2 1 4 / 2 / 2 1 2 5 24 28 VSSOP
[7.1 mm × 3 mm]
MSPM0G3506xDGS28 64 / 32
MSPM0G3507xDGS28 128 / 32
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 11, or see the TI website.
(2) Device Qualifications:
• Q = –40°C to 125°C , AEC-Q100 qualified
(3) The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section 11.
(4) For more information about the device name, see Section 10.2
(5) 24, 32 and 48-pin VQFN packages are available with wettable flanks
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6 Pin Configuration and Functions
The System Configuration tool provides a graphical interface to enable, configurable, and generate initialization
code for pin multiplexing and simplifying pin settings. The following pin diagrams show the primary peripheral
functions, some of the integrated device features, and available clock signals to simplify the device pinout. For
full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections.
6.1 Pin Diagrams
Power
Reset
High-Speed I/O (HSIO)
5-V Tolerant Open-Drain I/O (ODIO)
High-Drive I/O (HDIO)
Figure 6-1. Pin Diagram Color Coding
LQFP64
1
2
3
4
5
6
7
8
64 63 62 61 60 59 58 57
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PB12 PB11 / CLK_OUT PB10 PB9 PB8 PB7 PB6 PA11 PA10 / CLK_OUT PA9 / RTC_OUT / CLK_OUT PA8 PB5 PB4 PB3 PB2 PA7 / CLK_OUT
PB1
PB0
PA6 / HFCLK_IN / HFXOUT
PA5 / HFXIN / FCC_IN
PA4 / LFCLK_IN / LFXOUT
PA3 / LFXIN
PA2 / ROSC
VSS
VDD
PA31 / CLK_OUT
NRST
PA30
PA29
PA28
PA1
PA0 / FCC_IN
PB13
PB14
PB15
PB16
PA12 / FCC_IN
PA13
PA14 / CLK_OUT / A0_12
PA15 / A1_0
PA16 /A1_1 /FCC_IN
PA17 / A1_2
PA18 / A1_3
PA19 / SWDIO
PA20 / SWCLK
PB17 / A1_4
PB18 / A1_5
PB19 / A1_6
PA21 / A1_7 / VREF-
PA22 / CLK_OUT / A0_7
PB20 / A0_6
PB21
PB22
PB23
PB24 / A0_5
PA23 VREF+
PA24 / A0_3
PA25 / A0_2
PB25 / A0_4
PB26
PB27
PA26 / A0_1
PA27/ A0_0
VCORE
Figure 6-2. 64-Pin PM (LQFP) (Top View)
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LQFP48
1
2
3
4
5
6
7
8
48 47 46 45 44 43 42 41
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
PB17 / A1_4
PA20 / SWCLK
PA19 / SWDIO
PA18 / A1_3
PA17 / A1_2
PA16 / A1_1 /FCC_IN
PA15 / A1_0
PA14 / CLK_OUT /A0_12
PA13
PA12 / FCC_IN
PB16
PB15
VCORE PA27 / RTC_OUT / A0_0 PA26 / A0_1 PA25 / A0_2 / OPA0_IN1+ PA24 / A0_3 PB24 / A0_5 PB20 / A0_6 PA22 / CLK_OUT / A0_7 PA21 / A1_7 / VREF- PB19 / A1_6 PB18 / A1_5
PA23 / VREF+
PA0 / FCC_IN
PA1
PA28
NRST
PA31 / CLK_OUT
VDD
VSS
PA2 / ROSC
PA3 / COMP1_OUT / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA7 / CLK_OUT
PB2 PB3
PA8
PA9 / RTC_OUT / CLK_OUT
PA10 / CLK_OUT
PA11
PB6
PB7
PB8
PB9
PB14
Figure 6-3. 48-Pin PT (LQFP) (Top View)
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1
2
3
4
5
6
7
8
48 47 46 45 44 43 42 41
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
VCORE PA27 / RTC_OUT / A0_0 PA26 / A0_1 PA25 / A0_2 PA24 / A0_3 PB24 / A0_5 PB20 / A0_6 PA22 / CLK_OUT / A0_7 PA21 / A1_7 / VREF- PB19 / A1_6 PB18 / A1_5
PA0 / FCC_IN
PA1
PA28
NRST
PA31 / CLK_OUT
VDD
VSS
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA7 / CLK_OUT
PB2 PB3 PA8
PA9 / RTC_OUT / CLK_OUT
PA10 / CLK_OUT
PA11
PB6
PB7
PB8 PB9
PB14
PB17 / A1_4
PA20 / SWCLK
PA19 / SWDIO
PA18 / A1_3
PA17 / A1_2
PA16 / A1_1 /FCC_IN
PA15 / A1_0
PA14 / CLK_OUT / A0_12
PA13
PA12 / FCC_IN
PB16
PB15
VQFN48
Thermal pad
PA23 / VREF+
Figure 6-4. 48-Pin RGZ (VQFN) (Top View)
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VQFN32
Thermal pad
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
NRST
VDD
VSS
VCORE
PA0 / FCC_IN
PA1
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA7 / CLK_OUT
PA8
PA9 / RTC_OUT / CLK_OUT
PA10 / CLK_OUT
PA11
PA12 / FCC_IN
PA20 / SWCLK
PA19 / SWDIO
PA18 / A1_3
PA17 / A1_2
PA16 / A1_1/ FCC_IN
PA15 / A1_0
PA14 / CLK_OUT / A0_12
PA13
PA27 / RTC_OUT / A0_0
PA26 / A0_1 PA25 / A0_2 PA24 / A0_3 PA22 / A0_7
PA21 / A1_7 / VREF-
PA23 / VREF+
Figure 6-5. 32-Pin RHB (VQFN) (Top View)
VSSOP28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PA20 / SWCLK
PA19 / SWDIO
VCORE
NRST
VDD
VSS
PA0
PA1
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA5 / HFXIN / FCC_IN
PA6 / HFCLK_IN / HFXOUT
PA9 / RTC_OUT / CLK_OUT PA10 / CLK_OUT
PA11
PA16 / A1_1 / FCC_IN
PA15 / A1_0
PA14 / CLK_OUT / A0_12
PA18 / A1_3
PA17 / A1_2
PA25 / A0_2
PA24 / A0_3
PA22 / CLK_OUT / A0_7
PA21 / A1_7 / VREF-
PA27 / RTC_OUT / A0_0
PA26 / A0_1
PA23 / VREF+
Figure 6-6. 28-Pin DGS28 (VSSOP) (Top View)
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VQFN24
Thermal
pad
1
2
3
4
5
6
7 8 9 10 11 12
24 23 22 21 20 19
NRST
VDD
VSS
VCORE
PA0 / FCC_IN
PA1
PA2 / ROSC
PA3 / LFXIN
PA4 / LFCLK_IN / LFXOUT
PA9 / RTC_OUT / CLK_OUT
PA10 / CLK_OUT
PA11
PA20 / SWCLK
PA19 / SWDIO
PA18 / A1_3
PA17 / A1_2
PA16 / A1_1 / FCC_IN
PA15 / A1_0
PA26 / A0_1 PA25 / A0_2
PA24 /A0_3
PA22 / CLK_OUT / A0_7
PA21 / A1_7 / VREF-
PA23 / VREF+
18
17
16
15
14
13
Figure 6-7. 24-Pin RGE (VQFN) (Top View)
Note
For the full pin configuration and description of the functions for each package option, see Pin
Attributes and Signal Descriptions.
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6.2 Pin Attributes
The following table describes the functions available on every pin for each device package.
Note
Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) that
lets users configure the desired Pin Function using the PINCM.PF control bits.
Table 6-1. Pin Attributes
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTU
RE
ANALOG DIGITAL [PIN FUNCTION] (1)
64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN
N/A VDD 40 6 4 7 3 Power
N/A VSS 41 7 5 8 4 Power
N/A VCORE 32 48 32 3 23 Power
N/A NRST 38 4 3 6 2 Reset
1 PA0
UART0_TX [2] / I2C0_SDA [3] / TIMA0_C0 [4] /
TIMA_FAL1 [5] / TIMG8_C1 [6] / FCC_IN [7]/(Default
BSL I2C_SDA)
33 1 1 4 24
5V Tol.
Open-
Drain
2 PA1
UART0_RX [2] / I2C0_SCL [3] / TIMA0_C1 [4] /
TIMA_FAL2 [5] / TIMG8_IDX [6] / TIMG8_C0 [7]/
(Default BSL I2C_SCL)
34 2 2 5 1
5V Tol.
Open-
Drain
7 PA2 ROSC TIMG8_C1 [2] / SPI0_CS0 [3] / TIMG7_C1 [4] /
SPI1_CS0 [5] 42 8 6 9 5 Standard
8 PA3 LFXIN
TIMG8_C0 [2] / SPI0_CS1 [3] / UART2_CTS [4] /
TIMA0_C2 [5] / COMP1_OUT [6] / TIMG7_C0 [7] /
TIMA0_C1 [8] / I2C1_SDA [9]
43 9 7 10 6 Standard
9 PA4 LFXOUT
TIMG8_C1 [2] / SPI0_POCI [3] / UART2_RTS
[4] / TIMA0_C3 [5] / LFCLK_IN [6] / TIMG7_C1 [7] /
TIMA0_C1N [8] / I2C1_SCL [9]
44 10 8 11 7 Standard
10 PA5 HFXIN TIMG8_C0 [2] / SPI0_PICO [3] / TIMA_FAL1 [4] /
TIMG0_C0 [5] / TIMG6_C0 [6] / FCC_IN [7] 45 11 9 12 - Standard
11 PA6 HFXOUT
TIMG8_C1 [2] / SPI0_SCK [3] / TIMA_FAL0 [4] /
TIMG0_C1 [5] / HFCLK_IN [6] / TIMG6_C1 [ 7] /
TIMA0_C2N [8]
46 12 10 13 - Standard
14 PA7
COMP0_OUT [2] / CLK_OUT [3] / TIMG8_C0 [4] /
TIMA0_C2 [5] / TIMG8_IDX [6] / TIMG7_C1 [7] /
TIMA0_C1 [8]
49 13 11 – - Standard
19 PA8 UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] /
TIMA0_C0 [5] / TIMA1_C0N [6] 54 16 12 – - Standard
20 PA9
UART1_RX [2] / SPI0_PICO [3] / UART0_CTS [4] /
TIMA0_C1 [5] / RTC_OUT [6] / TIMA0_C0N [7] /
TIMA1_C1N [8] / CLK_OUT [9]
55 17 13 14 8 High-
Speed
21 PA10
UART0_TX [2] / SPI0_POCI [3] / I2C0_SDA [4] /
TIMA1_C0 [5] / TIMG12_C0 [6] / TIMA0_C2 [7] /
I2C1_SDA [8] / CLK_OUT [9]/(Default BSL UART_TX)
56 18 14 15 9 High-Drive
22 PA11
UART0_RX [2] / SPI0_SCK [3] / I2C0_SCL [4] /
TIMA1_C1 [5] / COMP0_OUT [6]/ TIMA0_C2N [7] /
I2C1_SCL [8]/(Default BSL UART_RX)
57 19 15 16 10 High-Drive
34 PA12 UART3_CTS [2] / SPI0_SCK [3] / TIMG0_C0 [4] /
CAN_TX [5] / TIMA0_C3 [6] / FCC_IN [7] 5 27 16 – - High- Speed
35 PA13 COMP0_IN2- UART3_RTS [2] / SPI0_POCI [3] / UART3_RX [4] /
TIMG0_C1 [5] / CAN_RX [6] / TIMA0_C3N [7] 6 28 17 – - High- Speed
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Table 6-1. Pin Attributes (continued)
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTU
RE
ANALOG DIGITAL [PIN FUNCTION] (1)
64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN
36 PA14 COMP0_IN2+ / A0_12 UART0_CTS [2] / SPI0_PICO [3] / UART3_TX [4] /
TIMG12_C0 [5] / CLK_OUT [6] 7 29 18 17 - High- Speed
37 PA15
A1_0 / DAC_OUT /
OPA0_IN2+ /
OPA1_IN2+/
COMP0_IN3+ /
COMP1_IN3+
UART0_RTS [2] / SPI1_CS2 [3] / I2C1_SCL [4] /
TIMA1_C0 [5] / TIMG8_IDX [6] / TIMA1_C0N [7] /
TIMA0_C2 [8]
8 30 19 18 11 Standard
38 PA16 A1_1 / OPA1_OUT
COMP2_OUT [2] / SPI1_POCI [3] / I2C1_SDA [4] /
TIMA1_C1 [5] / TIMA1_C1N [6] / TIMA0_C2N [7] /
FCC_IN [8]
9 31 20 19 12 Standard
39 PA17 A1_2 / OPA1_IN1- /
COMP0_IN1-
UART1_TX [2] / SPI1_SCK [3] / I2C1_SCL [4] /
TIMA0_C3 [5] / TIMG7_C0 [6] / TIMA1_C0 [7] 10 32 21 20 13
Standard
with
wake(2)
40 PA18
A1_3 / OPA1_IN1+ /
COMP0_IN1+ /
GPAMP_IN-
UART1_RX [2] / SPI1_PICO [3] / I2C1_SDA [4] /
TIMA0_C3N [5] / TIMG7_C1 [6] / TIMA1_C1 [7]/Default
BSL_Invoke
11 33 22 21 14
Standard
with
wake(2)
41 PA19 SWDIO [2] 12 34 23 22 15 High-
Speed
42 PA20 SWCLK [2] 13 35 24 23 16 Standard
46 PA21 A1_7 / COMP2_IN1- /
VREF-
UART2_TX [2] / TIMG8_C0 [3] / UART1_CTS [4] /
TIMA0_C0 [5] / TIMG6_C0 [6] 17 39 25 24 17 Standard
47 PA22 A0_7 / GPAMP_OUT /
OPA0_OUT
UART2_RX [2] / TIMG8_C1 [3] / UART1_RTS [4] /
TIMA0_C1 [5] / CLK_OUT [6] / TIMA0_C0N [7] /
TIMG6_C1 [8]
18 40 26 25 18 Standard
53 PA23 COMP1_IN1- / VREF+
UART2_TX [2] / SPI0_CS3 [3] / TIMA0_C3 [4] /
TIMG0_C0 [5] / UART3_CTS [6] / TIMG7_C0 [7]/
TIMG8_C0 [8]
24 43 27 26 19 Standard
54 PA24 A0_3 / OPA0_IN1-
UART2_RX [2] / SPI0_CS2 [3] / TIMA0_C3N [4] /
TIMG0_C1 [5] / UART3_RTS [6] / TIMG7_C1 [7] /
TIMA1_C1 [8]
25 44 28 27 20 Standard
55 PA25 A0_2 / OPA0_IN1+ UART3_RX [2] / SPI1_CS3 [3] / TIMG12_C1 [4] /
TIMA0_C3 [5] / TIMA0_C1N [6] 26 45 29 28 21 Standard
59 PA26
A0_1 / COMP0_IN0+ /
OPA0_IN0+ /
GPAMP_IN+
UART3_TX [2] / SPI1_CS0 [3] / TIMG8_C0 [4] /
TIMA_FAL0 [5] / CAN_TX [6] / TIMG7_C0 [7] 30 46 30 1 1 Standard
60 PA27 A0_0 / COMP0_IN0- /
OPA0_IN0-
RTC_OUT [2] / SPI1_CS1 [3] / TIMG8_C1 [4] /
TIMA_FAL2 [5] / CAN_RX [6] / TIMG7_C1 [7] 31 47 31 2 - Standard
3 PA28 UART0_TX [2] / I2C0_SDA [3] / TIMA0_C3 [4] /
TIMA_FAL0 [5] / TIMG7_C0 [6] / TIMA1_C0 [ 7] 35 3 – – - High-Drive
4 PA29 I2C1_SCL [2] / UART2_RTS [3] / TIMG8_C0 [4] /
TIMG6_C0 [5] 36 – – – - Standard
5 PA30 I2C1_SDA [2] / UART2_CTS [3] / TIMG8_C1 [4] /
TIMG6_C1 [5] 37 – – – - Standard
6 PA31
UART0_RX [2] / I2C0_SCL [3] / TIMA0_C3N [4] /
TIMG12_C1 [5] / CLK_OUT [6]/ TIMG7_C1 [7] /
TIMA1_C1 [8]
39 5 – – - High-Drive
12 PB0 UART0_TX [2] / SPI1_CS2 [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] 47 – – – - Standard
13 PB1 UART0_RX [2] / SPI1_CS3 [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] 48 – – – - Standard
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Table 6-1. Pin Attributes (continued)
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTU
RE
ANALOG DIGITAL [PIN FUNCTION] (1)
64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN
15 PB2
UART3_TX [2] / UART2_CTS [3] / I2C1_SCL [4] /
TIMA0_C3 [5] / UART1_CTS [6] / TIMG6_C0 [ 7] /
TIMA1_C0 [8]
50 14 – – - Standard
16 PB3
UART3_RX [2] / UART2_RTS [3] / I2C1_SDA [4] /
TIMA0_C3N[5] / UART1_RTS [6] / TIMG6_C1 [7] /
TIMA1_C1 [8]
51 15 – – - Standard
17 PB4 UART1_TX [2] / UART3_CTS [3] / TIMA1_C0 [4] /
TIMA0_C2 [5] / TIMA1_C0N [6] 52 – – – - Standard
18 PB5 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] /
TIMA0_C2N [5] / TIMA1_C1N [6] 53 – – – - Standard
23 PB6
UART1_TX [2] / SPI1_CS0 [3] / SPI0_CS1 [4] /
TIMG8_C0 [5] / UART2_CTS [6] / TIMG6_C0 [7] /
TIMA1_C0N [8]
58 20 – – - Standard
24 PB7
UART1_RX [2] / SPI1_POCI [3] / SPI0_CS2 [4] /
TIMG8_C1 [5] / UART2_RTS [6] / TIMG6_C1 [7] /
TIMA1_C1N [8]
59 21 – – - Standard
25 PB8 UART1_CTS [2] / SPI1_PICO [3] / TIMA0_C0 [4] /
COMP1_OUT [5] 60 22 – – - Standard
26 PB9 UART1_RTS [2] / SPI1_SCK [3] / TIMA0_C1 [4] /
TIMA0_C0N [5] 61 23 – – - Standard
27 PB10 TIMG0_C0 [2] / TIMG8_C0 [3] / COMP1_OUT [4] /
TIMG6_C0 [5] 62 – – – - Standard
28 PB11 TIMG0_C1 [2] / TIMG8_C1 [3] / CLK_OUT [4] /
TIMG6_C1 [5] 63 – – – - Standard
29 PB12 UART3_TX [2] / TIMA0_C2 [3] / TIMA_FAL1 [4] /
TIMA0_C1 [5] 64 – – – - Standard
30 PB13 UART3_RX [2] / TIMA0_C3 [3] / TIMG12_C0 [4] /
TIMA0_C1N [5] 1 – – – - Standard
31 PB14 SPI1_CS3 [2] / SPI1_POCI [3] / SPI0_CS3 [4] /
TIMG12_C1 [5] / TIMG8_IDX [6] / TIMA0_C0 [7] 2 24 – – - Standard
32 PB15 UART2_TX [2] / SPI1_PICO [3] / UART3_CTS [4] /
TIMG8_C0 [5] / TIMG7_C0 [6] 3 25 – – - Standard
33 PB16 UART2_RX [2] / SPI1_SCK [3] / UART3_RTS [4] /
TIMG8_C1 [5] / TIMG7_C1 [6] 4 26 – – - Standard
43 PB17 A1_4 / COMP1_IN2- UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] /
TIMA1_C0 [5] / TIMA0_C2 [6] 14 36 – – - Standard
44 PB18 A1_5 / COMP1_IN2+ UART2_RX [2] / SPI0_SCK [3] / SPI1_CS2 [4] /
TIMA1_C1 [5] / TIMA0_C2N [6] 15 37 – – - Standard
45 PB19 A1_6 / COMP2_IN1+ /
OPA1_IN0+
COMP2_OUT [2] / SPI0_POCI [3] / TIMG8_C1 [4] /
UART0_CTS [5] / TIMG7_C1 [6] 16 38 – – - Standard
48 PB20 A0_6 / OPA1_IN0-
SPI0_CS2 [2] / SPI1_CS0 [3] / TIMA0_C2 [4] /
TIMG12_C0 [5] / TIMA_FAL1 [6] / TIMA0_C1 [7] /
TIMA1_C1N [8]
19 41 – – - Standard
49 PB21 COMP2_IN0+ SPI1_POCI [2] / TIMG8_C0 [3] 20 – – – - Standard
50 PB22 COMP2_IN0- SPI1_PICO [2] / TIMG8_C1 [3] 21 – – – - Standard
51 PB23 SPI1_SCK [2] / COMP0_OUT [3] / TIMA_FAL0 [4] 22 – – – - Standard
52 PB24 A0_5 / COMP1_IN1+ SPI0_CS3 [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG12_C1 [5] / TIMA0_C1N [6] / TIMA1_C0N [7] 23 42 – – - Standard
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Table 6-1. Pin Attributes (continued)
PINCMx PIN
NAME
SIGNAL NAMES PIN NUMBER
IO
STRUCTU
RE
ANALOG DIGITAL [PIN FUNCTION] (1)
64 LQFP 48 LQFP, VQFN 32 VQFN 28 VSSOP 24 VQFN
56 PB25 A0_4 UART0_CTS [2] / SPI0_CS0 [3] / TIMA_FAL2 [4] 27 – – – - Standard
57 PB26 COMP1_IN0+ UART0_RTS [2] / SPI0_CS1 [3] / TIMA0_C3 [4] /
TIMG6_C0 [5] / [6] 28 – – – 22 Standard
58 PB27 COMP1_IN0- COMP2_OUT [2] / SPI1_CS1 [3] / TIMA0_C3N [4] /
TIMG6_C1 [5] / TIMA1_C1 [6] 29 – – – - Standard
(1) Set PINCM.PF and PINCM.PC in IOMUX to 0 for analog functions (for example, OPA inputs or outputs, and COMP inputs). Each
digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired
Pin Function using the PINCM.PF control bits.
(2) Standard with Wake allows the I/O to wake up the device from the lowest low-power mode of SHUTDOWN. All I/O can be configured
to wakeup the MCU from higher low-power modes. See section GPIO FastWake in the MSPM0 G-Series 80-MHz Microcontrollers
Technical Reference Manual for details.
Table 6-2. Digital IO Features by IO Type
IO STRUCTURE INVERSION
CONTROL
DRIVE
STRENGTH
CONTROL
HYSTERESIS
CONTROL
PULLUP
RESISTOR
PULLDOWN
RESISTOR
WAKEUP
LOGIC
Standard drive Y Y Y
Standard drive with wake(2) Y Y Y Y
High drive Y Y Y Y Y
High speed Y Y Y Y
5-V tolerant open drain Y Y Y Y
6.3 Signal Descriptions
Table 6-3. Signal Descriptions
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
ADC
A0_0 31 47 31 2 – I ADC0 analog input 0
A0_1 30 46 30 1 22 I ADC0 analog input 1
A0_2 26 45 29 28 21 I ADC0 analog input 2
A0_3 25 44 28 27 20 I ADC0 analog input 3
A0_4 27 – – – – I ADC0 analog input 4
A0_5 23 42 – – – I ADC0 analog input 5
A0_6 19 41 – – – I ADC0 analog input 6
A0_7 18 40 26 25 18 I ADC0 analog input 7
A0_12 7 29 18 17 – I ADC0 analog input 12
A1_0 8 30 19 18 11 I ADC1 analog input 0
A1_1 9 31 20 19 12 I ADC1 analog input 1
A1_2 10 32 21 20 13 I ADC1 analog input 2
A1_3 11 33 22 21 14 I ADC1 analog input 3
A1_4 14 36 – – – I ADC1 analog input 4
A1_5 15 37 – – – I ADC1 analog input 5
A1_6 16 38 – – – I ADC1 analog input 6
A1_7 17 39 25 24 17 I ADC1 analog input 7
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
BSL BSL_invoke 11 33 22 21 14 I Input pin used to invoke bootloader
BSL (I2C) BSLSCL 34 2 2 5 1 I/O Default I2C BSL clock
BSLSDA 33 1 1 4 24 I/O Default I2C BSL data
BSL (UART) BSLRX 57 19 15 16 10 I Default UART BSL receive
BSLTX 56 18 14 15 9 O Default UART BSL transmit
CAN
CAN_TX 5
30
27
46
16
30 1 22 O CAN-FD transmit data
CAN_RX 6
31
28
47
17
31 2 – I CAN-FD receive data
Clock
CLK_OUT
7
18
39
49
55
56
63
5
13
17
18
29
40
11
13
14
18
26
14
15
17
25
8
9
19
O Configurable clock output
HFCLK_IN 46 12 10 13 – I Digital high-frequency clock input
HFXIN 45 11 9 12 – I Input for high-frequency crystal oscillator HFXT
HFXOUT 46 12 10 13 – O Output for high-frequency crystal oscillator HFXT
LFCLK_IN 44 10 8 11 7 I Digital low-frequency clock input
LFXIN 43 9 7 10 – I Input for low-frequency crystal oscillator LFXT
LFXOUT 44 10 8 11 7 O Output of low-frequency crystal oscillator LFXT
ROSC 42 8 6 9 5 I External resistor used for improving oscillator
accuracy
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
Comparator
COMP0_IN0- 31 47 31 2 – I Comparator 0 inverting input 0
COMP0_IN0+ 30 46 30 1 22 I Comparator 0 noninverting input 0
COMP0_IN1- 10 32 21 20 13 I Comparator 0 inverting input 1
COMP0_IN1+ 11 33 22 21 14 I Comparator 0 noninverting input 1
COMP0_IN2- 6 28 17 – – I Comparator 0 inverting input 2
COMP0_IN2+ 7 29 18 17 – I Comparator 0 noninverting input 2
COMP0_IN3+ 8 30 19 18 11 I Comparator 0 noninverting input 3
COMP0_OUT
22
49
57
13
19
11
15 16 10 O Comparator 0 output
COMP1_IN0- 29 – – – – I Comparator 1 inverting input 0
COMP1_IN0+ 28 – – – – I Comparator 1 noninverting input 0
COMP1_IN1- 24 43 27 26 19 I Comparator 1 inverting input 1
COMP1_IN1+ 23 42 – – – I Comparator 1 noninverting input 1
COMP1_IN2- 14 36 – – – I Comparator 1 inverting input 2
COMP1_IN2+ 15 37 – – – I Comparator 1 noninverting input 2
COMP1_IN3+ 8 30 19 18 11 I Comparator 1 noninverting input 3
COMP1_OUT
43
60
62
9
22 7 10 6 O Comparator 1 output
COMP2_IN0- 21 – – – – I Comparator 2 inverting input 0
COMP2_IN0+ 20 – – – – I Comparator 2 noninverting input 0
COMP2_IN1- 17 39 25 24 17 I Comparator 2 inverting input 1
COMP2_IN1+ 16 38 – – – I Comparator 2 noninverting input 1
COMP2_OUT
9
16
29
31
38 20 19 12 O Comparator 2 output
DAC DAC_OUT 8 30 19 18 11 O DAC output
Debug SWCLK 13 35 24 23 16 I Serial wire debug input clock
SWDIO 12 34 23 22 15 I/O Serial wire debug data input/output
FCC FCC_IN
5
9
33
45
1
11
27
31
1
9
16
20
4
12
19
12
14 I Frequency clock counter input
General-
Purpose
Amplifier
GPAMP_IN+ 30 46 30 1 22 I GPAMP noninverting terminal input
GPAMP_IN- 11 33 22 21 14 I GPAMP inverting terminal input
GPAMP_OUT 18 40 26 25 18 O GPAMP output
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
GPIO
PA0 33 1 1 4 24 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA1 34 2 2 5 1 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA2 42 8 6 9 5 I/O General-purpose digital I/O
PA3 43 9 7 10 6 I/O General-purpose digital I/O
PA4 44 10 8 11 7 I/O General-purpose digital I/O
PA5 45 11 9 12 – I/O General-purpose digital I/O
PA6 46 12 10 13 – I/O General-purpose digital I/O
PA7 49 13 11 – – I/O General-purpose digital I/O
PA8 54 16 12 – – I/O General-purpose digital I/O
PA9 55 17 13 14 8 I/O General-purpose digital I/O
PA10 56 18 14 15 9 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA11 57 19 15 16 10 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA12 5 27 16 – – I/O General-purpose digital I/O
PA13 6 28 17 – – I/O General-purpose digital I/O
PA14 7 29 18 17 – I/O General-purpose digital I/O
PA15 8 30 19 18 11 I/O General-purpose digital I/O
PA16 9 31 20 19 12 I/O General-purpose digital I/O
PA17 10 32 21 20 13 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA18 11 33 22 21 14 I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA19 12 34 23 22 15 I/O General-purpose digital I/O
PA20 13 35 24 23 16 I/O General-purpose digital I/O
PA21 17 39 25 24 17 I/O General-purpose digital I/O
PA22 18 40 26 25 18 I/O General-purpose digital I/O
PA23 24 43 27 26 19 I/O General-purpose digital I/O
PA24 25 44 28 27 20 I/O General-purpose digital I/O
PA25 26 45 29 28 21 I/O General-purpose digital I/O
PA26 30 46 30 1 22 I/O General-purpose digital I/O
PA27 31 47 31 2 – I/O General-purpose digital I/O
PA28 35 3 – – – I/O General-purpose digital I/O with wake up from
SHUTDOWN
PA29 36 – – – – I/O General-purpose digital I/O
PA30 37 – – – – I/O General-purpose digital I/O
PA31 39 5 – – – I/O General-purpose digital I/O with wake up from
SHUTDOWN
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MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
GPIO
PB0 47 – – – – I/O General-purpose digital I/O
PB1 48 – – – – I/O General-purpose digital I/O
PB2 50 14 – – – I/O General-purpose digital I/O
PB3 51 15 – – – I/O General-purpose digital I/O
PB4 52 – – – – I/O General-purpose digital I/O
PB5 53 – – – – I/O General-purpose digital I/O
PB6 58 20 – – – I/O General-purpose digital I/O
PB7 59 21 – – – I/O General-purpose digital I/O
PB8 60 22 – – – I/O General-purpose digital I/O
PB9 61 23 – – – I/O General-purpose digital I/O
PB10 62 – – – – I/O General-purpose digital I/O
PB11 63 – – – – I/O General-purpose digital I/O
PB12 64 – – – – I/O General-purpose digital I/O
PB13 1 – – – – I/O General-purpose digital I/O
PB14 2 24 – – – I/O General-purpose digital I/O
PB15 3 25 – – – I/O General-purpose digital I/O
PB16 4 26 – – – I/O General-purpose digital I/O
PB17 14 36 – – – I/O General-purpose digital I/O
PB18 15 37 – – – I/O General-purpose digital I/O
PB19 16 38 – – – I/O General-purpose digital I/O
PB20 19 41 – – – I/O General-purpose digital I/O
PB21 20 – – – – I/O General-purpose digital I/O
PB22 21 – – – – I/O General-purpose digital I/O
PB23 22 – – – – I/O General-purpose digital I/O
PB24 23 42 – – – I/O General-purpose digital I/O
PB25 27 – – – – I/O General-purpose digital I/O
PB26 28 – – – – I/O General-purpose digital I/O
PB27 29 – – – – I/O General-purpose digital I/O
I2C
I2C0_SCL
34
39
57
2
5
19
2
15
5
16
1
10 I/O I2C0 serial clock
I2C0_SDA
33
35
56
1
3
18
1
14
4
15
9
24 I/O I2C0 serial data
I2C1_SCL
8
10
36
44
50
57
10
14
19
30
32
8
15
19
21
11
16
18
20
7
10
11
13
I/O I2C1 serial clock
I2C1_SDA
9
11
37
43
51
56
9
15
18
31
33
7
14
20
22
10
15
19
21
6
9
12
14
I/O I2C1 serial data
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
Operational
Amplifier with
Chopping
(Zero-Drift
Op-Amp)
OPA0_IN0+ 30 46 30 1 22 I OPA0 noninverting terminal input 0
OPA0_IN1+ 26 45 29 28 21 I OPA0 noninverting terminal input 1
OPA0_IN2+ 8 30 19 18 11 I OPA0 noninverting terminal input 2
OPA0_IN0- 31 47 31 2 – I OPA0 inverting terminal input 0
OPA0_IN1- 25 44 28 27 20 I OPA0 inverting terminal input 1
OPA0_OUT 18 40 26 25 18 O OPA0 output
OPA1_IN0+ 16 38 – – I OPA1 noninverting terminal input 0
OPA1_IN1+ 11 33 22 21 14 I OPA1 noninverting terminal input 1
OPA1_IN2+ 8 30 19 18 11 I OPA1 noninverting terminal input 2
OPA1_IN0- 19 41 – – I OPA1 inverting terminal input 0
OPA1_IN1- 10 32 21 20 13 I OPA1 inverting terminal input 1
OPA1_OUT 9 31 20 19 12 O OPA1 output
Power
VSS 41 7 5 8 6 P Ground supply
VDD 40 6 4 7 5 P Power supply
VCORE 32 48 32 3 3 P Regulated core power supply output
QFN Pad – Pad Pad – Pad P QFN package exposed thermal pad. TI recommends
connection to VSS.
RTC RTC_OUT 31
55
17
47
13
31
2
14
2
10 O RTC clock output
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MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
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Table 6-3. Signal Descriptions (continued)
FUNCTION SIGNAL
NAME
PIN NO. (1)
PIN TYPE
(2) DESCRIPTION
64 PM 48 PT,
RGZ
32
RHB
28
DGS28
24
RGE
SPI
SPI0_CS0
27
42
54
8
16
6
12 9 7 I/O SPI0 chip-select 0
SPI0_CS1
23
28
43
58
9
20
42
7 10 – I/O SPI0 chip-select 1
SPI0_CS2
19
25
59
21
41
44
28 27 20 I/O SPI0 chip-select 2
SPI0_CS3
2
23
24
24
42
43
27 26 19 I/O SPI0 chip-select 3
SPI0_SCK
5
15
46
57
12
19
27
37
10
15
16
13
16
9
12
13
I/O SPI0 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI0_POCI
6
16
44
56
10
18
28
38
8
14
17
11
15 11 I/O SPI0 controller in/peripheral out
SPI0_PICO
7
14
45
55
11
17
29
36
9
13
18
12
14
17
8
10 I/O SPI0 controller out/peripheral in
SPI1_CS0
19
30
42
58
8
20
41
46
6
30
1
9
1
7I/O SPI1 chip-select 0
SPI1_CS1
14
29
31
36
47 31 2 2 I/O SPI1 chip-select 1
SPI1_CS2
8
15
47
30
37 19 18 – I/O SPI1 chip-select 2
SPI1_CS3
2
26
48
24
45 29 28 – I/O SPI1 chip-select 3
SPI1_SCK
4
10
22
61
23
26
32
21 20 14 I/O SPI1 clock signal input – SPI peripheral mode
Clock signal output – SPI controller mode
SPI1_POCI
2
9
20
59
21
24
31
20 19 – I/O SPI1 controller in/peripheral out
SPI1_PICO
3
11
21
60
22
25
33
22 21 15 I/O SPI1 controller out/peripheral in
System NRST 38 4 3 6 4 I Reset input active low
MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
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