CompuLab CM-T43 User manual

CM-T43
Reference Guide

Legal
Revised September 2017 CM-T43 Reference Guide 2
© 2016 Compulab Ltd.
All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a
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otherwise without the prior written permission of Compulab Ltd.
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reason of negligence) will be accepted by Compulab Ltd., its subsidiaries or employees for any
direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
Compulab Ltd. reserves the right to change details in this publication without notice.
Product and company names herein may be the trademarks of their respective owners.
Compulab Ltd.
P.O. Box 687 Yokneam Illit
20692 ISRAEL
Tel: [phone]
http://www.compulab.co.il
Fax: [phone]

Table of Contents
Revised September 2017 CM-T43 Reference Guide 3
Table of Contents
1INTRODUCTION..........................................................................................................6
1.1 About This Document..................................................................................................6
1.2 CM-T43 Part Number Legend.....................................................................................6
1.3 Related Documents......................................................................................................6
2OVERVIEW ...................................................................................................................7
2.1 Highlights ....................................................................................................................7
2.2 Block Diagram.............................................................................................................8
2.3 CM-T43 Features.........................................................................................................9
3CORE SYSTEM COMPONENTS .............................................................................11
3.1 Sitara AM437x SoC...................................................................................................11
3.2 PRU-ICSS..................................................................................................................12
3.3 Multimedia System....................................................................................................13
3.4 Memory......................................................................................................................13
3.4.1 DRAM..............................................................................................................13
3.4.2 Primary Storage (Boot-loader) .........................................................................13
3.4.3 Secondary Storage (OS & User data)...............................................................13
4PERIPHERAL INTERFACES...................................................................................14
4.1 Display Interface........................................................................................................16
4.2 Camera Interfaces (VPFE).........................................................................................18
4.3 Local Bus (GPMC)....................................................................................................19
4.4 Analog Audio.............................................................................................................23
4.5 Digital Audio (McASP).............................................................................................24
4.6 WLAN, Bluetooth and NFC......................................................................................26
4.7 Ethernet......................................................................................................................27
4.8 USB2.0.......................................................................................................................28
4.9 MMC / SD / SDIO.....................................................................................................29
4.10 UART....................................................................................................................32
4.11 I2C .........................................................................................................................34
4.12 SPI.........................................................................................................................35
4.13 Quad SPI (QSPI)...................................................................................................36
4.14 CAN Bus...............................................................................................................37
4.15 ADC and Resistive Touch-Screen ........................................................................38
4.16 HDQ / 1-Wire........................................................................................................39
4.17 GPIO .....................................................................................................................39
4.18 Enhanced Capture module (eCAP).......................................................................45
4.19 Enhanced PWM module (eHRPWM)...................................................................46
4.20 Quadrature Encoder Pulse module (eQEP)...........................................................48
4.21 PRU-ICSS.............................................................................................................50
4.21.1 PRU-ICSS MII .................................................................................................50
4.21.2 PRU-ICSS UART.............................................................................................52

Table of Contents
Revised September 2017 CM-T43 Reference Guide 4
4.21.3 PRU-ICSS Industrial Ethernet Peripheral ........................................................52
4.21.4 PRU-ICSS Industrial Capture interface (PRU-ICSS1 eCAP)..........................53
4.21.5 PRU-ICSS GPI / GPO......................................................................................54
4.22 Timers ...................................................................................................................57
4.23 General Purpose Clocks........................................................................................57
4.24 External DMA/Interrupt requests..........................................................................58
5SYSTEM LOGIC .........................................................................................................59
5.1 Power Supply.............................................................................................................59
5.2 Power Management ...................................................................................................59
5.3 Reset ..........................................................................................................................59
5.4 Boot Sequence ...........................................................................................................60
5.5 Signal Multiplexing Characteristics ..........................................................................61
5.6 Flash Write-protection...............................................................................................65
5.7 RTC............................................................................................................................65
5.8 LED............................................................................................................................65
6CARRIER BOARD INTERFACE .............................................................................66
6.1 Connector Pinout .......................................................................................................66
6.2 Mating Connectors.....................................................................................................75
6.3 Mechanical Drawings................................................................................................76
6.4 Standoffs/Spacers ......................................................................................................77
7OPERATIONAL CHARACTERISTICS ..................................................................78
7.1 Absolute Maximum Ratings......................................................................................78
7.2 Recommended Operating Conditions........................................................................78
7.3 DC Electrical Characteristics.....................................................................................78
7.4 ESD Performance ......................................................................................................78
7.5 Operating Temperature Ranges.................................................................................78
8APPLICATION NOTES .............................................................................................79
8.1 Carrier Board Design Guidelines...............................................................................79
8.2 Carrier Board Troubleshooting..................................................................................79
8.3 Ethernet Magnetics Implementation..........................................................................80
8.3.1 Magnetics Selection..........................................................................................80
8.3.2 Magnetics Connection......................................................................................80

Revision Notes
Revised September 2017 CM-T43 Reference Guide 5
Table 1 Revision Notes
Date
Description
Dec 2015
First release
Jan 2016
Bugfix release:
Updated company logo and document layout.
Added notes and revised signals tables for all signals on the following
CM-T43 pins (across the whole document): 4, 16, 30, 32, 34, 36, 38,
39, 40, 41, 42, 43, 44, 47, 48, 50, 51, 57, 59, 100, 102, 104, 106, 108,
110, 112, 116, 117, 118, 120, 122, 124, 126, 128, 130, 133, 134, 136,
138, 140, 149, 151, 153, 155, 161, 163, 192, 202.
Revised note in chapter 5.6
Revised pinout table for better readability
Revised spacers information (chapter 6.4)
Attached excel pinout table into this document
Fixed pin# of signal RTC_WAKEUP in table 62 to pin # 179
Added a new chapter describing EEPROM/SPI-Flash write protection
feature.
Aug 2016
Documented the effect of ‘N16G’(16GB onboard eMMC storage) option
on signals availability throughout chapters 4, 5 and the attached pinmux
excel table.
Aug 2017
Updated links for related documents in table 2.
Updated MTTF specifications in table 4.
Updated functionality description for pin 181 in section 5.2.
Please check for a newer revision of this manual at the CompuLab web site
http://www.compulab.co.il/. Compare the revision notes of the updated manual from the web site
with those of the printed or electronic version you have.

Introduction
Revised September 2017 CM-T43 Reference Guide 6
1 INTRODUCTION
1.1 About This Document
This document is part of a set of reference documents providing information necessary to operate
and program CompuLab CM-T43 Computer-on-Module.
1.2 CM-T43 Part Number Legend
Please refer to the CompuLab website ‘Ordering information’ section to decode the CM-T43 part
number: http://www.compulab.co.il/products/computer-on-modules/cm-t43/#ordering.
1.3 Related Documents
For additional information, refer to the documents listed in Table 2.
Table 2 Related Documents
Document
Location
CM-T43 Developer Resources
http://www.compulab.com/
Sitara AM437x Reference Manual
http://www.ti.com/product/AM4377/technicaldocuments
Sitara AM437x Datasheet
http://www.ti.com/product/AM4377/technicaldocuments

Overview
Revised September 2017 CM-T43 Reference Guide 7
2 OVERVIEW
2.1 Highlights
Texas Instruments Sitara AM437x ARM Cortex-A9 processor @ up to 1.0GHz
NEON™ SIMD Coprocessor and Vector – Interrupt Controller Floating Point (VFPv3)
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
(PRU-ICSS).
Up to 1GB DDR3
Up to 32GB on-board eMMC or raw SLC NAND storage
SGX530 Graphics Engine
1Gbit Ethernet × 2, USB2.0 Host/Device × 1, USB2.0 Host ×1, UART × 6, SDIO × 3,
ADC × 16, CAN bus × 2, Onboard WiFi IEEE 802.11a/b/g/n/ac, Onboard Bluetooth 4.0
(supports Low Energy), Onboard NFC.
Miniature size: 36 × 68 x 5 mm
SB-SOM-T43 carrier board turns the CM-T43 system on module (CoM/SoM) into SBC-
T43, a single board computer

Overview
Revised September 2017 CM-T43 Reference Guide 8
2.2 Block Diagram
Figure 1 CM-T43 Block Diagram
Texas
Instruments
AM437x
SPI0
USB2.0
DDR3
Memory
Controller
SPI Flash
(primary
bootloader
storage)
Wolfson Audio
Codec
I2C
EEPROM
(board info)
DDR3
(Up to 1GB) 32bit
ARM
Cortex-A9
TPS65218
PMIC
Marvell
88W8897 Based
WLAN+BT+NFC
Stereo
Multifunctional signals (muxed)
2 Ethernet Ports
(1Gbps)
Local bus
3 x I2C
2 x McASP
Parallel 24bit
Display
6 x UART
5 x McSPI
2 x VPFE
3D
acceleration
(SGX530) 1 x 1-WIRE
3 x SD/SDIO
204-pin SODIMMedge connector
6 x Timers/PWM
McASP0
I2C0
Optional Bypass
USB2.0 OTG
USB2.0 Host
1Gbit PHY
1Gbit PHY
RGMII1
RGMII2
1Gbit Eth
1Gbit Eth
MMC2
Optional Bypass
8x General Purpose ADC / Resistive Touch
8x General Purpose ADC
Backup Battery Power
2 x CAN
133 x GPIO
1 x QuadSPI
3 x eCAP
6 x eHRPWM
3 x eQEP
PRU GPIO
1 x PRU UART
1 x PRU eCAP
Cryptographic
Engine
Integrated
Ethernet
switch
1 x JTAG
TestPoints JTAG
Optional Bypass
Optional Bypass
Local bus (GPMC)
Power
Power
Power
up to 1x Parallel Display (24bit max)
up to 1x Remote Frame Buffer
up-to 3x Capture interfaces (eCAP)
up-to 6x PWM interfaces (eHRPWM)
up-to 6x Timer/PWM interfaces
up-to 3x Quadrature encoder
up to 2x Camera (VPFE)
up-to 4x SPI
up-to 6x UART
up-to 2x I2C Bus
up-to 2x I2S/McASP
up-to 133x GPIOs
up-to 3x SD/SDIO/MMC (1/4/8-bit)
up-to 1x HDQ/SIO 1-wire
up-to 2x CAN bus
up-to 1x Quad SPI
MMC1
SLC NAND Flash
(128MB - 512MB)
or
eMMC
(4GB - 32GB)
ADC0
USB2.0
ADC1
RTC
Stereo
Microphone
up-to 1x PRU-ICSS1 UART
up-to 1x PRU-ICSS1 eCAP
up-to 6x Industrial Ethernet digital outputs
up-to 8x Industrial Ethernet digital inputs
up-to 2x PRU-ICSS1 MII (ethernet)
up-to 13x PRU-ICSS1 GPI
up-to 12x PRU-ICSS1 GPO
up-to 40x PRU-ICSS0 GPIO
Two
PRU-ICSS
cores
PRU MII
PRU Industrial
Ethernet
Optional Bypass

Overview
Revised September 2017 CM-T43 Reference Guide 9
2.3 CM-T43 Features
The "Option" column specifies the CoM/SoM configuration option required to have the particular
feature. When a CoM/SoM configuration option is prefixed by “NOT”, the particular feature is
only available when the option is not used. A feature is only available when a CoM/SoM
configuration complies with all options denoted in the “Option” column.
"+" means that the feature is always available.
Table 3 Features and Configuration options
Feature
Description
Option
CPU Core and Graphics
CPU
Texas Instruments Sitara AM4379 ARM Cortex-A9, 1GHz
NEON™ SIMD and VFPv3
C1000M
Texas Instruments Sitara AM4376 ARM Cortex-A9, 800MHz
NEON™ SIMD and VFPv3
C800
Graphics
Acceleration Unit
PowerVR SGX530 GPU supporting Direct3D Mobile, OpenGL-ES 2.0
and OpenVG 1.0
C1000M
Real-Time
Coprocessor
Programmable Real-Time Unit Subsystem supporting 1588, BiSS,
EnDat 2.2, EtherCAT, EtherNet/IP, Ethernet POWERLINK,
HIPERFACE DSL, PROFIBUS, PROFINET RT/IRT, SERCOS III and
Sigma Delta Filter protocols
C1000M
Programmable Real-Time Unit Subsystem supporting 1588, BiSS,
EnDat 2.2, EtherNet/IP, HIPERFACE DSL, PROFIBUS, PROFINET
RT/IRT, SERCOS III and Sigma Delta Filter protocols
C800
Memory and Storage
RAM
128MB –1GB, DDR3-800, 32-bit data bus
D
Storage
On-board SLC NAND flash, 128MB - 512MB
N
On-board eMMC flash, 4GB - 32GB
Display and Camera
Display
Parallel 24-bit display interface - up to 100 Mpixels/sec
+
Remote frame buffer interface
+
Touchscreen
On-board 4/5/8-wire resistive touch-screen controller
+
Capacitive touch-screen support through SPI and I2C interfaces
+
Camera
Primary 12-bit parallel camera (VPFE) interface
+
Secondary 12-bit parallel camera (VPFE) interface
not WB
Network
Gigabit Ethernet
Primary 1000/100/10Mbps Ethernet port (MAC+PHY)
E1
Secondary 1000/100/10Mbps Ethernet port (MAC+PHY)
E2
WiFi
Dual-band, dual-antenna 2x2 MIMO 802.11ac/a/b/g/n WiFi interface
WB
Bluetooth
Bluetooth 4.0 (low energy)
WB
NFC
NFC - full protocol support for ISO 14443A/B, ISO 18092 and ISO
15693
WB
Audio
Analog Audio
Audio codec with analog stereo output, stereo input and electret
microphone support
A
Digital Audio
I2S compliant digital audio interface
not A
I/O
Local Bus
External local bus interface, variable rate up to 100 MHz, up-to 16-bit
+
USB
USB2.0 high-speed dual-role (host / device) port
+
USB2.0 high-speed host port
+
Serial Ports (UARTs)
Up to 6 UART ports, 16C750 compatible, 3.3V interface, up to 3.6
Mbps
+
CAN bus
Up to 2 CAN bus interfaces, 3.3V levels
+
MMC/SD/SDIO
Up to 3 MMC/SD/SDIO interfaces
+
SPI
Up to 4 SPI bus interfaces
+
I2C
Up to 2 I2C interfaces
+
1-Wire
1-Wire interface
+
GPIO
Up to 133 multifunction signals. Can be used as GPIO (shared with other
functions)
+
ADC
Up to 16 general-purpose ADC channels
+
System Logic
RTC
Real time clock, powered by external lithium battery
+

Overview
Revised September 2017 CM-T43 Reference Guide 10
Table 4 Electrical, Mechanical and Environmental Specifications
Electrical Specifications
Supply Voltage
3.3V - 5.0V typ
Digital I/O voltage
3.3V
Active power consumption
TBD
Mechanical Specifications
Dimensions
36 × 68 x 5 mm
Weight
12 gram
Connectors
SODIMM-204
Environmental and Reliability
MTTF
> 200,000 hours
Operation temperature (case)
Commercial: 0° to 70° C
Extended: -20° to 70° C
Industrial: -40° to 85° C. Click for availability note
Storage temperature
-40° to 85° C
Relative humidity
10% to 90% (operation)
05% to 95% (storage)
Shock
50G / 20 ms
Vibration
20G / 0 - 600 Hz

Core system components
Revised September 2017 CM-T43 Reference Guide 11
3 CORE SYSTEM COMPONENTS
3.1 Sitara AM437x SoC
The TI Sitara AM437x high-performance system-on-chip (SoC) is built around the ARM Cortex-
A9 core. The SoC includes POWERVR SGX™ 3D graphics acceleration for rich graphical user
interfaces, as well as a co-processor for deterministic, real-time processing including industrial
communication protocols, such as EtherCAT®, PROFIBUS®, EnDat and others. Cryptographic
acceleration is also available in every CM-T43 device. Secure boot can also be made available for
anti-cloning and illegal software update protection.
Up to 1000-MHz Sitara™ ARM® Cortex®-A9 32-Bit RISC processor
NEON™ SIMD Coprocessor and Vector Floating Point (VFPv3) Coprocessor
32KB of Both L1 Instruction and Data Cache
256KB of L2 Cache or L3 RAM
SGX530 Graphics Engine
Crypto Hardware Accelerators (AES, SHA, RNG, DES and 3DES)
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
(PRU-ICSS)
Figure 2 SITARA AM437X Block Diagram

Core system components
Revised September 2017 CM-T43 Reference Guide 12
3.2 PRU-ICSS
The programmable real-time unit subsystem and industrial communication subsystem (PRU-
ICSS) is separate from the ARM core and allows independent operation and clocking for greater
efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time
protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos,
EnDat, and others. The PRU-ICSS enables EnDat and another industrial communication protocol
in parallel.
The PRU-ICSS consists of dual 32-bit RISC cores (Programmable Real-Time Units, or PRUs),
shared, data, and instruction memories, internal peripheral modules, and an interrupt controller
(INTC). The programmable nature of the PRU-ICSS, along with their access to pins, events and
all SoC resources, provides flexibility in implementing fast real-time responses, specialized data
handling operations, custom peripheral interfaces, and in offloading tasks from the other processor
cores of the SoC. Sitara AM437x contains two subsystems: PRU-ICSS1 and PRU-ICSS0. PRU-
ICSS1 is considered a superset of PRU-ICSS0.
The PRU cores within the subsystems have access to all resources on the SoC through the
Interface/OCP Master port, and the external host processors can access the PRU-ICSS resources
through the Interface/OCP Slave port. The 32-bit interconnect bus connects the various internal
and external masters to the resources inside the PRU-ICSS. The INTC handles system input
events and posts events back to the device-level host CPU.
The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate
independently or in coordination with each other and can also work in coordination with the
device-level host CPU. This interaction between processors is determined by the nature of the
firmware loaded into the PRU's instruction memories
The PRU is a processor optimized for performing embedded tasks that require manipulation of
packed memory mapped data structures, handling of system events that have tight real-time
constraints and interfacing with systems external to the SoC. The PRU is both very small and very
efficient at handling such tasks
Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, and EtherNet/IP™,
EnDat 2.2, and More
Two Programmable Real-Time Units (PRUs) Subsystems With Two PRU Cores Each
Each Core is a 32-Bit Load and Store RISC Processor Capable of Running at 200
MHz
12KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Instruction RAM with Single-Error
Detection (Parity)
8KB (PRU-ICSS1), 4KB (PRU-ICSS0) of Data RAM with Single-Error Detection
(Parity)
Single-Cycle 32-Bit Multiplier with 64-Bit Accumulator
Enhanced GPIO Module Provides Shift-In and Shift-Out Support and Parallel Latch
on External Signal
12KB (PRU-ICSS1 only) of Shared RAM with Single-Error Detection (Parity)
Three 120-Byte Register Banks Accessible by Each PRU
Interrupt Controller Module (INTC) for Handling System Input Events
Local Interconnect Bus for Connecting Internal and External Masters to the Resources
Inside the PRU-ICSS
Peripherals Inside the PRU-ICSS:
One UART Port with Flow Control Pins, Supports Up to 12 Mbps
One Enhanced Capture (eCAP) Module
Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
One MDIO Port
Industrial Communication is Supported by Two PRU-ICSS Subsystems

Core system components
Revised September 2017 CM-T43 Reference Guide 13
3.3 Multimedia System
CM-T43 multimedia capabilities are derived from the 2D/3D graphics accelerator (SGX)
subsystem of the Sitara AM437x SoC. The SGX subsystem can accelerate 2-dimensional (2D)
and 3-dimensional (3D) graphics applications. The subsystem is based on the POWERVR ® SGX
core from Imagination Technologies. SGX is a new generation of programmable POWERVR
graphic cores. The POWERVR ® SGX Main Features include the following:
2D and 3D graphics
Tile-based architecture
Universal scalable shader engine (USSE™) – multithreaded engine incorporating pixel
and vertex shader functionality
Advanced shader feature set: in excess of OpenGL2.0
Industry-standard API support: OpenGL ES 1.1 and 2.0, OpenVG v1.0.1
Fine-grained task switching, load balancing, and power management
Advanced geometry direct memory access (DMA) driven operation for minimum CPU
interaction
Programmable high-quality image anti-aliasing
Built in MMU
Fully virtualized memory addressing for OS operation in a unified memory architecture
Advanced and standard 2D operations [e.g., vector graphics, BLTs (block level transfers),
ROPs (raster operations)]
3.4 Memory
3.4.1 DRAM
CM-T43 is equipped with up to 1GB of onboard DDR3 memory. The DDR3 data bus is 32-bits
wide and operates at 400 MHz clock frequency (DDR3-800).
NOTE: CM-T43 boards with 128MB of DRAM (D128 option) feature a 16-bit wide DDR3
data bus.
3.4.2 Primary Storage (Boot-loader)
The CM-T43 is assembled with 2MBytes of SPI NOR flash. The SPI NOR flash is the primary
non-volatile memory device of CM-T43, used for the boot-loader and configuration blocks
storage.
3.4.3 Secondary Storage (OS & User data)
CM-T43 is available with optional secondary on-board storage designed to store the operating
system and user data. One of the following on-board non-volatile memory devices can be used as
the secondary on-board storage.
On-board eMMC flash (up to 32GBytes).
On-board raw SLC NAND Flash (up to 1GBytes).
The secondary storage device is designed to store the operating system (kernel & root filesystem)
and general purpose (user) data.

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 14
4 PERIPHERAL INTERFACES
CM-T43 implements a variety of peripheral interfaces through the SODIMM-204 carrier board
connector. The following notes apply to interfaces available through the SODIMM-204 interface:
Some interfaces/signals are available only with/without certain configuration options of CM-
T43. The availability restrictions of each signal are described in the “Signals description”
table for each interface.
Many of the CM-T43 carrier board interface pins are multifunctional. Up-to 10 functions
(ALT modes) are accessible through each multifunctional pin. Multifunctional pins are
denoted with an asterisk (*). For additional details, please refer to chapter 5.5 of this
document.
Only one multifunctional pin can be used for each function, configuring several
multifunctional pins to implement the same function will result in unexpected system
behavior.
All of the CM-T43 digital interfaces operate at 3.3V voltage levels, unless otherwise noted.
The signals for each interface are described in the “Signal description” table for the interface in
question. The following notes provide information on the “Signal description” tables:
“Signal name” –The name of each signal with regards to the discussed interface. The signal
name corresponds to the relevant function in cases where the carrier board pin in question is
multifunctional.
“Pin#” – The carrier board interface pin number where the discussed signal is available,
multifunctional pins are denoted with an asterisk.
“Type” – Signal type, see the definition of different signal types below
“Description” – Signal description with regards to the interface in question.
“Availability” – Depending on CM-T43 Configuration options, certain carrier board
interface pins are physically disconnected (floating) from the carrier board interface
connector on-board CM-T43. The “Availability” column summarizes configuration
requirements for each signal. All the listed requirements must be met (logical AND) for a
signal to be “available” unless otherwise noted.
Each described signal can be one of the following types. Signal type is noted in the “Signal
description” tables. Multifunctional pin direction, pull resistor and open drain functionality is
software controlled. The “Type” column header for multifunctional pins refers to the recommended
pin configuration with regards to the discussed signal.
“AI” –Analog Signal Input
“AO” –Analog Signal Output
“AIO” –Analog Signal Input/Output
“APO” –Analog Power Output
“API” –Analog Power Input
“I” –Digital Input
"O" –Digital Output
“IO” –Digital Input/Output
“IOD” –Open Drain Signal (not pulled up on-board CM-T43 unless otherwise noted).
“PI” –Power Input
“PO” –Power Output
“SPU” – Software controlled pull up to 3.3V
“SPD” – Software controlled pull down to GND
"PU18" –Always pulled up to 1.8V on-board CM-T43, (typ. 5KΩ-15KΩ).

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 15
"PU33" –Always pulled up to 3.3V on-board CM-T43, (typ. 5KΩ-15KΩ).
"PUSUPPLY" –Always pulled up to 3.3V - 5.0V on-board CM-T43, (typ. 5KΩ-15KΩ).
"PD" - Always pulled down on-board CM-T43, (typ. 5KΩ-15KΩ).

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 16
4.1 Display Interface
CM-T43 Display interface is derived from the Sitara AM437x display subsystem (DSS). The DSS
can operate in one of the following modes (depending on software configuration)
RFBI mode (implements MIPI-DBI 2.0 protocol) and supports the following features:
8/9/12/16-bit parallel interface (up to QVGA@30fps)
Two programmable configurations for two devices connected to the RFBI module.
Tearing Effect control logic (Horizontal Synchronization (HSync) and Vertical
Synchronization (VSync) embedded in a single signal (TE) or using two signals
(HS+VS))
Programmable pixel memory formats (12-, 16-, 18- and 24-bit-per-pixel modes in RGB
format)
Programmable output formats on one/multiple cycles per pixel (data from Display
controller and from L4) (TDM)
BYPASS mode (implements MIPI-DPI 1.0 protocol), commonly known as the parallel RGB
interface. The following features are supported in bypass mode:
Programmable pixel rate (up to 100 MHz)
Programmable pixel memory formats (Palletized: 1, 2, 4, 8-bit per pixel; RGB 16, and 24-
bit per pixel and YUV 4:2:2)
Programmable display size (up to 2048 x 2048)
256 x 24-bit entries palette in RGB
For additional details on DSS, please refer to the Sitara AM437x technical reference manual.
The table below summarizes the display interface signals
Table 5 Display Interface Signals
Signal Name
Pin #
Type
Description
Availability
DSS_AC_BIAS_EN
104*^
O; PU33
AC Bias Enable / RFBI Command/Data
indicator
10KΩ Pull Up onboard CM-T43
Always
DSS_DATA0
106*^
IO;
PU33/PD
Pixel Data Bus / RFBI Data; Pulled high/low
on SoM when normal/alternate boot sequence
is selected respectively
Always
DSS_DATA1
108*^
IO;
PD/PU33
Pixel Data Bus / RFBI Data; Pulled low/high
on SoM when normal/alternate boot sequence
is selected respectively
Always
DSS_DATA10
128*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA11
130*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA12
134*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA13
136*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA14
138*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA15
140*^
IO; PU33
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA16
94*
O
Pixel Data Bus / RFBI Data
Always
DSS_DATA16
131*
O
Pixel Data Bus / RFBI Tearing Effect or
Vertical Sync 0
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA17
92*
O
Pixel Data Bus / RFBI Tearing Effect or
Horizontal Sync 0
Always

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 17
Signal Name
Pin #
Type
Description
Availability
DSS_DATA17
133*
O
Pixel Data Bus / RFBI Tearing Effect or
Horizontal Sync 0
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA18
142*
O
Pixel Data Bus / RFBI Tearing Effect or
Vertical Sync 1
Always
DSS_DATA18
163*
O
Pixel Data Bus / RFBI Tearing Effect or
Vertical Sync 1
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA19
144*
O
Pixel Data Bus / RFBI Tearing Effect or
Horizontal Sync 1
Always
DSS_DATA19
161*
O
Pixel Data Bus / RFBI Tearing Effect or
Horizontal Sync 1
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA2
110*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA20
146*
O
Pixel Data Bus / RFBI Chip Select 0
Always
DSS_DATA20
149*
O
Pixel Data Bus
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA21
148*
O
Pixel Data Bus
Always
DSS_DATA21
151*
O
Pixel Data Bus
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA22
74*
O
Pixel Data Bus
Always
DSS_DATA22
153*
O
Pixel Data Bus
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA23
76*
O
Pixel Data Bus
Always
DSS_DATA23
155*
O
Pixel Data Bus
Without
"N4G"
Without
"N16G"
Without
"N32G"
DSS_DATA3
112*^
IO;
PU33/PD
Pixel Data Bus / RFBI Data; Pulled high/low
on
SoM when normal/alternate boot sequence is
selected respectively
Always
DSS_DATA4
116*^
IO;
PD/PU33
Pixel Data Bus / RFBI Data; Pulled low/high
on SoM when normal/alternate boot sequence
is selected respectively
Always
DSS_DATA5
118*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA6
120*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA7
122*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA8
124*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_DATA9
126*^
IO; PD
Pixel Data Bus / RFBI Data
10KΩ Pull Down onboard CM-T43
Always
DSS_HSYNC
100*^
O; PD
Horizontal Sync / RFBI Chip Select 0
Always

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 18
Signal Name
Pin #
Type
Description
Availability
10KΩ Pull Down onboard CM-T43
DSS_PCLK
98*
O
Pixel Clock / RFBI Read 1 Enable
Always
DSS_VSYNC
102*^
O; PD
Always
NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to
chapter 5.5 of this document
NOTE: Pins denoted with "^" must not be pulled or driven by carrier board during SoM
power-up / reset.
4.2 Camera Interfaces (VPFE)
CM-T43 camera interfaces are derived from the Sitara AM437x integrated Video Port Front End
(VPFE) modules. CM-T43 includes two instantiations of the VPFE for connection to CCD cameras
or BT.656 compliant video encoders. The following main features are supported:
Dual Port 8- and 10-Bit BT656 Interface
Dual Port 8- and 10-Bit Including External Syncs
Single Port 12-Bit
YUV422/RGB422 and BT656 Input Format
RAW Format
Pixel Clock Rate Up to 75 MHz
For additional details on VPFE, please refer to the Sitara AM437x technical reference manual. The
tables below summarize the camera interface signals
Table 6 Camera Port 0 Interface Signals
Signal Name
Pin #
Type
Description
Availability
CAM0_DATA0
109*
I
Camera/VPFE data
Always
CAM0_DATA1
107*
I
Camera/VPFE data
Always
CAM0_DATA10
99*
I
Camera/VPFE data
Always
CAM0_DATA10
148*
I
Camera/VPFE data
Always
CAM0_DATA11
127*
I
Camera/VPFE data
Always
CAM0_DATA11
146*
I
Camera/VPFE data
Always
CAM0_DATA2
121*
I
Camera/VPFE data
Always
CAM0_DATA3
119*
I
Camera/VPFE data
Always
CAM0_DATA4
97*
I
Camera/VPFE data
Always
CAM0_DATA5
75*
I
Camera/VPFE data
Always
CAM0_DATA6
73*
I
Camera/VPFE data
Always
CAM0_DATA7
81*
I
Camera/VPFE data
Always
CAM0_DATA8
142*
I
Camera/VPFE data
Always
CAM0_DATA9
92*
I
Camera/VPFE data
Always
CAM0_FIELD
148*
IO
CCD Data Field Indicator
Always
CAM0_HD
76*
IO
CCD Data Horizontal Detect
Always
CAM0_PCLK
144*
I
CCD Data Pixel Clock
Always
CAM0_VD
74*
IO
CCD Data Vertical Detect
Always
CAM0_WEN
146*
I
CCD Data Write Enable
Always
Table 7 Camera Port 1 Interface Signals
Signal Name
Pin #
Type
Description
Availability
CAM1_DATA0
101*
I
Camera/VPFE data
Always
CAM1_DATA1
103*
I
Camera/VPFE data
Always
CAM1_DATA10
99*
I
Camera/VPFE data
Always
CAM1_DATA10
121*
I
Camera/VPFE data
Always
CAM1_DATA10
148*
I
Camera/VPFE data
Always
CAM1_DATA11
119*
I
Camera/VPFE data
Always
CAM1_DATA11
127*
I
Camera/VPFE data
Always

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 19
Signal Name
Pin #
Type
Description
Availability
CAM1_DATA11
146*
I
Camera/VPFE data
Always
CAM1_DATA2
89*
I
Camera/VPFE data
Without "WB"
CAM1_DATA3
91*
I
Camera/VPFE data
Without "WB"
CAM1_DATA4
77*
I
Camera/VPFE data
Without "WB"
CAM1_DATA5
79*
I
Camera/VPFE data
Without "WB"
CAM1_DATA6
83*
I
Camera/VPFE data
Without "WB"
CAM1_DATA7
85*
I
Camera/VPFE data
Without "WB"
CAM1_DATA8
93*
I
Camera/VPFE data
Always
CAM1_DATA8
107*
I
Camera/VPFE data
Always
CAM1_DATA9
94*
I
Camera/VPFE data
Always
CAM1_DATA9
109*
I
Camera/VPFE data
Always
CAM1_FIELD
99*
IO
CCD Data Field Indicator
Always
CAM1_HD
115*
IO
CCD Data Horizontal Detect
Always
CAM1_PCLK
95*
I
CCD Data Pixel Clock
Always
CAM1_VD
113*
IO
CCD Data Vertical Detect
Always
CAM1_WEN
97*
I
CCD Data Write Enable
Always
CAM1_WEN
127*
I
CCD Data Write Enable
Always
NOTE: Pins denoted with "*" are multifunctional. For additional details please refer to
chapter 5.5 of this document
4.3 Local Bus (GPMC)
The Local bus interface available with CM-T43 is derived from the general-purpose memory
controller (GPMC) IP built into the Sitara AM437x SoC. The GPMC is a unified memory controller
dedicated to interfacing external memory devices such as SRAM-Like memories, NAND, NOR and
Pseudo-SRAM devices. The following main features are supported with by the GPMC:
Data path to external memory device can be 16- or 8-bit wide
32-bit OCPIP 2.0 compliant core, single slave interface. Support non-wrapping and wrapping
burst up to 16x32bits.
Up to 100 MHz external memory clock performance (single device)
Address and Data multiplexed access
Support 512M Bytes maximum addressing capability which can be divided into seven
independent chip-select with programmable bank size and base address on 16M Bytes, 32M
Bytes, 64M Bytes, or 128M Bytes boundary
Each chip-select as independent and programmable control signal timing parameters for Setup
and Hold time
Flexible internal access time control (wait state) and flexible handshake mode using external
WAIT pins monitoring (up to two WAIT pins)
Bus keeping and bus turn-around support
Pre-fetch and write posting engine associated with system DMA to get full performance from
NAND device with minimum impact on NOR/SRAM concurrent access
On the fly ECC Hamming Code calculation to improve NAND usage reliability with
minimum impact on SW
Programmable auto-clock gating support
NOTE: Some of the GPMC signals are shared with onboard SLC NAND flash when CM-T43
configuration includes the “N128” or “N512” options.
For additional details on GPMC, please refer to the Sitara AM437x technical reference manual. The
table below summarizes the GPMC interface signals

Peripheral Interfaces
Revised September 2017 CM-T43 Reference Guide 20
Table 8 GPMC Interface Signals
Signal Name
Pin #
Type
Description
Availability
GPMC_A0
57*
O
GPMC Address
Without
"E2"
GPMC_A0
106*^
IO;
PU33/PD
GPMC Address; Pulled high/low on SoM
when normal/alternate boot sequence is
selected respectively
Always
GPMC_A1
44*
O
GPMC Address
Without
"E2"
GPMC_A1
102*^
O; PD
GPMC Address
Always
GPMC_A1
108*^
O;
PD/PU33
GPMC Address; Pulled low/high on SoM
when normal/alternate boot sequence is
selected respectively
Always
GPMC_A10
50*
O
GPMC Address
Without
"E2"
GPMC_A10
98*
O
GPMC Address
Always
GPMC_A11
42*
O
GPMC Address
Without
"E2"
GPMC_A11
104*^
O; PU33
GPMC Address
Always
GPMC_A12
124*^
O; PD
GPMC Address
Always
GPMC_A13
126*^
O; PD
GPMC Address
Always
GPMC_A14
128*^
O; PD
GPMC Address
Always
GPMC_A15
130*^
O; PD
GPMC Address
Always
GPMC_A16
57*
O
GPMC Address
Without
"E2"
GPMC_A16
134*^
O; PD
GPMC Address
Always
GPMC_A17
44*
O
GPMC Address
Without
"E2"
GPMC_A17
136*^
O; PD
GPMC Address
Always
GPMC_A18
36*
O
GPMC Address
Without
"E2"
GPMC_A18
138*^
O; PD
GPMC Address
Always
GPMC_A19
38*
O
GPMC Address
Without
"E2"
GPMC_A19
140*^
O; PU33
GPMC Address
Always
GPMC_A2
36*
O
GPMC Address
Without
"E2"
GPMC_A2
100*^
O; PD
GPMC Address
Always
GPMC_A2
110*^
O; PD
GPMC Address
Always
GPMC_A20
30*
O
GPMC Address
Without
"E2"
GPMC_A20
90*
O
GPMC Address
Always
GPMC_A21
32*
O
GPMC Address
Without
"E2"
GPMC_A21
88*
O
GPMC Address
Always
GPMC_A22
40*
O
GPMC Address
Without
"E2"
GPMC_A22
86*
O
GPMC Address
Always
GPMC_A23
47*
O
GPMC Address
Without
"E2"
GPMC_A23
84*
O
GPMC Address
Always
GPMC_A24
34*
O
GPMC Address
Without
"E2"
GPMC_A24
80*
O
GPMC Address
Always
GPMC_A25
48*
O
GPMC Address
Without
"E2"
GPMC_A25
82*
O
GPMC Address
Always
GPMC_A26
50*
O
GPMC Address
Without
"E2"
GPMC_A27
42*
O
GPMC Address
Without
"E2"
GPMC_A3
38*
O
GPMC Address
Without
"E2"
GPMC_A3
98*
O
GPMC Address
Always
GPMC_A3
112*^
O;
PU33/PD
GPMC Address; Pulled high/low on SoM
when normal/alternate boot sequence is
selected respectively
Always
GPMC_A4
30*
O
GPMC Address
Without
"E2"