CompuLab UCM-iMX93 User manual

UCM-iMX93
Reference Guide

Legal
Revised May 2023 UCM-iMX93 Reference Guide 2
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Table of Contents
Revised May 2023 UCM-iMX93 Reference Guide 3
Table of Contents
1INTRODUCTION ....................................................................................................... 6
1.1 About This Document ..................................................................................................6
1.2 UCM-iMX93 Part Number Legend ...............................................................................6
1.3 Related Documents .....................................................................................................6
2OVERVIEW............................................................................................................... 7
2.1 Highlights .....................................................................................................................7
2.2 Block Diagram ..............................................................................................................7
2.3 Specifications ...............................................................................................................8
3CORE SYSTEM COMPONENTS................................................................................. 10
3.1 i.MX93 System-on-Chip .............................................................................................10
3.2 Memory .....................................................................................................................10
3.2.1 DRAM................................................................................................................10
3.2.2 Bootloader and General Purpose Storage........................................................10
4PERIPHERAL INTERFACES ....................................................................................... 11
4.1 Display Interfaces.......................................................................................................12
4.1.1 MIPI-DSI ............................................................................................................12
4.1.2 LVDS Interface ..................................................................................................12
4.2 Camera Interface .......................................................................................................13
4.3 Audio Interfaces.........................................................................................................13
4.3.1 S/PDIF ...............................................................................................................13
4.3.2 SAI .....................................................................................................................14
4.3.3 MQS ..................................................................................................................15
4.4 Ethernet .....................................................................................................................16
4.4.1 Gigabit Ethernet ...............................................................................................16
4.4.2 RGMII ................................................................................................................17
4.5 WiFi and Bluetooth Interfaces...................................................................................19
4.6 USB.............................................................................................................................19
4.7 MMC / SD /SDIO ........................................................................................................20
4.8 FlexSPI........................................................................................................................21
4.9 UART ..........................................................................................................................22
4.10 CAN-FD ..................................................................................................................25
4.11 SPI..........................................................................................................................26
4.12 I2C .........................................................................................................................28
4.13 I3C .........................................................................................................................29
4.14 Timer/Pulse Width Modulation ............................................................................30
4.15 ADC........................................................................................................................31
4.16 Tamper ..................................................................................................................31

Table of Contents
Revised May 2023 UCM-iMX93 Reference Guide 4
4.17 JTAG.......................................................................................................................31
4.18 GPIO ......................................................................................................................31
5SYSTEM LOGIC ....................................................................................................... 34
5.1 Power Supply .............................................................................................................34
5.2 I/O Voltage Domains..................................................................................................34
5.3 System and Miscellaneous Signals ............................................................................34
5.3.1 Power management .........................................................................................34
5.4 Reset ..........................................................................................................................35
5.5 Boot Sequence...........................................................................................................35
5.6 Signal Multiplexing Characteristics............................................................................36
5.7 RTC .............................................................................................................................40
5.8 Reserved Pins.............................................................................................................40
5.9 Not Connected Pins ...................................................................................................40
6CARRIER BOARD INTERFACE................................................................................... 41
6.1Connectors Pinout .....................................................................................................41
6.2 Mating Connectors ....................................................................................................46
6.3 Mechanical Drawings.................................................................................................46
7OPERATIONAL CHARACTERISTICS........................................................................... 48
7.1 Absolute Maximum Ratings.......................................................................................48
7.2 Recommended Operating Conditions .......................................................................48
7.3 ESD Performance .......................................................................................................48
8APPLICATION NOTES.............................................................................................. 49
8.1 Carrier Board Design Guidelines................................................................................49
8.2 Carrier Board Troubleshooting ..................................................................................49

Revision Notes
Revised May 2023 UCM-iMX93 Reference Guide 5
Table 1 Revision Notes
Date
Description
Mar 2023
Initial release
Please check for a newer revision of this manual at the CompuLab website
https://www.compulab.com. Compare the revision notes of the updated manual from the
website with those of the printed or electronic version you have.

Introduction
Revised May 2023 UCM-iMX93 Reference Guide 6
1 INTRODUCTION
1.1 About This Document
This document is part of a set of reference documents providing information necessary to
operate and program CompuLab UCM-iMX93 System-on-Module.
1.2 UCM-iMX93 Part Number Legend
Please refer to the CompuLab website ‘Ordering information’ section to decode the UCM-iMX93
part number: https://www.compulab.com/products/computer-on-modules/ucm-imx93-nxp-i-
mx9-som-system-on-module-computer/#ordering.
1.3 Related Documents
For additional information, refer to the documents listed in Table 2.
Table 2 Related Documents
Document
Location
UCM-iMX93 Developer Resources
https://www.compulab.com/products/computer-on-
modules/ucm-imx93-nxp-i-mx9-som-system-on-module-
computer/#devres
i.MX93 Reference Manual
https://www.nxp.com/products/processors-and-
microcontrollers/arm-processors/i-mx-applications-processors/i-
mx-9-processors/i-mx-93-applications-processor-family-arm-
cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93
i.MX93 Datasheet

Overview
Revised May 2023 UCM-iMX93 Reference Guide 7
2 OVERVIEW
2.1 Highlights
NXP i.MX93 processor, up-to 1.7GHz
Up to 2GB LPDDR4 and 64GB eMMC
Integrated AI/ML Neural Processing Unit
LVDS, MIPI-DSI and MIPI-CSI
Certified 802.11ac WiFi, BT 5.3
GbE, RGMII, 2x USB, 2x CAN-FD, 7x UART
Tiny size and weight - 28 x 38 x 4 mm, 7 gram
2.2 Block Diagram
Figure 1 UCM-iMX93 Block Diagram

Overview
Revised May 2023 UCM-iMX93 Reference Guide 8
2.3 Specifications
The "Option" column specifies the CoM/SoM configuration option required to have the
particular feature. When a CoM/SoM configuration option is prefixed by “NOT”, the particular
feature is only available when the option is not used.
"+" means that the feature is always available.
Table 3 Features and Configuration options
Feature
Description
Option
CPU Core and Graphics
CPU
NXP i.MX9352, dual-core ARM Cortex-A55, 1.7GHz
C1700D
NXP i.MX9352, dual-core ARM Cortex-A55, 1.5GHz, industrial
temp. grade
C1500D
NXP i.MX9331, single-core ARM Cortex-A55, 1.7GHz
C1700S
NPU
AI/ML Neural Processing Unit
Arm® Ethos™ U-65 microNPU
C1700D
or
C1500D
Real-Time
Co-processor
ARM Cortex-M33, 250Mhz
+
Memory and Storage
RAM
512MB –2GB, LPDDR4
D
Storage
eMMC flash, 8GB - 64GB
N
Display, Camera and Audio
Display
MIPI-DSI, 4 data lanes, up to 1080p60
+
LVDS, 4 lanes, up to 1366x768 p60
+
Touchscreen
Capacitive touch-screen support through SPI and I2C interfaces
+
Camera
MIPI-CSI, 2 data lanes
+
Audio
Up-to 2x I2S / SAI
+
S/PDIF input/output
+
Network
Ethernet
Gigabit Ethernet port (MAC+PHY)
+
RGMII
Primary RGMII
not E
Secondary RGMII
+
WiFi
Certified 802.11ac WiFi
NXP 88W8997 chipset
WB
Bluetooth
Bluetooth 5.3 BLE
I/O
USB
2x USB2.0 dual-role ports
+
UART
Up to 7x UART
+
CAN bus
Up-to 2x CAN-FD
+
SD/SDIO
1x SD/SDIO
+
Additional 1x SD/SDIO
not WB
SPI
Up to 7x SPI
+
I2C
Up to 6x I2C
+
ADC
4x general-purpose ADC channels
PWM
Up to 6x PWM signals
+
GPIO
Up to 79x GPIO (multifunctional signals shared with other
functions)
+

Overview
Revised May 2023 UCM-iMX93 Reference Guide 9
Feature
Description
Option
System Logic
RTC
Real-time clock, powered by external battery
+
JTAG
JTAG debug interface
+
Table 4 Electrical, Mechanical and Environmental Specifications
Electrical Specifications
Supply Voltage
3.45V to 4.4V
Digital I/O voltage
3.3V / 1.8V
Mechanical Specifications
Dimensions
28 x 38 x 4 mm
Weight
7 gram
Connectors
2 x 100 pin, 0.4mm pitch
Environmental and Reliability
MTTF
> 200,000 hours
Operation
temperature (case)
Commercial: 0° to 70° C
Extended: -20° to 70° C -only with C1500D
Industrial: -40° to 85° C -only with C1500D
Storage
temperature
-40° to 85° C
Relative humidity
10% to 90% (operation)
05% to 95% (storage)
Shock
50G / 20 ms
Vibration
20G / 0 - 600 Hz

Core System Components
Revised May 2023 UCM-iMX93 Reference Guide 10
3 CORE SYSTEM COMPONENTS
3.1 i.MX93 System-on-Chip
The i.MX 93 System-on-Chip (SoC) includes powerful dual Arm® Cortex®-A55 processors with
speeds up to 1.7 GHz integrated with a NPU that accelerates machine learning inference. A
general-purpose Arm® Cortex®-M33 running up to 250 MHz is for real-time and low-power
processing.
Figure 2 i.MX 93 Block Diagram
3.2 Memory
3.2.1 DRAM
UCM-iMX93 is equipped with up to 2GB of onboard LPDDR4 memory. The LPDDR4 channel is 16-
bits wide.
3.2.2 Bootloader and General Purpose Storage
UCM-iMX93 uses on-board non-volatile memory (eMMC) storage for storing the bootloader. The
remaining eMMC space is intended to store the operating system (kernel & root filesystem) and
general purpose (user) data.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 11
4 PERIPHERAL INTERFACES
UCM-iMX93 implements a variety of peripheral interfaces through two 100-pin (0.4mm pitch)
carrier board connectors. The following notes apply to interfaces available through the carrier-
board connectors:
Some interfaces/signals are available only with/without certain configuration options of
the UCM-iMX93 SoM. The availability restrictions of each signal are described in the
“Signals description” table for each interface.
Some of the UCM-iMX93 carrier board interface pins are multifunctional. Up to 8
functions (ALT modes) are accessible through each multifunctional pin. For additional
details, please refer to chapter 5.6.
UCM-iMX93 uses different I/O voltage domains to power different groups of digital
signals. Some pin operate at 3.3V, some at 1.8V. Voltage domain of each signal is
specified in the “Signals description” table for each interface.
The signals for each interface are described in the “Signal description” table for the interface in
question. The following notes provide information on the “Signal description” tables:
“Signal name” –The name of each signal with regards to the discussed interface. The
signal name corresponds to the relevant function in cases where the carrier board pin in
question is multifunctional.
“Pin#” – Pin number on the carrier board interface connector
“Type” – Signal type, see the definition of different signal types below
“Description” – Signal description with regards to the interface in question
“Voltage Domain” –Voltage level of the particular signal
“Availability” – Depending on UCM-iMX93 configuration options, certain carrier board
interface pins are physically disconnected (floating). The “Availability” column
summarizes configuration requirements for each signal. All the listed requirements must
be met (logical AND) for a signal to be “available” unless noted otherwise.
Each described signal can be one of the following types. Signal type is noted in the “Signal
description” tables. Multifunctional pin direction, pull resistor, and open drain functionality is
software controlled. The “Type” column header for multifunctional pins refers to the
recommended pin configuration with regards to the discussed signal.
“AI” –Analog Input
“AO” –Analog Output
“AIO” –Analog Input/Output
“AP” –Analog Power Output
“I” –Digital Input
"O" –Digital Output
“IO” –Digital Input/Output
“P” –Power
"PD" - Always pulled down onboard UCM-iMX93, followed by pull value.
"PU" - Always pulled up onboard UCM-iMX93, followed by pull value.
“LVDS” -Low-voltage differential signaling.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 12
4.1 Display Interfaces
4.1.1 MIPI-DSI
The UCM-iMX93 MIPI-DSI interface is derived from the four-lane MIPI display interface available
on the i.MX93 SoC. The following main features are supported:
Compliant with MIPI DSI specification v1.2 and MIPI D-PHY specification v1.2
Maximum data rate per lane of 1.5 Gbps
Maximum resolution ranges up to 1920 x 1200 p60
The following table below summarizes the MIPI-DSI interface signals.
Table 5 MIPI-DSI Interface Signals
Signal Name
Pin #
Type
Description
Availability
DSI_CKN
P2-21
AO
Negative part of MIPI-DSI clock diff-pair
Always
DSI_CKP
P2-23
AO
Positive part of MIPI-DSI clock diff-pair
Always
DSI_DN0
P2-1
AO
Negative part of MIPI-DSI data diff-pair 0
Always
DSI_DP0
P2-2
AO
Positive part of MIPI-DSI data diff-pair 0
Always
DSI_DN1
P2-15
AO
Negative part of MIPI-DSI data diff-pair 1
Always
DSI_DP1
P2-17
AO
Positive part of MIPI-DSI data diff-pair 1
Always
DSI_DN2
P2-5
AO
Negative part of MIPI-DSI data diff-pair 2
Always
DSI_DP2
P2-7
AO
Positive part of MIPI-DSI data diff-pair 2
Always
DSI_DN3
P2-11
AO
Negative part of MIPI-DSI data diff-pair 3
Always
DSI_DP3
P2-13
AO
Positive part of MIPI-DSI data diff-pair 3
Always
4.1.2 LVDS Interface
UCM-iMX93 provides one LVDS interface derived from the i.MX93 LVDS display bridge. It
supports the following key features:
Single channel (4 lanes) output at up to 80MHz pixel clock
Resolutions of up to 1366 x 768 p60 or 1280 x 800 p60
The table below summarizes the LVDS interface signals.
Table 6 LVDS Interface Signals
Signal Name
Pin #
Type
Description
Availability
LVDS_CLK_N
P2-14
AO
Negative part of LVDS clock diff-pair
Always
LVDS_CLK_P
P2-12
AO
Positive part of LVDS clock diff-pair
Always
LVDS_D0_N
P2-26
AO
Negative part of LVDS data diff-pair 0
Always
LVDS_D0_P
P2-24
AO
Positive part of LVDS data diff-pair 0
Always
LVDS_D1_N
P2-20
AO
Negative part of LVDS data diff-pair 1
Always
LVDS_D1_P
P2-18
AO
Positive part of LVDS data diff-pair 1
Always
LVDS_D2_N
P2-8
AO
Negative part of LVDS data diff-pair 2
Always
LVDS_D2_P
P2-6
AO
Positive part of LVDS data diff-pair 2
Always
LVDS_D3_N
P2-4
AO
Negative part of LVDS data diff-pair 3
Always
LVDS_D3_P
P2-2
AO
Positive part of LVDS data diff-pair 3
Always

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 13
4.2 Camera Interface
UCM-iMX93 provides one MIPI-CSI interface, derived from the MIPI CSI host controller integrated
into the i.MX93 SoC. The controller supports the following main features:
Up to two data lanes and one clock lane
Complaint with MIPI CSI-2 specification v1.3 and MIPI D-PHY specification v1.2
Please refer to the i.MX93 Reference manual for additional details. The following table
summarizes MIPI-CSI signals.
Table 7 MIPI-CSI Interface Signals
Signal Name
Pin #
Type
Description
Availability
MIPI_CSI _CLK_N
P2-30
AI
Negative part of MIPI-CSI1 clock diff-pair
Always
MIPI_CSI _CLK_P
P2-32
AI
Positive part of MIPI-CSI1 clock diff-pair
Always
MIPI_CSI_D0_N
P2-31
AI
Negative part of MIPI-CSI1 data diff-pair 0
Always
MIPI_CSI_D0_P
P2-33
AI
Positive part of MIPI-CSI1 data diff-pair 0
Always
MIPI_CSI_D1_N
P2-35
AI
Negative part of MIPI-CSI11 data diff-pair 1
Always
MIPI_CSI_D1_P
P2-37
AI
Positive part of MIPI-CSI1 data diff-pair 1
Always
4.3 Audio Interfaces
4.3.1 S/PDIF
UCM-iMX93 provides one S/PDIF transmitter with one output and one S/PDIF receiver with one
input.
Please refer to the i.MX93 Reference manual for additional details. The following table
summarizes the S/PDIF interface signals.
Table 8 S/PDIF Interface Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SPDIF_IN
P1-79
I
SPDIF input data line signal
3.3V
Always
P2-43
1.8V
P2-47
1.8V
SPDIF_OUT
P1-81
O
SPDIF output data line signal
3.3V
Always
P2-47
1.8V
NOTE: S/PDIF signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 14
4.3.2 SAI
UCM-iMX93 supports up-to two of the i.MX93 integrated synchronous audio interface (SAI)
modules. The SAI module provides a synchronous audio interface (SAI) that supports full duplex
serial interfaces with frame synchronization, such as I2S, AC97, TDM, and codec/DSP interfaces.
The following main features are supported:
One transmitter with independent bit clock and frame sync supporting 1 data line. One
receiver with independent bit clock and frame sync supporting 1 data line.
Maximum Frame Size of 32 words.
Word size of between 8-bits and 32-bits. Separate word size configuration for the first
word and remaining words in the frame.
Asynchronous 32 × 32-bit FIFO for each transmit and receive channel
Please refer to the i.MX93 Reference manual for additional details. The tables below summarize
the SAI interface signals.
Table 9 SAI1 Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SAI1_MCLK
P1-19
IO
Audio master clock. An input when
generated externally and an output when
generated internally.
3.3V
Always
P1-45
3.3V
Always
SAI1_RX_DATA[0]
P1-45
I
Receive data, sampled synchronously by
the bit clock
3.3V
Always
SAI1_TX_DATA[0]
P1-53
O
Transmit data signal synchronous to bit
clock.
3.3V
Always
SAI1_TX_DATA[1]
P1-87
O
Transmit data signal synchronous to bit
clock.
3.3V
Always
SAI1_TX_BCLK
P1-51
O
Transmit bit clock. An input when
generated externally and an output when
generated internally.
3.3V
Always
SAI1_TX_SYNC
P1-87
O
Transmit frame sync. An input sampled by
bit clock when generated externally. A bit
clock synchronous output when generated
internally.
3.3V
Always
NOTE: SAI1 signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.
Table 10 SAI2 Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SAI2_MCLK
P2-45
IO
Audio master clock. An input when
generated externally and an output when
generated internally.
1.8V
Always
SAI2_RX_DATA[0]
P2-63
I
Receive data, sampled synchronously by
the bit clock
1.8V
Always
SAI2_RX_DATA[1]
P2-65
I
Receive data, sampled synchronously by
the bit clock
1.8V
Always
SAI2_RX_DATA[2]
P2-61
I
Receive data, sampled synchronously by
the bit clock
1.8V
Always
SAI2_RX_DATA[3]
P2-59
I
Receive data, sampled synchronously by
the bit clock
1.8V
Always
SAI2_RX_BCLK
P2-70
I
Receive bit clock. An input when
generated externally and an output when
generated internally.
1.8V
Always

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 15
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SAI2_RX_SYNC
P2-68
I
Receive frame sync. An input sampled by
bit clock when generated externally. A bit
clock synchronous output when generated
internally.
1.8V
Always
SAI2_TX_DATA[0]
P2-53
O
Transmit data signal synchronous to bit
clock.
1.8V
Always
SAI2_TX_DATA[1]
P2-55
O
Transmit data signal synchronous to bit
clock.
1.8V
Always
SAI2_TX_DATA[2]
P2-41
O
Transmit data signal synchronous to bit
clock.
1.8V
Always
SAI2_TX_DATA[3]
P2-43
O
Transmit data signal synchronous to bit
clock.
1.8V
Always
SAI2_TX_BCLK
P2-69
O
Transmit bit clock. An input when
generated externally and an output when
generated internally.
1.8V
Always
SAI2_TX_SYNC
P2-67
O
Transmit frame sync. An input sampled by
bit clock when generated externally. A bit
clock synchronous output when generated
internally.
1.8V
Always
NOTE: SAI2 signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.
4.3.3 MQS
UCM-iMX93 supports up-to two MOQ interfaces that can be used to generate medium quality
audio via standard GPIO.
Please refer to the i.MX93 Reference manual for additional details. The following table
summarizes the S/PDIF interface signals.
Table 11 MQS Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
MQS1_LEFT
P1-21
O
Left signal output
3.3V
Always
P1-87
3.3V
Always
MQS1_RIGHT
P1-23
O
Right signal output
3.3V
Always
P1-45
3.3V
Always
MQS2_LEFT
P1-71
O
Left signal output
1.8
Always
P2-47
1.8
Always
MQS2_RIGHT
P1-67
O
Right signal output
1.8
Always
P2-45
1.8
Always
NOTE: MQS signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 16
4.4 Ethernet
4.4.1 Gigabit Ethernet
UCM-iMX93 incorporates an optional (“E” configuration option) full-featured 10/100/1000
Ethernet interface implemented with Realtek RTL8211E GbE PHY.
The following main features are supported:
10/100/1000 BASE-T IEEE 802.3 compliant
IEEE 802.3u compliant Auto-Negotiation
Supports all IEEE 1588 frames - inside the MAC
Automatic channel swap (ACS)
Automatic MDI/MDIX crossover
Automatic polarity correction
Activity and speed indicator LED controls
The table below summarizes the GbE interface signals.
Table 12 GbE Interface Signals
Signal Name
Pin #
Type
Description
Availability
ETH0_LED_ACT
P2-83
Active High, activity LED driver.
3.3V signal, PHY strap
With 'E' option
ETH0_LINK-LED_10_100
P2-86
Active High, link, any speed
LED driver. 3.3V signal
With 'E' option
ETH0_LINK-LED_1000
P2-75
Active High, link, any speed , blinking on
transmit or receive
PHY strap
With 'E' option
ETH0_MDI0N
P2-73
AIO
Negative part of 100ohm diff-pair 0
With 'E' option
ETH0_MDI0P
P2-74
AIO
Positive part of 100ohm diff-pair 0
With 'E' option
ETH0_MDI1N
P2-80
AIO
Negative part of 100ohm diff-pair 1
With 'E' option
ETH0_MDI1P
P2-78
AIO
Positive part of 100ohm diff-pair 1
With 'E' option
ETH0_MDI2N
P2-81
AIO
Negative part of 100ohm diff-pair 2
With 'E' option
ETH0_MDI2P
P2-79
AIO
Positive part of 100ohm diff-pair 2
With 'E' option
ETH0_MDI3N
P2-85
AIO
Negative part of 100ohm diff-pair 3
With 'E' option
ETH0_MDI3P
P2-84
AIO
Positive part of 100ohm diff-pair 3
With 'E' option

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 17
4.4.2 RGMII
UCM-iMX93 features up-to two RMGII interfaces.
Primary RGMII interface ENET1 is available only when UCM-iMX93 is assembled without the “E”
configuration option.
Secondary RGMII interface ENET2 is available with all UCM-iMX93 configurations.
The tables below summarize the Ethernet RGMII interface signals.
Table 13 Primary RGMII ENET1 (QOS) Interface Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
ENET1_MDC
P2-60
O
Provides a timing reference to the PHY for
data transfers on the MDIO signal
1.8V
Only w/o
'E' option
ENET1_MDIO
P2-62
IO
Transfers control information between the
external PHY and the MAC. Data is
synchronous to MDC. This signal is an input
after reset
1.8V
Only w/o
'E' option
1.8V
Only w/o
'E' option
ENET1_RD0
P2-86
I
Ethernet input data from the PHY
1.8V
Only w/o
'E' option
ENET1_RD1
P2-83
I
Ethernet input data from the PHY
1.8V
Only w/o
'E' option
ENET1_RD2
P2-84
I
Ethernet input data from the PHY
1.8V
Only w/o
'E' option
ENET1_RD3
P2-85
I
Ethernet input data from the PHY
1.8V
Only w/o
'E' option
ENET1_RX_CTL
P2-81
I
Contains RX_EN on the rising edge of
RGMII_RXC, and RX_EN XOR RX_ER on the
falling edge of RGMII_RXC (RGMII mode)
1.8V
Only w/o
'E' option
ENET1_RXC
P2-78
I
Timing reference for RX_DATA[3:0] and
RX_CTL in RGMII MODE
1.8V
Only w/o
'E' option
ENET1_TD0
P2-75
O
Ethernet output data to PHY
1.8V
Only w/o
'E' option
ENET1_TD1
P2-80
O
Ethernet output data to PHY
1.8V
Only w/o
'E' option
ENET1_TD2
P2-77
O
Ethernet output data to PHY
1.8V
Only w/o
'E' option
ENET1_TD3
P2-74
O
Ethernet output data to PHY
1.8V
Only w/o
'E' option
ENET1_TXC
P2-79
O
Timing reference for TX_DATA[3:0] and
TX_CTL in RGMII MODE
1.8V
Only w/o
'E' option
ENET1_TX_CTL
P2-73
O
Contains TX_EN on the rising edge of
RGMII_TXC, and TX_EN XOR TX_ER on the
falling edge of RGMII_TXC (RGMII mode)
1.8V
Only w/o
'E' option
ENET1_1588_
EVENT0_IN
P2-92
I
1588 event input
3.3V/1.8V
Always
ENET1_1588_
EVENT0_OUT
P2-96
O
1588 event output
3.3V/1.8V
Always
NOTE: RGMII ENET1 interface operates at 1.8V voltage level.
NOTE: ENET1 signals are multiplexed with other functions. For additional details please refer
to chapter 5.6 of this document.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 18
Table 14 Secondary RGMII ENET2 Interface Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
ENET2_MDC
P2-68
O
Provides a timing reference to the PHY for
data transfers on the MDIO signal
1.8V
Always
ENET2_MDIO
P2-70
IO
Transfers control information between
the external PHY and the MAC. Data is
synchronous to MDC. This signal is an
input after reset
1.8V
Always
ENET2_RD0
P2-41
I
Ethernet input data from the PHY
1.8V
Always
ENET2_RD1
P2-43
I
Ethernet input data from the PHY
1.8V
Always
ENET2_RD2
P2-45
I
Ethernet input data from the PHY
1.8V
Always
ENET2_RD3
P2-47
I
Ethernet input data from the PHY
1.8V
Always
ENET2_RX_CTL
P2-53
I
Contains RX_EN on the rising edge of
RGMII_RXC, and RX_EN XOR RX_ER on the
falling edge of RGMII_RXC (RGMII mode)
1.8V
Always
ENET2_RXC
P2-55
I
Timing reference for RX_DATA[3:0] and
RX_CTL in RGMII MODE
1.8V
Always
ENET2_TD0
P2-59
O
Ethernet output data to PHY
1.8V
Always
ENET2_TD1
P2-61
O
Ethernet output data to PHY
1.8V
Always
ENET2_TD2
P2-65
O
Ethernet output data to PHY
1.8V
Always
ENET2_TD3
P2-63
O
Ethernet output data to PHY
1.8V
Always
ENET2_TXC
P2-69
O
Timing reference for TX_DATA[3:0] and
TX_CTL in RGMII MODE
1.8V
Always
ENET2_TX_CTL
P2-67
O
Contains TX_EN on the rising edge of
RGMII_TXC, and TX_EN XOR TX_ER on the
falling edge of RGMII_TXC (RGMII mode)
1.8V
Always
ENET2_1588_
EVENT0_IN
P2-99
I
1588 event input
3.3V/1.8V
Always
ENET2_1588_
EVENT0_OUT
P2-97
O
1588 event output
3.3V/1.8V
Always
ENET2_1588_
EVENT1_OUT
P2-94
O
1588 event output
3.3V/1.8V
Always
NOTE: RGMII ENET2 signals operate at 1.8V voltage level.
NOTE: ENET2 signals are multiplexed with other functions. For additional details please refer
to chapter 5.6 of this document.

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 19
4.5 WiFi and Bluetooth Interfaces
UCM-iMX93 features optional 802.11ac WiFi and Bluetooth functions implemented with the
AzureWave AW-CM276NF certified WiFi module (NXP 88W8997 chipset).
AzureWave AW-CM276NF provides the following key features:
IEEE 802.11 ac/a/b/g/n, Wi-Fi compliant
IEEE 802.11i for advanced security
Multiple power saving modes for low power consumption
Quality of Service (QoS) support
Bluetooth 5.3 complaint
The wireless module is interfaced with i.MX93 SoC through SDIO3 interface.
The wireless module provides two on-board MHF4 antenna connectors:
ANT_A –main WiFi antenna
ANT_B –auxiliary WiFi / Bluetooth antenna
NOTE: WiFi and Bluetooth functions are available only with “WB” configuration option.
4.6 USB
UCM-iMX93 provides two dual-role USB2.0 ports. USB port #1 can be configured as host or device,
while the second port is configured permanently for host mode.
Please refer to the i.MX93 Reference manual for additional details.
The tables below summarize the USB interface signals.
Table 15 USB port #1 Signals
Signal Name
Pin #
Type
Description
Availability
USB1_DN
P1-14
IO
USB2.0 negative data
Always
USB1_DP
P1-12
IO
USB2.0 positive data
Always
USB1_VBUS_DET
P1-24
I
USB1 VBUS detect
Always
USB1_ID
P1-22
I
USB1 ID
Always
Table 16 USB port #2 Signals
Signal Name
Pin #
Type
Description
Availability
USB2_DN
P1-5
IO
USB2.0 negative data
Always
USB2_DP
P1-3
IO
USB2.0 positive data
Always
USB2_VBUS_DET
P1-1
I
USB2 VBUS detect
Always
USB2_ID
P1-7
I
USB2 ID
Always

Peripheral Interfaces
Revised May 2023 UCM-iMX93 Reference Guide 20
4.7 MMC / SD /SDIO
UCM-iMX93 features two SD/SDIO ports. These ports are derived from the i.MX93 uSDHC2 and
uSDHC3 controllers. uSDHC IP supports the following main features:
Fully compliant with MMC 5.1 command/response sets and physical layer
Fully compliant with SD 3.0 command/response sets and physical layer
Please refer to the i.MX93 Reference manual for additional details.
The table below summarizes the MMC/SD/SDIO interface signals.
Table 17 SD2 Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SD2_CLK
P2-96
O
Clock for MMC/SD/SDIO card
3.3V/1.8V
Always
SD2_CMD
P2-100
IO
CMD line connect to card
3.3V/1.8V
Always
SD2_DATA0
P2-97
IO
DATA0 line in all modes. Also used to
detect busy state
3.3V/1.8V
Always
SD2_DATA1
P2-99
IO
DATA1 line in 4/8-bit mode. Also used to
detect interrupt in 1/4- bit mode
3.3V/1.8V
Always
SD2_DATA2
P2-94
IO
DATA2 line or Read Wait in 4-bit mode.
Read Wait in 1-bit mode
3.3V/1.8V
Always
SD2_DATA3
P2-98
IO
DATA3 line in 4/8-bit mode or configured
as card detection pin. May be configured as
card detection pin in 1-bit mode.
3.3V/1.8V
Always
SD2_RESET_B
P2-51
O
Card hardware reset signal, active LOW
3.3V/1.8V
Always
SD2_CD_B
P2-92
I
Card detection pin
3.3V/1.8V
Always
NOTE: SD2 pins can be configured to operate at 3.3V or 1.8V voltage levels. Voltage level is
controlled by SoC pin SD2_VSELECT.
NOTE: SD2 signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.
Table 18 SD3 Signals
Signal Name
Pin #
Type
Description
Voltage
Domain
Availability
SD3_CLK
P2-36
O
Clock for MMC/SD/SDIO card
1.8V
Only w/o
'WB' option
SD3_CMD
P2-38
IO
CMD line connect to card
1.8V
Only w/o
'WB' option
SD3_DATA0
P2-42
IO
DATA0 line in all modes. Also used to detect
busy state
1.8V
Only w/o
'WB' option
SD3_DATA1
P2-44
IO
DATA1 line in 4/8-bit mode. Also used to
detect interrupt in 1/4- bit mode
1.8V
Only w/o
'WB' option
SD3_DATA2
P2-48
IO
DATA2 line or Read Wait in 4-bit mode. Read
Wait in 1-bit mode
1.8V
Only w/o
'WB' option
SD3_DATA3
P2-50
IO
DATA3 line in 4/8-bit mode or configured as
card detection pin. May be configured as card
detection pin in 1-bit mode.
1.8V
Only w/o
'WB' option
NOTE: SD3 signals are multiplexed with other functions. For additional details please refer to
chapter 5.6 of this document.