CompuLab SBC-FITPC3 User manual

SBC-FITPC3
Reference Guide

Revised December 2011 SBC-FITPC3 2
© 2011 CompuLab
No warranty of accuracy is given concerning the contents of the information contained in this
publication. To the extent permitted by law no liability (including liability to any person by reason of
negligence) will be accepted by CompuLab, its subsidiaries or employees for any direct or indirect
loss or damage caused by omissions from or inaccuracies in this document.
CompuLab reserves the right to change details in this publication without notice.
Product and company names herein may be the trademarks of their respective owners.
CompuLab
P.O. Box 687 Yokneam Elite
20692 ISRAEL
Tel: [phone]
http://www.compulab.co.il
Fax: [phone]

Table of Contents
Revised December 2011 SBC-FITPC3 3
Table of Contents
1INTRODUCTION .............................................................................................................. 6
1.1 About This Document...................................................................................................... 6
1.2 Related Documents .......................................................................................................... 6
2OVERVIEW........................................................................................................................ 7
2.1 Highlights......................................................................................................................... 7
2.2 Block Diagram ................................................................................................................. 7
2.3 Features ............................................................................................................................ 8
3CORE SYSTEM COMPONENTS.................................................................................... 9
3.1 AMD Embedded G-Series APU ...................................................................................... 9
3.1.1 CPU Core ................................................................................................................ 9
3.1.2 GPU Core................................................................................................................ 9
3.2 System Memory ............................................................................................................. 10
3.2.1 DRAM................................................................................................................... 10
3.3 Display Subsystem......................................................................................................... 10
3.3.1 HDMI.................................................................................................................... 10
3.3.2 DisplayPort ........................................................................................................... 10
3.4 Audio Subsystem ........................................................................................................... 11
3.4.1 Analog Audio........................................................................................................ 12
3.4.2 S/PDIF Output ...................................................................................................... 12
3.4.3 S/PDIF Input ......................................................................................................... 12
3.5 USB3.0 Subsystem......................................................................................................... 13
3.6 Gigabit Ethernet ............................................................................................................. 13
3.7 Super I/O ........................................................................................................................ 13
4SYSTEM LOGIC.............................................................................................................. 14
4.1 Power Subsystem ........................................................................................................... 14
4.1.1 Power Rails ........................................................................................................... 14
4.1.2 RTC Back-Up Battery........................................................................................... 14
4.1.3 Power-on Logic..................................................................................................... 14
4.1.4 Power Button ........................................................................................................ 14
5FACE MODULE INTERFACES.................................................................................... 15
5.1 PCIe................................................................................................................................ 15
5.2 SATA ............................................................................................................................. 16
5.3 USB................................................................................................................................ 16
5.4 SMBus............................................................................................................................ 17
5.5 Digital Audio.................................................................................................................. 17
5.6 LPC ................................................................................................................................ 17
5.7 GPIOs............................................................................................................................. 18

Table of Contents
Revised December 2011 SBC-FITPC3 4
5.8 Power ............................................................................................................................. 18
5.9 Miscellaneous................................................................................................................. 19
6CONNECTORS ................................................................................................................ 20
6.1 HDMI Connector (P13).................................................................................................. 20
6.2 DisplayPort Connector (P19) ......................................................................................... 20
6.3 DC Power Jack (J2)........................................................................................................ 20
6.4 RS232 connector (P2) .................................................................................................... 20
6.5 Audio Jacks (P5, P9)...................................................................................................... 21
6.6 USB 3.0 Host Connectors (P8A, P8B) .......................................................................... 22
6.7 USB 2.0 Host Connectors (P11A, P11B) ...................................................................... 22
6.8 Gigabit Ethernet Connector (P12).................................................................................. 22
6.9 eSATA Connectors (P16A, P16B)................................................................................. 22
6.10 SATA Header (P3) .................................................................................................... 22
6.11 Front Panel Header (P6) ............................................................................................ 22
6.12 Mini-PCIe sockets (P4, P7) ....................................................................................... 22
6.13 SO-DIMM Sockets (P14, P18).................................................................................. 23
6.14 FACE Extension Connectors (PX1, PX2)................................................................. 23
6.15 Power Button (SW2) ................................................................................................. 24
7MECHANICAL DRAWINGS......................................................................................... 25
8CUSTOM FACE MODULE DESIGN............................................................................ 26
9OPERATIONAL CHARACTERISTICS....................................................................... 27
9.1 Absolute Maximum Ratings .......................................................................................... 27
9.2 Recommended Operating Conditions ............................................................................ 27
9.3 DC Electrical Characteristics ......................................................................................... 27

Revised December 2011 SBC-FITPC3 5
Table 1 Document Revision Notes
Date Description
December 2011
·
First release

Introduction
Revised December 2011 SBC-FITPC3 6
1 INTRODUCTION
1.1 About This Document
This document is part of a set of reference documents necessary to operate and program CompuLab
Fit-PC3.
1.2 Related Documents
For additional information not covered in this manual, please refer to the documents listed in Table 2.
Table 2 Related Documents
Document Location
Fit-PC3 Resources http://www.fitpc.com

Overview
Revised December 2011 SBC-FITPC3 7
2 OVERVIEW
2.1 Highlights
Fit-PC3 is a fan-less, extensible PC with powerful multimedia capabilities,
based on AMD embedded G-Series platform.
2.2 Block Diagram
Figure 1 SBC-FITPC3 Block Diagram
UMI
UMI
Memory
Ctrl.
HDMI
Display
Ctrl.
x2
DisplayPort
DDR3
SODIMM x2
(up to 8GB)
eSATA
SATA-III
x4
eSATA
PCIe
x4
USB3
Ctrl.
USB3
USB3
GbE Ctrl.
RTL8111
RJ45
USB2
USB2
USB2
x3
USB2
x6
Mini PCIe
half-size
Audio
codec
ALC888
GPIO
x30
SATA-III
x2
Function and Connectivity Extension Connector
LPC
SPI
HDA
BootROM
SIO
SMSC
PCIe
x4
LED & IR
conn
12V DC
Power
button
RS232
xcvr. Mini serial
64 bit
AMD
Radeon
HD
6xxx
x86 CPU
cores
x2
AMD G-Series
T56N / T40N / T40E / T44R
SATA hdr.
Mini PCIe
full-size
SMBus
x2
RTC
3.5mm jack
3.5mm jack
RTC
battery
TPM
Hudson
A55E
Controller
Hub
PMU

Overview
Revised December 2011 SBC-FITPC3 8
2.3 Features
System
Feature Specifications Notes
CPU
AMD G-T44R
64bit single core
1GHz 9W TDP
AMD G-T40N
64bit dual core
1GHz 9W TDP
AMD G-T40E
64bit single core
1GHz 6.4W TDP
AMD G-T56N
64bit dual core
1.65GHz 18W TDP
RAM Up to 8 GB, DDR3, 1333 MHz, 64-bit (two SO-DIMM sockets) Configurable
Storage
Internal 2.5” hard drive interface
Two eSATA ports, up to 6 Gbit/s
mSATA (multiplexed with full-size mini PCIe socket)
Graphics
Feature Specifications Notes
GPU AMD G-T44R AMD G-T40N AMD G-T40E AMD G-T56N
Radeon HD 6250 Radeon HD 6290 Radeon HD 6250 Radeon HD 6320
HDMI HDMI 1.3a up to 1920x1200 at 60 Hz HDMI 1.4a up to
1920x1200 at 60 Hz
HDMI Stereo 3D - - - +
DisplayPort Up to 2560x1600 at 60Hz
I/O
Feature Specifications Notes
Audio Stereo line-out and stereo line-in
7.1 channel S/PDIF, (electrical through 3.5mm jack)
Network
1000 BaseT Ethernet port, activity LEDs, RJ-45 connector
802.11b/g/n Wi-Fi, 2 antennas, 150 Mbit/s Optional
Mini PCIe
module
Bluetooth V3.0 + EDR
USB
Two USB 3.0 host ports, 5 Gbit/s
Two USB 2.0 host ports, 480 Mbit/s
Four additional USB 2.0 host ports, 480 Mbit/s (front panel) Optional
module
RS232 Partial modem controls, ultra mini serial connector
IR Consumer IR receiver
Expansion
Mini PCIe socket, half-size (used for wireless module)
Mini PCIe socket, full-size, with mSATA support
Proprietary FACE Module (Function And Connectivity Extension Module)
·4x PCIe
·6x USB2
·2x SATA
·4x SMBus
·30x GPIOs
·LPC
Electrical and Mechanical
Feature Specifications Notes
Power Supply Unregulated 10 to 16 volt input
Power
consumption
AMD G-T44R AMD G-T40N AMD G-T40EAMD G-T56N Depends on
system load
TBD 8W – 17W 7W – 15W 9W – 24W
Dimensions 16cm x 16cm x 2.5cm 19cm x 16cm x 4cm

CORE System Components
Revised December 2011 SBC-FITPC3 9
3 CORE SYSTEM COMPONENTS
3.1 AMD Embedded G-Series APU
3.1.1 CPU Core
The AMD embedded G-Series APU x86 core supports the following key features:
·Single or dual x86 Processor
·AMD64 64-bit ISA
·Advanced Branch Prediction
·Out-of-Order Instruction Execution
·64-bit floating-point unit
·SSE1,2,3, SSSE3 ISA, SSE4A, MMX
·AMD Virtualization technology
3.1.2 GPU Core
The AMD embedded G-Series APU integrated GPU core supports the following key features:
·Dedicated graphics memory controller
·High efficiency ring bus memory controller
·Direct connection to memory
·2D Acceleration
·Highly-optimized 128-bit engine, capable of processing multiple pixels per clock
·3D Acceleration
·Full DirectX 11 support, including full speed 32-bit floating point per component
operations
·Shader Model 5
·OpenCL 1.1 support
·OpenGL 4.0 support
·Motion Video Acceleration
·Dedicated hardware (UVD 3) for H.264, VC-1 and MPEG2 decode
·HD HQV and SD HQV support: noise removal, detail enhancement, color enhancement,
cadence detection, sharpness, and advanced de-interlacing
·Super up-conversion for SD to HD resolutions

CORE System Components
Revised December 2011 SBC-FITPC3 10
3.2 System Memory
3.2.1 DRAM
The Fit-PC3 features two user accessible DDR3 SO-DIMM sockets. The DRAM interface is 64-bits
wide and runs at a 666 MHz clock. Fit-PC3 supports up to 8GB of memory.
3.3 Display Subsystem
3.3.1 HDMI
The Fit-PC3 HDMI output is implemented with the APU HDMI interface. HDMI signals are routed
to the display output connector P13. The HDMI output supports resolutions of up to 1920 x 1200 at
60Hz.
NOTE: HDMI 1.4a is supported only in the Fit-PC3 model featuring the G-T56N APU. Other
Fit-PC3 models support HDMI 1.3a.
3.3.2 DisplayPort
The Fit-PC3 DisplayPort output is implemented with the APU DisplayPort interface. DisplayPort
signals are routed to the display output connector P19. The DisplayPort output supports resolutions of
up to 2560 x 1600 at 60Hz.

CORE System Components
Revised December 2011 SBC-FITPC3 11
3.4 Audio Subsystem
The Fit-PC3 audio subsystem is implemented with the Realtek ALC888S-VC2 audio codec. The
ALC888S-VC2 is a high performance 7.1+2 channel high definition audio codec with an independent
S/PDIF output. The codec features ten DAC channels that simultaneously support 7.1 sound playback
and an independent stereo output.
The audio codec is connected to the A55E Controller Hub HDA port.
The ALC888S-VC2 supports the following main features:
·Meets premium audio requirements for Microsoft WLP 3.10
·Meets stricter performance requirements for future WLP effective from 01 June 2008
·High-performance DACs with 97dB SNR (A-Weighting), ADCs with 90dB SNR (A-
Weighting)
·Ten DAC channels support 16/20/24-bit PCM format for 7.1 sound playback, plus 2 channels
of independent stereo sound output (multiple streaming) through the front panel output
·Two stereo ADCs support 16/20/24-bit PCM format recording simultaneously
·All DACs supports 16/20/24-bit, 44.1k/48k/96k/192kHz sample rate
·All ADCs supports 16/20/24-btt, 44.1k/48k/96k/192kHz sample rate
·SPDIF-OUT converter supports 16/20/24-bit, 44.1k/48k/88.2k/96k/192kHz sample rate
·SPDIF-IN converter supports 44.1k/48k/96k/192k Hz sample rate
·Wide range (–80dB ~ +42dB) volume control with 1.5dB resolution of analog to analog
mixer gain
·Software selectable boost gain (+10/+20/+30dB) for analog microphone input
·Built-in headphone amplifiers for each re-tasking jack
·Integrates high-pass filter to cancel DC offset generated from digital microphone

CORE System Components
Revised December 2011 SBC-FITPC3 12
3.4.1 Analog Audio
The Fit-PC3 analog audio sub-system features a stereo line output and a stereo line input
implemented with the ALC888S-VC2 codec.
Analog line output is routed to the audio jack P5. Analog line input is routed to the audio jack P4.
Table 3 Audio Characteristics
Parameter Min Typical Max Unit
Full-Scale Input Voltage
All Inputs (gain=0dB) - 1.6 - Vrms
ADC - 1.1 - Vrms
Full-Scale Output Voltage
DAC - 1.4 - Vrms
Headphone Amplifier Output@32 - 1.6 - Vrms
S/N (A Weighted)
ADC - 90 - dB FSA
DAC - 96 - dB FSA
Headphone Amplifier Output@32 - 95 - dB FSA
THD+N
ADC - -84 - dB FS
DAC - -90 - dB FS
Headphone Amplifier Output@32 - -80 - dB FS
Frequency Response
ADC 10 - 0.45*Fs Hz
DAC 0 - 0.45*Fs Hz
Power Supply Rejection - -50 - dB
Total Out-of-Band Noise (28.8kHz~100kHz) - -60 - dB
Amplifier Gain Step - 1.5 - dB
Crosstalk Between Input Channels - -80 - dB
Input Impedance (gain=0dB) - 47 - KΩ
Output Impedance
Amplified Output - 1 - Ω
Non-amplified Output - 100 - Ω
3.4.2 S/PDIF Output
The S/PDIF output is implemented with the ALC888S-VC2 codec. SPDIF-OUT converter supports
16/20/24-bit, 44.1k/48k/88.2k/96k/192kHz sample rates. The S/PDIF output signal is routed to audio
jack P5.
3.4.3 S/PDIF Input
The S/PDIF input is implemented with the ALC888S-VC2 codec. SPDIF-IN converter supports
44.1k/48k/96k/192kHz sample rates. The S/PDIF input signal is routed to audio jack P4.

CORE System Components
Revised December 2011 SBC-FITPC3 13
3.5 USB3.0 Subsystem
The Fit-PC3 features two external USB3.0 ports that are implemented with the Texas Instruments
TUSB7320 host controller. The down-stream ports support SuperSpeed, High-speed and Full-
speed/Low-speed connections.
The TUSB7320 host controller is interfaced with the PCIe interface of the A55E Controller Hub. The
two USB down-stream ports are routed to the dual-stacked USB connector P8.
For additional details, please refer to the TUSB7320 datasheet, available from http://www.ti.com/.
3.6 Gigabit Ethernet
The Fit-PC3 Gigabit Ethernet interface is implemented with the RTL8111D Realtek Gigabit Ethernet
controller. The controller is connected to the PCIe interface of the A55E Controller Hub. The
interface supports the following main features:
·Full compliance with IEEE 802.3 standard
·Crossover Detection and Auto-Correction
·Wake-on-LAN and remote wake-up support
·Auto-negotiation
·Activity and speed indicator LED controls
Gigabit Ethernet signals are routed to the RJ-45 connector P12.
3.7 Super I/O
The Fit-PC3 utilizes a SMSC SIO1007 Super I/O controller to implement RS232 and CIR interfaces.
The SIO1007 Super I/O controller is interfaced with the A55E controller hub LPC port.
CIR signals are routed to the IR connector U7.
UART signals are routed through the RS232 transceiver to the RS232 connector P2.

System Logic
Revised December 2011 SBC-FITPC3 14
4 SYSTEM LOGIC
4.1 Power Subsystem
4.1.1 Power Rails
The Fit-PC3 is powered with a single 12V power supply.
Table 4 Power signals
Signal Name Type Description
VIN_12V P Main power supply. Typical voltage – 12V.
GND P Common ground.
4.1.2 RTC Back-Up Battery
The Fit-PC3 features an on-board 18mAh rechargeable coin cell lithium battery, which maintains the
Fit-PC3 RTC when the main power supply is not present. The battery is being re-charged whenever
Fit-PC3 is connected to the main power supply. The back-up battery will sustain the RTC for up to 6
months with no charging.
4.1.3 Power-on Logic
The Fit-PC3 is designed to support standard PC power-on logic. The Fit-PC3 BIOS can be configured
for the following behavior for when main power is applied:
·Stay off
·Turn on automatically
·Preserve the last state before power disconnect
4.1.4 Power Button
The Fit-PC3 power button SW2 controls the system power state. The button serves as a standard
ON/OFF button in a typical PC system. The button behavior is programmable using standard tools
available in MS Windows and Linux.

FACE MODULE interfaces
Revised December 2011 SBC-FITPC3 15
5 FACE MODULE INTERFACES
5.1 PCIe
Table 5 PCIe Interface Signals
Signal Name Pin # Type Description Notes
PCIe-0
PCIE_P0_TX_P PX1-A44 I/O PCIe port 0 transmit positive
PCIE_P0_TX_N PX1-A45 I/O PCIe port 0 transmit negative
PCIE_P0_RX_P PX1-B44 I/O PCIe port 0 receive positive
PCIE_P0_RX_N PX1-B45 I/O PCIe port 0 receive negative
PCIe-1
PCIE_P1_TX_P PX1-A41 I/O PCIe port 1 transmit positive
PCIE_P1_TX_N PX1-A42 I/O PCIe port 1 transmit negative
PCIE_P1_RX_P PX1-B41 I/O PCIe port 1 receive positive
PCIE_P1_RX_N PX1-B42 I/O PCIe port 1 receive negative
PCIe-2
PCIE_P2_TX_P PX1-A38 I/O PCIe port 2 transmit positive
PCIE_P2_TX_N PX1-A39 I/O PCIe port 2 transmit negative
PCIE_P2_RX_P PX1-B38 I/O PCIe port 2 receive positive
PCIE_P2_RX_N PX1-B39 I/O PCIe port 2 receive negative
PCIe-3
PCIE_P3_TX_P PX1-A35 I/O PCIe port 3 transmit positive
PCIE_P3_TX N PX1-A36 I/O PCIe port 3 transmit negative
PCIE_P3_RX_P PX1-B35 I/O PCIe port 3 receive positive
PCIE_P3_RX_N PX1-B36 I/O PCIe port 3 receive negative
PCIe generic
PCIE_CLK1_P PX1-B32 O PCIe clock 1 positive
PCIE_CLK1_N PX1-B33 O PCIe clock 1 negative
PCIE_CLK2_P PX2-B26 O PCIe clock 2 positive
PCIE_CLK2_N PX2-B27 O PCIe clock 2 negative
PCIE_RESET# PX1-B31 O PCIe reset. Asserted during transition to
S3/S4/S5.
PCIE_WKUP# PX1-A37 I PCIe wake-up
PCIE_CLKREQ# PX2-A41 I PCIe clock request

FACE MODULE interfaces
Revised December 2011 SBC-FITPC3 16
5.2 SATA
Table 6 SATA Interface Signals
Signal Name Pin # Type Description Notes
SATA-1
SATA_P1_TX_P PX1-B8 O SATA channel 1 transmit positive
SATA_P1_TX_N PX1-B9 O SATA channel 1 transmit negative
SATA_P1_RX_P PX1-B11 I SATA channel 1 receive positive
SATA_P1_RX_N PX1-B12 I SATA channel 1 receive negative
SATA-2
SATA_P2_TX_P PX1-A2 O SATA channel 2 transmit positive
SATA_P2_TX_N PX1-A3 O SATA channel 2 transmit negative
SATA_P2_RX_P PX1-A5 I SATA channel 2 receive positive
SATA_P2_RX_N PX1-A6 I SATA channel 2 receive negative
SATA-3
SATA_P3_TX_P PX1-A8 O SATA channel 3 transmit positive
SATA_P3_TX_N PX1-A9 O SATA channel 3 transmit negative
SATA_P3_RX_P PX1-A11 I SATA channel 3 receive positive
SATA_P3_RX_N PX1-A12 I SATA channel 3 receive negative
SATA generic
SATA_ACT# PX1-B4 OD SATA channel active
5.3 USB
Table 7 PCIe Interface Signals
Signal Name Pin # Type Description Notes
USB-4
USB_P4_P P1-A24 I/O USB port 4 positive I/O
USB_P4_N P1-A25 I/O USB port 4 negative I/O
USB-5
USB_P5_P PX2-A48 I/O USB port 5 positive I/O
USB_P5_N PX2-A49 I/O USB port 5 negative I/O
USB-7
USB_P7_P PX1-B17 I/O USB port 7 positive I/O
USB_P7_N PX1-B18 I/O USB port 7 negative I/O
USB-8
USB_P8_P PX1-B14 I/O USB port 8 positive I/O
USB_P8_N PX1-B15 I/O USB port 8 negative I/O
USB-12
USB_P12_P PX1-A27 I/O USB port 12 positive I/O
USB_P12_N PX1-A28 I/O USB port 12 negative I/O
USB-13
USB_P13_P PX2-A45 I/O USB port 13 positive I/O
USB_P13_N PX2-A46 I/O USB port 13 negative I/O
USB Overcurrent
USB_P7_P8_OVC PX1-B16 I/O USB over current for ports 7 and 8
USB_P4_P12_OVC PX1-A26 I/O USB over current for ports 4 and 12
USB_P5_P13_OVC PX1-A47 I/O USB over current for ports 5 and 13

FACE MODULE interfaces
Revised December 2011 SBC-FITPC3 17
5.4 SMBus
Table 8 SMBus Interface Signals
Signal Name Pin # Type Description Notes
SMBus-0
SMBUS_P0_CLK PX1-A14 I/OD SMBus channel 0 clock
SMBUS_P0_DAT PX1-A15 I/OD SMBus channel 0 data
SMBus-2
SMBUS_P2_CLK PX2-A39 I/OD SMBus channel 2 clock
SMBUS_P2_DAT PX2-A40 I/OD SMBus channel 2 data
SMBus thermal
SMBUS_THRM_CLK PX2-B39 I/O APU temperature sensor SMBus clock
SMBUS_THRM_DAT PX2-B40 I/O APU temperature sensor SMBus data
SMBus generic
SMBUS_ALERT# PX1-A10 I/O SMBus alert - this signal can be used to wake
the system or generate an SMI
5.5 Digital Audio
Table 9 Digital Audio Interface Signals
Signal Name Pin # Type Description Notes
HDA_ RST# PX1-A16 O HD audio interface reset
HDA_SYNC PX1-A17 O HD audio sync signal to codec
HDA_CLK PX1-A18 O HD audio interface bit clock
HDA_SOUT PX1-A19 O HD audio serial data output to codec
HDA_SIN1 PX1-A20 I/O HD audio serial data input from a second
codec
HDA_SIN2 PX1-A21 I/O HD audio serial data input from a third codec
5.6 LPC
Table 10 LPC Interface Signals
Signal Name Pin # Type Description Notes
LPC_LAD0 PX1-A30 I/O Multiplexed command / address / data bit 0
LPC_LAD1 PX1-A31 I/O Multiplexed command / address / data bit 1
LPC_LAD2 PX1-A32 I/O Multiplexed command / address / data bit 2
LPC_LAD3 PX1-A33 I/O Multiplexed command / address / data bit 3
LPC_CLK PX1-B23 O 33MHz clock for LPC device
LPC_LFRAME# PX1-B24 O LPC bus frame
LPC_SER_IRQ PX1-B22 I/O Serial IRQ

FACE MODULE interfaces
Revised December 2011 SBC-FITPC3 18
5.7 GPIOs
Table 11 GPIO Signals
Signal Name Pin # Type Description Notes
FCH_GPIO0 PX2-B4
I/O S0-domain General Purpose I/O
GPIO state is
not preserved
in sleep mode
FCH_GPIO1 PX2-B10
FCH_GPIO3 PX2-B16
FCH_GPIO4 PX2-B12
FCH_GPIO5 PX2-B14
FCH_GPIO6 PX2-B15
FCH_GPIO7 PX2-B17
FCH_GPIO8 PX2-B18
FCH_GPIO9 PX2-B20
FCH_GPIO10 PX2-B21
FCH_GPIO11 PX2-B23
FCH_GPIO12 PX2-B24
FCH_GPIO54 PX1-A46
FCH_GPIO57 PX2-A42
FCH_GPIO58 PX2-A43
FCH_GPIO182 PX1-A22
I/O S5-domain General Purpose I/O
GPIO state is
preserved in
sleep mode
FCH_GPIO201 PX2-A20
FCH_GPIO202 PX2-A21
FCH_GPIO204 PX2-A23
FCH_GPIO205 PX2-A24
FCH_GPIO129_OD PX2-A17
I/OD General Purpose I/OD
GPIO state is
not preserved
in sleep mode
FCH_GPIO130_OD PX2-A18
FCH_GPIO144_OD PX2-A14
FCH_GPIO145_OD PX2-A4
FCH_GPIO146_OD PX2-A10
FCH_GPIO147_OD PX2-A15
FCH_GPIO149_OD PX2-A16
FCH_GPIO150_OD PX2-A22
FCH_PWM0_GPIO197 PX2-B44
I/O S5-domain General Purpose I/O
GPIO state is
preserved in
sleep mode
FCH_PWM1_GPIO198 PX2-B47
NOTE: GPIO numbering corresponds with GPIO numbering in the A55E controller hub
documentation.
5.8 Power
Table 12 Power Signals
Signal Name Pin # Type Description Notes
GND
PX1-A1, PX1-B1, PX1-A7,
PX1-A23, PX1-B25, PX1-A29,
PX1-A34, PX1-A40, PX1-B40,
PX2-A1, PX2-B1, PX2-A7,
PX2-B7, PX2-A13, PX2-B13,
PX2-A25, PX2-B25, PX2-A32,
PX2-B32, PX2-A38, PX2-B41,
PX2-A44, PX2-A50
P Main GND rail
5V_S5 PX1-B7, PX1-A13, PX1-B13,
PX1-B19, PX2-A19, PX2-B19 P S5-domain 5V power rail
VCC_12V
PX1-A47, PX1-A48, PX1-A49,
PX1-A50, PX1-B47, PX1-B48,
PX1-B49, PX1-B50, PX2-B48,
PX2-B49, PX2-B50
P Main 12V power rail

FACE MODULE interfaces
Revised December 2011 SBC-FITPC3 19
5.9 Miscellaneous
Table 13 Miscellaneous Signals
Signal Name Pin # Type Description Notes
FACE_PRSNT# PX1-B34 I
FACE module presence
detection. Must be connected
to GND.
PWR_BTN# PX1-A43 I
Power button - causes an SMI
or SCI to indicate a system
request to enter a sleep state. If
the system is already in a sleep
state, this signal will cause a
wake event. If PWR_BTN# is
asserted for more than 4
seconds, it will cause an
unconditional transition (power
button override) to the S5 state
with only the PWR_BTN#
available as a wake event.
Override will occur even if the
system is in the S1 state. This
signal has an internal pull-up
resistor.
SLEEP_S3# PX1-B43 O
S3 sleep power plane control.
Assertion of SLP_S3# shuts
off power to non-critical
components when system
transitions to S3, S4, or S5
states. De-assertion of
SLP_S3# turns on power to
non-critical components when
system transitions from S3, S4,
or S5 back to S0.
RESERVED
PX1-A4, PX1-B2, PX1-B3,
PX1-B5, PX1-B6, PX1-B10,
PX1-B20, PX1-B20, PX1-B26,
PX1-B27, PX1-B28, PX1-B29,
PX1-B30, PX1-B37, PX1-B46,
PX2-A2, PX2-A3, PX2-A5,
PX2-A6, PX2-B2, PX2-B3,
PX2-B5, PX2-B6, PX2-B28,
PX2-B29, PX2-B30, PX2-B31,
PX2-A35, PX2-B33, PX2-B34,
PX2-B35, PX2-B36, PX2-B37,
PX2-B38, PX2-B42, PX2-B43,
PX2-B45, PX2-B46
- Reserved for future use.
Should be left unconnected.
NC
PX2-A8, PX2-A9, PX2-A11,
PX2-A12, PX2-B8, PX2-B9,
PX2-B11, PX2-A26, PX2-A27,
PX2-A28, PX2-A29, PX2-A30,
PX2-A31, PX2-A33, PX2-A34,
PX2-A36, PX2-A37
- Should be left unconnected.

Connectors
Revised December 2011 SBC-FITPC3 20
6 CONNECTORS
6.1 HDMI Connector (P13)
The HDMI display output is provided through the standard HDMI socket (P13).
For additional details, please refer to section 3.3.1 of this document.
6.2 DisplayPort Connector (P19)
The DisplayPort display output is provided through the standard DisplayPort connector (P19).
For additional details, please refer to section 3.3.2 of this document.
6.3 DC Power Jack (J2)
DC power input connector.
Table 14 J2 connector pin-out
Pin Signal Name
1 VIN_12V
2 GND
Table 15 J2 connector data
Manufacturer Mfg. P/N
Contact Technology DC-081HS
The connector is compatible with the Fit-PC3 power supply unit supplied by CompuLab.
6.4 RS232 connector (P2)
The Fit-PC3 RS232 port is routed to the on-board RS232 ultra-mini connector (P2). All signals are at
RS232 levels.
Table 16 P2 connector pin-out
Pin Signal Name Pin Signal Name
1 RS232_TXD 5 RS232_DTR
2 RS232_RTS 6 RS232_DSR
3 RS232_RXD 7 RS232_RI
4 RS232_CTS 8 GND
Table 17 P2 connector data
Manufacturer Mfg. P/N Mating connector
Wieson G3169-500001 Wieson, P/N: 4306-5000
The connector is compatible with the serial cable adapter (CompuLab P/N 199D10230) supplied by
CompuLab.