Cromemco 32K Bytesaver User manual

Cromemeo
31K
By te saver
Five Dollars

.
Cromemco
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CopyrIght c,1978 by Cromemco Inc A1ll1ghlS reserved
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cromemco
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Tomorrow's Computers Today
::l!OBER!;AAOO "'.'E UOUN1'A N V'E;W c.\ \joIljolJ
Part No. 023·0002
April 1979

Table of COntents
Section 1
I ntraduction .. _. _ ... _ ..... _ .........•......•......•.. 1
Technical Specifications ...........•................ ,
Section 2
Operating Instructions .. _ ... _ ..... _ .............••.... _.2
2.1 Switch Options-An Overview
..........•...••...... 2
PROGRAM POWER Toggle Switch
ADDR/CONTROL Switches
PROGRAM ENABLE Switches
BAN K SE LEer Switches
SHADOW ROM Switches
2.2 Addressing The 32K BYTESAVER .. _. _ •.••••...... 7
2.3 Board Select/Chip Select _ _ 8
2.4 Shadowing ROM Socket Pairs _ 10
2.5 Memory Banks 12
2.6 Select
BANK 0 On RESET Or POWER·ONCLEAR 16
2.7 Direct Memory Access. _16
Section 3
PROM Programming Instructions 19
3.1 Programming From RODS Or
2·80 Monitor 19
3.2 Programming From 3K Control BASIC 20
3.3 Programming From l-80 Assembly Code 22
Section 4
Theory Of Operation
...........••.•...•••......•...... 24
4.1 Power Supplies ................•.............. 24
4.2 Addressing. . ................•.............. 24
4.3 Memory Read Cycles ....................•...... 25
4.4 Memory Write Cycles
.......•.................. 25
4.5
DMA Cycles .......•.................... 25
Section 5
Assembly Instructions
............•••....•••........... 27
5.1 Assembly Steps .........................•..... 27
5.2 Power
line Testing ........•................... 28
Parts List. .. _. _. _ _ .......•.....••.•.......... 30
Parts Location Diagram .. _. _ .......•.....••......•..... 32
Switch Options-Ouick Reference ....•......••.....•..... 33
Warranty _. _ _ .........•......•........... 34
Schematic Diagram .....••......•... _. _. _ ......•... _ .. 35

Table of COntents
LIST OF ILLUSTRATIONS
Figure 1 - Switch Locations. .............•....•......... 2
Figure 2 - ADDR!CONTROL Switches .........•.......... 3
Figure 3 - Example 1 Switch Settings _ _ _ 5
Figure 4 - Example 2
Switch Settings _. _. _. _ _ .6
Figure 5 • 32K BYTESAVER Addressing .. __ . __ 7
Figure 6 .
Two 32K BYTESAVEAS Spanning The 64K
Address Space _ 9
Figure 7 - Example 4
Switch Settings And Memory Map 11
Figure 8 . The Memory Map With Multiple Memory Banks 12
Figure 9 - Example 5 Switch Settings 13
Figure
10 -Example 5Memory Map 14
Figure 1'- DMA OVERRIDE Example Configuration 17
Figure
12 - Control BASIC Memory Map _ 21
Figure 13 -IC Pin Position 28

32K Bytesaver
Introduction
This manual provides assembly instructions,
operating instructions and theory of operation for
the Cromemco 32K BYTESAVER memory board.
The 32K BYTESAVER is an 5-100 bus com-
patible. 32K-byte capacity. 2716-type EPROM
memory board and programmer. The 32K BYTE·
SAVER features:
•Independent operation as a 32K-byte ROM
memory board.
• Independent operation as a 2716 PROM pro-
grammer.
•BANK SE LEeT allowing memory expansion
beyond 64K-bytes_
•ROM SHADOWING allowing external mem-
ory to overlap portions of the 32K BYTE-
SAVER's address space.
• Powerful DMA configuration options with
DMA OVERRIDE.
•Fully buffered address lines.
• Digital count derived PROGRAM PULSES
(no erratic one-shots).
• A separate memory protect switch for each
ROM socket.
• All options SWitch selectable lno soldered
jumper wires).
This manual consists of four basic sections:
Operating Instructions. PROM Programming Instruc-
tions, Theory of Operation and Assembly Instruc-
tions. If you purchased a 32K BYTESAVEA kit, the
Assembly Instructions provide step-by-step con-
struction and initial test procedures. The section
"Switch Options - An Overview" of the Operating
Instructions provides a 32K BYTESAVER opera·
tional overview for those who want to put the board
quickly to use.
Technical Specifications-32K BYTESAVER PROM Card
MEMORY CAPACITY:
MEMORY TYPE:
MEMORY ACCESS TIME:
WAIT STATES@2 MHZ:
WAIT STATES@4 MHZ:
BUS COMPATIBILITY:
POWER REQUIREMENTS:
OPERATING ENVIRONMENT:
32K BYTES
INTEL 2716, TI 2516 DR EQUIVALENT'
450 NANOSECONDS
NONE REQUIRED
ONE PER MACHINE CYCLE
S·100
+B VOLTS AT 2.1 AMPS (MAX.)
0-55 DEGREES CELSIUS
I
·NOTE: Texas Instrument's 2716 PROM is not
equivalenr to the Intel 2716 PROM. and
thus
it may not be used with the 32K
BYTESAVER. The TI 2516 IS equivalenr
to the Intel
2716, so it may be used with
the 32K BYTESAVER.
1

32K Bytesaver
operating Instructions
=--
- -~-
Operating the 32K BYTESAVER board involves
inserting from one to sixteen 2716 PROM devices in
sockets ROM 0 - ROM 15 (any sockets may be
used or left unused), setting six switch groups to
configure the board, plugging the board into acon-
venient 5·100 bus slot, and then applying system
power. To program aPROM, you will additionally
need to run software described in the Section 3,
PROM PROGRAMMING INSTRUCTIONS.
2.1 Switch Options-AnOverview
The 32K BYTESAVER is configured by setting
six switch groups located along the top edge of the
board (see Figure 1). To provide an operational
overview and for later quick reference, the function
of each switch group is briefly explained in this
section.
Figure I-Switch Locations
PROGRAM
POWER
r--l., ADDR;!DNTRDL
PROGRAM
ENABLE
""
~ •• t.....:
..
. 'r
'H
..
.. ". "
..
... ~
~.....
,- ....
[) Croon_on",o
jZl<
BI'TESA/.'ER'~
I
BANK iLEeT SHADO\ ROMS
2

32K Bytesaver
PROGRAM POWER Toggle Switch
The PROGRAM POWER switch turns the +26
volt de to de power supply and the nearby red LED
indicator ON and OFF. Position this switch ON be-
fore PROM programmmg: position it OFF when
done to prevent inadvertent re-programming.
ADDR/CONTROL Switches
The ADDA/CONTROL switches control several
different functions (see Figure 2).
Switches 1, 2 and 3are not used.
The BANK ENABLE/DISABLE switch enables
multiple 64K memory banks (bank 0-bank 7) when
ON, and disables multiple banks when OFF(normal
direct 64K addressing).
The WAIT STATE switch is used to match the.
CPU cycle time to the 2716 PROM 45005 (max)
memory access time. Positioning the WAIT STATE
switch ON introduces one wait state per machine
cycle; the OFF position introduces no wait states.
When used
in aCromemco system with aZPU run-
ning at 4
MHz, position the switch ON. The switch
may be left OFF when operating at 2 MHz.
The A15 switch memory maps the 32K BYTE·
SAVER board in the lower 32K half of the memory
address space lOOOOH -7FFFHI when in the OFF
pOSItion IA15=0>, and memory maps the board in
the upper 32K half of memory address space
(8000H-FFFFHI when in the ON position
(A 15'11.
The DMA ENABLE/DISABLE switch enables
DMA OVERRIDE when ON and disables OMA
OVERRIDE when OFF. For normal direct 64K
DMA addressing, position the switch OFF. When
performing OMA with memory banks enabled. turn
Figure 2-ADDR/CONTROL Switches
~~--- MEMORY BAN~S ENABLED
I
~~==ONE WAIT STATE
AIS=I (UPPER 32~)
DMA OVERRIDE ENABLED
r-DMA OUT
~2E8-\HPJ.HI-I' -lH
L-DMAIN
L
-'=== DMA OVERRIDE DISABLED
AIS=O (LOWER
32KI
l
_~~==== NO WAIT STATES
MEMORY BANKS DISABLED
NOT USED •
3

,
32K Bytesaver
the switch ON. The DMA IN/OUT switch is active
only when DMA OVERRIDE is enabled. With DMA
OVERRIDE enabled, the 32K BYTESAVER will
respond directly to a DMA in the board's 16-bit
address range by board enabling if DMA is IN, and
by board disabling if DMA is OUT, regardless of
current active memory bank status at the time. This
feature effectively permits the user to define one
board out of several stacked in different memory
banks as the DMA board (the one with DMA INI.
and the boards in other memory banks as non-DMA
boards (the ones with DMA OUT).
PROGRAM ENABLE Switches
The sixteen PROGRAM ENABLE switches indi-
vidually enable and disable programming sockets
ROMO thru ROM15. An ON switch enables pro-
gramming; an OFF switch inhibits programming.
These switches may be alternately viewed as MEM-
ORY PROTECT switches, preventing any memory
write operations when in the OFF position.
To enable and disable socket programming,
associate the board socket numbers
IROM0-
ROM15) with the numerals printed above the two
switch DIPs
on the p.c. board (15 to the far left,
a to the far right).
4
BANK SELECT Switches
The eight BANK SE LECT switches map the 32K
BYTESAVER IOta any combination of eight possi-
ble 64K byte memory banks (bank 0 - bank 71. Set
ting aBANK SELECT switch ON logically places
the board
in the correspondingly numbered memory
bank; an OFF switch logically removes the board
from abank. Again, associate
the bank number with
the numerals printed above the BANK SELECT
switches
on the p.c. board, not the numerals on the
DIP proper_
SHADOW ROM Switches
Each SHADOW ROM switch controls two ROM
sockets (the rightmost controls ROMe and ROM 1,
the leftmost controls ROM 14 and ROM 151 by plac-
ing
both sockets in the memory map when the
switch is OFF, and by removing both sockets
("floating"
the board when either socket is address-
ed) from the memory map when ON. Placing a
SHADOW
ROM SWitch ON effectively creates a
4K-byte
"hole" In the 32K BYTESAVER address
space,
into which another memory module may be
mapped.

32K Bytesaver
:-=0::: ==-==-
==-=-=-=-
----
Example 1
Suppose you have a 4MHz ZPU and you want
your 32K BYTESA VER (0 reside in the upper 32t;
of memory. As a standard practice, yOll decide co
program 2716 PROMs in socket ROM€) only;
there are no other boards in the upper 32K of memo
ary, so multiple memory banks are nor required.
Then,
for memory read operatioll. the switch set·
lings would be as shown in Figure 3.
To
program a PROM in socket ROMe, all switch
settings remain the same except the PROGRAM
POWER switch which /IIl/st be turned ON. 0
Figure 3-Example 1 Switch Settings
PROGRAM
POjER
,---BANI< DISABLE
r
~==A1S~1
DON'r CARE SINCE OMA
OVERRIDE DISABLED
iDISABLE ROM a-ROM 15
--l- PROGRAMMING
'fi' "l'L--r't" l'~:"":;;~;=";'~:;:~1
U . t~,';";1
L ALL SOCKET PAIRS
IN MEMORY MAP
l
~~== OMA OVERRIDE DISABLED
ONE WAIT STATE
NOT uSED
5
ENABLE ROM 0-
PROGRAMMING
DISABLE
ROMf~ROM 7l
PROGRAMMING
DON'T CARE SINCEI
BANKS DISABLED
:UN BYTESAJlER ,.

32K Bytesaver
The following example uses all of the 32K
BYTESAVER special features.
Example2
Suppose you have a 2MHz system and you walJl
the board to reside in the lower 32K of memory.
The system has 4K of RAM at overlapping addresses
OOOOH-OFFFH, so a 4K "hole" must be created in
the 32K BYTESAVER memory map. You incend co
----
-~--
-----
-- ---
=~ ;:;:;:.
program four PROMs at a lime in sockets ROM12-
ROM15 (programming 8K blocks of source code to
PROM) amI a16K RAM card also resides in the
lower 32K of memory solely for DMA transfers
(assume this card is assigned to memory bank 1 J.
You decide to assign the 32K BYTESAVER 10
memory bank 0so it will be enabled on iJ system
Power·Qn-Clear or RESET - see Section 2.6 for
details. The appropriate 32K BYTESAVER switch
settings for memory read operations are then shown
in Figure 4 0
Figure 4-Example 2 Switch Settings
PROGRAM
POWER
r::====BANKS ENABLED
I Ar5=O
,---DMAOUT
[[=
ENABlE ROM 12·RDM 15
PROGRAMMING
,DISABLE ROM a-ROM II
.-L PROGRAMMING
- SHADOW SOCKETS
ROM O-ROM 3
'--SOCKETS ROM 4-ROM 15
IN MEMORY MAP
L---OMA OVERRIDE ENABLED
L
~====NO WAIT STATES
NOT USED
6
DISABLE l
ROM O-ROM 7
PROGRAMMING
lIUOUUO~O
BOARD NOT IN
BANK I- BANK 1
BOARD IN
BANK

All 32K BYTESAVER special features and oper-
ational modes touched upon above are discussed
in
greater detail in the sections which immediately
follow.
2.2 Addressing The 32K BYTESAVER
Addressing a byte on the 32K BYTESAVER in-
volves four levels of selection: choosing amemory
bank, amemory board, an
IC chip, and finally
choosing the byte-on-chip_
Memory banks are addressed by the CPU out-
puning acontrol word to an integral OUTPUT
PO RT 40H contained on each 32K BYTESAV ER
board. Board, chip and byte-on·chip are all decoded t
from the sixteen bit address seni: out by the CPU on
the S-l00 bus.
Since the board capacity
is 32K bytes. board
select is generated by the high order address line
A15. There are sixteen
ROM sockets. so the next
four high order address lines A
11- A14 are used to
hardware generate chip enable (selecting ROM0-
ROM 151. and the remaining eleven address lines AO
-A 10 are used to address one-of-2,048 bytes on a
2716 PROM (see Figure 5).
Figure 5-32K BYTESAVER Addressing
Execute OUT (40H), A } _
A15}-----
~~~j------
A12
A 11
Select bank 0- 7
Select one-of-two boards
Select one-of-sixteen chips
A10
A9
AS
A7
A6
A5
A4
A3
A2
Al
A0
}-------- Select one-of-2048 bytes
7

32K Bytesaver
2.3 Board SELECT/CHIP Select
5-100 bus address line A15 is hardware com-
pared to switch A15 in the ADDR/CONTROL
switch group. Switch A15 ON corresponds to ad-
dress line A15""1 (address 800eH-FFFFH); switch
A15 OFF corresponds to address line A15=0 (ad-
dresses 0000H-7FFFH). These two switch settings
place the 32K BYTESAVEA in the upper or lower
32K half of the 64K address space, respectively_
Each ROM socket IROM0-ROM151 spans a2K-
liyte swath of memory. Address lines A 11 ~A 14 feed
two one-of-eight decoders (ICG and le7 in the 32K
BYTESAVER Schematic) to generate select signals
to! each ROM socket. The entire 64K address space
may then be spanned by two 32K BYTESAVER
8
boards. Figure 6illustrates such an arrangement
along with the address range spanned by each ROM
socket.
Example 3
Suppose you programmed two 2716 PROMs
with Cromemco's Z-80 MONITOR and 3K Concrol
BASIC. The Z-BO MONITOR spans addresses
EOOOH-£3FFH. and Control BASIC spans E400H-
EFFF H. To load these programs, you would then
place the two programmed PROMs in sockets
ROMI2 and ROMI3 on a 32K BYTESAVER
assigned to 800fJH-FFFFH with A15=1. 0

32K Bytesaver
Figure 6- Two 32K BYTESAVERS Spanning The 64K Address Space
ADDRESS
(HEXI
ROM,.
FFH
r800
ROM "
rooo
ROY 13
<800
ROUIZ
<000
ROUII
D800
ROM '0
DOOO
ROM 9
C800
A 32K
ROM 8
COOO
BY-ESAVER
WITH AIS"" I
ROM 1
8800
ROM 6
8000
ROM •
>800
ROM •
>000
ROM 3
9600
ROM 2
9000
ROM I
e600
ROM D
8000
64K BYTES
ROM 15
1800
ROM 14
1000
ROM 13
6800
ROM 12
6000
ROM II
5600
ROM 10
5000
ROM 9
4600
A 321<
ROM 8
BYTESAVER
4000
WITH AIS=O
ROM 7
3800
ROM 6
'000
ROM 5
2800
ROM 4
2000
ROM
,
1800
ROM
2
1000
ROM I
0800
ROM 0
0000
9

32K Bytesaver
2.4 Shadowing ROM Socket Pairs
A 32K BYTESAVER board spans one half of
the CPU's 64K direct addressing range. The eight
SHADOW ROM switches allow the user to remove
pairs of ROM sockets thereby creating
4K·byte
"holes" in the board's memory map which may then
be "filled" with other memory modules. Each
SHADOW
ROM switch controls two vertically separ·
ated ROM sockets: the leftmost switch lnumber 11
controls the two leftmost sockets (ROM14 and
ROM15):
the rightmost switch (number 81 controls
the two rightmost sockets (ROM~ and ROMl). Posi-
tioning aswitch ON completely removes asocket
pair from the
memory map; an OFF switch leaves
the socket pair in the map.
Example 4
Suppose you have a Cromemco Disc Opera.ting
System (COOS)
with 32K of RAM spanning OOOOH
-7FFFH. and a 32K BYTESA VER assigned to
10
BOODH-FFFFH. The Cromemco Floppy Disc COIl-
troller board is factory shipped with the RODS
monitor program in ROM memory on the 4FDC
board. The RODS program spans addresses COOOH
-C3FFH, so yO/J SHADOW sockets ROMS and
ROM9. leavmg a hole at COOOH-C7FFH whIch
RODS then partially fills.
Further aswme you program one-half of a 2716
with Cromemco's Z-80 Monitor program (spanning
EOOOH-E3FFHJ. and you program four 2716s w;th
your own 8K-byte development system.
The
required sw;tch settings and the resulting
memory map are shown in Figure 7. 0
Carefully note that two empty ROM sockets are
not equivalent to SHADOWING the same two sock-
ets.
The 32K BYTESAVER will memory read data
0FFH from an unSHADOWED empty ROM socket,
and
as aresult will actively drive all eight 5-100 data
bus lines
010-017 high. The32K BYTE5AVER tri-
states
its 01 output lines when SHADOWED sockets
are addressed, whether they are empty or not.

..
32K Bvtesaver
Figure 7-Example 4 Switch Settings And Memory Banks
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.uK
BYT£SAJ £R •
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..... "1(
11

32K Bytesaver
2.5 MemoryBanks
BANK SELECT is an optional board feature
which effectively allows memory expansion beyond
the CPU's 64K direct addressing range. This feature
may be completely disabled by switch selecting
BANK DISABLE in the ADDR/CONTROL $\'\Iitch
group. When this is done. the eight BANK SELECT
switch settings become irrelevant. In this mode the
32K BYTESAVER exists only in the upper or lo ..... er
half of the CPU's 64K direct addressing range for
memory read, PROM programming or DMA opera-
tions.
To enable memory banks, switch select BANK
ENABLE in the ADDR/CONTROL switch group.
When this IS done, the 32K BYTESAVER is logical-
ly placed In one or more 64K-byte memory banks
with the eight BANK SELECT switches, and bank
addressing IS software controlled by executing the
OUT (40H),A (or equivalent) Z-80 instruction.
Memory may be stacked up to eight banks deep
(see Figure 81. Positioning one or more BANK
SELECT switches ON places a 32K BYTESAVER m
each correspondmg memory bank. On the other
hand, positioning all switches OFF completely reo
32K BYTES
Figure8- The Memory Map With Multiple Memory Banks
16-BIT
FFFFH
SIZK BYTES
TOTAL
32K BYTES
BANK 7
BANK6
BANK S
I- BANK"
I- BAN)'. 3
BANK 2
BANK I
ooooH L ---.lBANK 0
12

32K Bytesaver
moves the board frorn the memory map (except pos-
sibly for DMA transfers - see Section 2.7).
As stated above. memory banks are activated
and deactivated under software control. Each 32K
BYTESAVER contains an integral OUTPUT PORT
40H which latches the bits of the control byte Qut-
put to it by the CPU. Each set bit (logic 11 enables
its corresponding memory bank, and each reset bit
(logic 01 disables its bank. Control byte bit 7(MSBl
controls memory bank 7, bit 6 controls memory
bank 6, etc.
-----
. -- --
- - :: ~ -::.=.
If the 32K BYTESAVER is switch mapped into
any of the banks activated by the control byte (Iogi· •
calOR). the board responds when addressed and
thus is placed "in" the memory map. When this
condition occurs, the green LED indicator lights.
Conversely.
if the 32K BYTESAVER is switch
mapped into no bank activated by the output con-
trol
byte. the board will not respond when address-
ed
and thus is "out" of the memory map_ When a
control byte inactivates the board, the green LED
indicator goes out, and more specifically, the board
responds by tri-statlOg (floating) all of its output
Figure 9-Example 5 Switch Settings
AOOR/CJJt~""ROL
BOARD a /
BANK SELECT
\
,
~ = -t 'I
t ""
-AI5=1
L-SANK ENABLE
f\ '.
ADDR/;ONTROL BANK S,ELECT
~B~O;A~RD~A:;!~ /~;;;;:;;-..L --': \F""'''j
~5:or .. L\.--' , , UK Bt'r£SAlt'liR ,~
o'~r "'I r,
t . 'I accr~ ...
h
l..--AI5=1
L--BANK ENABLE
I
13
IN BANK 0-
n« _,rESAIE_·
I•

32K Bytesaver
lines. This behavior allows two or more memory
boards with BANK SELECT to occupy the same or
overlapping 16-bit address space but in different
memory banks. provided only one board is memory
active at atime. and all other boards are inactive.
Memory bank conflicts may result if:
al Two or more address overlapping memory
boards are switch assigned to the same mem-
ory bank, or
b) Two or more 16·bit address overlapping
memory boards assigned to disjoint memory
banks are simultaneously activated by the
samt! control byte.
Example 5
Suppose two 32K BYTESAVERs are both
mapped mto the upper 32K of memory fA 75~1).
and theIr memory bank switches are set as shown in
Figure 9. The rewlting memory map is then shown
In Figure 10.
Figure ID-Example 5 Memory Map
~'-----
16-BIT r-l~~~~~~~~l~
ADDRESS
FFFFH
BOARD A
ooooH
BANK 7
BANK 6
BANK 5
~ BANK 4
f- BANK 3
f- BANK 2
BANK I
L .J8ANK 0
14