Renesas 7200 Series User manual

Regarding the change of names mentioned in the document, such as Mitsubishi
Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas
Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog
and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)
Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi
Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names
have in fact all been changed to Renesas Technology Corp. Thank you for your understanding.
Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been
made to the contents of the document, and these changes do not constitute any alteration to the
contents of the document itself.
Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices
and power devices.
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers

MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 7200 SERIES
7220
Group
User’s Manual

keep safety first in your circuit designs !
●Mitsubishi Electric Corporation puts the maximum effort into making semiconductor
products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury,
fire or property damage. Remember to give due consideration to safety when
making your circuit designs, with appropriate measures such as (i) placement
of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention
against any malfunction or mishap.
Notes regarding these materials
●These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the customer’s
application; they do not convey any license under any intellectual property rights,
or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
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infringement of any third-party’s rights, originating in the use of any product
data, diagrams, charts or circuit application examples contained in these materials.
●All information contained in these materials, including product data, diagrams
and charts, represent information on products at the time of publication of these
materials, and are subject to change by Mitsubishi Electric Corporation without
notice due to product improvements or other reasons. It is therefore recommended
that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for the latest product information before
purchasing a product listed herein.
●Mitsubishi Electric Corporation semiconductors are not designed or manufactured
for use in a device or system that is used under circumstances in which human
life is potentially at stake. Please contact Mitsubishi Electric Corporation or an
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●Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or the
products contained therein.

Preface
This manual describes the hardware of the Mitsubishi
CMOS 8-bit microcomputers 7220 group.
After reading this manual, the user should have a
through knowledge of the functions and features of
7220 group, and should be able to fully utilize the
product. The manual starts with specifications and
ends with application examples.
For details of software, refer to the “SERIES 740
<SOFTWARE> USER’S MANUAL.”
For details of development support tools, refer to the
“DEVELOPMENT SUPPORT TOOLS FOR
MICROCOMPUTERS” data book.

i
BEFORE USING THIS MANUAL
This user’s manual consists of the following chapters. Refer to the chapter appropriate to your conditions,
such as hardware design or software development. The M37221M6-XXXSP/FP is used as a general example
in describing the functions of the 7220 group, unless other wise noted.
1. Organization
● CHAPTER 1 HARDWARE
This chapter describes features of the microcomputer, pin configuration, pin description, functional
block diagram.
●CHAPTER 2 FUNCTIONAL DESCRIPTION
This chapter describes operation of each peripheral function.
●CHAPTER 3 ELECTRIC CHARACTERISTICS
This chapter describes electric characteristics and standard characteristics.
●CHAPTER 4 M37220M3-XXXSP/FP
This chapter describes differences between the M37220M3-XXXSP/FP and M37221M6-XXXSP/FP.
●CHAPTER 5 APPLICATION
This chapter describes usage and application examples of peripheral functions, based mainly on
setting examples of related registers.
●CHAPTER 6 APPENDIX
This chapter includes precautions for systems development using the microcomputer, a list of control
registers, the mask ROM confirmation forms (mask ROM version) and mark specification forms which
are to be submitted when ordering.

ii
2. Register diagram
The figure of each register structure describes its functions, contents at reset, end attributes as follows:
Values immediately after reset release
Bit attributes
(Note 1)
(Note 2)
Bits
2: Bit attributes••••••The attributes of control register bits are classified into 3 types : read-only, write-only
and read and write. In the figure, these attributes are represented as follows :
: Bit in which nothing is assigned
Notes 1: Values immediately after reset release
0••••••“0” after reset release
1••••••“1” after reset release
?••••••Indeterminate after reset release
••••••Read enabled
••••••Read disabled
R••••••Read ••••••Write enabled
••••••Write disabled
••••••“0” can be set by software, but “1”
cannot be set.
W••••••Write
b7b6 b5b4b3 b2b1b0 CPU mode register (CPUM) (CM) [Address FB 16]
B After reset RW
CPU Mode Register
0, 1
2
3
to
5
0
1
Name Functions
Fix these bits to “0.”
Fix these bits to “1.”
1
Stack page selection
bit (CM2)
1
0: 0 page
1: 1 page
100
6, 7 Indeterminate
111
RW
RW
RW
RW
R
—W —
✽

7220 Group User’s Manual i
Table of contents
Table of contents
CHAPTER 1. OVERVIEW
1.1 Performance overview.......................................................................................................... 1-2
1.2 Pin configuration................................................................................................................... 1-5
1.3 Pin description ...................................................................................................................... 1-7
1.4 Functional block diagram ................................................................................................... 1-9
CHAPTER 2. FUNCTIONAL DESCRIPTION
2.1 Central processing unit....................................................................................................... 2-2
2.1.1 Accumulator (A) ............................................................................................................. 2-2
2.1.2 Index register X (X), index register Y (Y).................................................................. 2-2
2.1.3 Stack pointer (S)............................................................................................................ 2-3
2.1.4 Program counter (PC)................................................................................................... 2-6
2.1.5 Processor status register (PS)..................................................................................... 2-6
2.2 Access area............................................................................................................................ 2-8
2.2.1 Zero page (addresses 000016 to 00FF16)..................................................................2-10
2.2.2 Special page (addresses FF0016 to FFFF16) ............................................................2-10
2.3 Memory assignment ........................................................................................................... 2-11
2.3.1 Internal RAM ................................................................................................................ 2-16
2.3.2 I/O ports (addresses 00C016 to 00CD16) ................................................................... 2-16
2.3.3 DA registers (addresses 00CE16 and 00CF16).......................................................... 2-17
2.3.4 PWM registers (addresses 00D016 to 00D416 and 00F616) .....................................2-17
2.3.5 PWM output control registers (addresses 00D516 and 00D616) .............................2-17
2.3.6 Multi-master I2C-BUS related registers (addresses 00D716 to 00DB16).................2-17
2.3.7 Serial I/O related registers (addresses 00DC16 and 00DD16).................................2-17
2.3.8 CRT display related registers (addresses 00E016 to 00EC16) ................................2-17
2.3.9 A-D control register (addresses 00EE16 and 00EF16)..............................................2-18
2.3.10 Timer registers (addresses 00F016 to 00F316)........................................................2-18
2.3.11 Timer mode registers (address 00F416, 00F516) ....................................................2-19
2.3.12 CPU mode register (address 00FB16) .....................................................................2-19
2.3.13 Interrupt request registers (addresses 00FC16 and 00FD16).................................2-19
2.3.14 Interrupt control registers (addresses 00FE16 and 00FF16) ..................................2-19
2.3.15 2 page register (addresses 021716 to 021B16) (only M37221M8/MA-XXXSP) .. 2-19
2.3.16 CRT display RAM (addresses 060016 to 06B716) ..................................................2-19
2.3.17 ROM (addresses A00016 to FFFF16) ........................................................................ 2-19
2.3.18 CRT display ROM (addresses 1000016 to 11FFF16)..............................................2-19
2.4 Input/Output pins ................................................................................................................ 2-20
2.4.1 Programmable ports .................................................................................................... 2-20
2.4.2 Dedicated pins ............................................................................................................. 2-23
2.5 Interrupts .............................................................................................................................. 2-26
2.5.1 Interrupt sources.......................................................................................................... 2-27
2.5.2 Interrupt control............................................................................................................ 2-29
2.6 Timers.................................................................................................................................... 2-34
2.6.1 Timer functions ............................................................................................................ 2-35
2.6.2 Timers 3 and timer 4 when reset and when executing STP instruction..............2-39
i

Table of contents
7220 Group User’s Manual
ii
Table of contents
2.7 Serial I/O ............................................................................................................................... 2-40
2.7.1 Structure of serial I/O ................................................................................................. 2-40
2.7.2 Serial I/O register (address 00DD16) ......................................................................... 2-42
2.7.3 Clock source generating circuit ................................................................................. 2-42
2.7.4 Serial input/output common transmission/reception mode .....................................2-42
2.7.5 Serial I/O data receive method (when an internal clock is selected) ..................2-43
2.7.6 Serial I/O data transmit method (when an external clock is selected) ................2-44
2.7.7 Note when selecting a synchronous clock............................................................... 2-45
2.8 Multi-master I2C-BUS interface......................................................................................... 2-47
2.8.1 Construction of multi-master I2C-BUS interface.......................................................2-48
2.8.2 Multi-master I2C-BUS interface-related registers ..................................................... 2-49
2.8.3 START condition, STOP condition generation method...........................................2-58
2.9 A-D comparator ................................................................................................................... 2-61
2.10 PWM..................................................................................................................................... 2-63
2.10.1 8-bit PWM registers (addresses 00D016 to 00D416 and 00F616)
/DA registers (addresses 00CE16 and 00CF16) ....................................................2-64
2.10.2 14-bit PWM (DA output) ........................................................................................... 2-65
2.10.3 8-bit PWM (PWM0 to PWM5: address 00D016 to 00D416 and 00F616 ) .............2-67
2.10.4 14-bit PWM output control........................................................................................ 2-69
2.10.5 8-bit PWM output control.......................................................................................... 2-70
2.11 CRT display function ....................................................................................................... 2-71
2.11.1 Display position.......................................................................................................... 2-74
2.11.2 Character size............................................................................................................ 2-77
2.11.3 Memory for display.................................................................................................... 2-78
2.11.4 Color registers............................................................................................................ 2-82
2.11.5 Multiline display ......................................................................................................... 2-84
2.11.6 Character border function......................................................................................... 2-85
2.11.7 CRT output pin control ............................................................................................. 2-86
2.11.8 Raster coloring function............................................................................................ 2-87
2.11.9 Clock for display........................................................................................................ 2-88
2.12 ROM correction function................................................................................................. 2-89
2.13 Software runaway detect function ................................................................................ 2-90
2.14 Low-power dissipation mode ......................................................................................... 2-91
2.14.1 Stop mode .................................................................................................................. 2-91
2.14.2 Wait mode .................................................................................................................. 2-93
2.14.3 Interrupts in low-power dissipation mode............................................................... 2-93
2.15 Reset.................................................................................................................................... 2-95
2.15.1 Reset operation.......................................................................................................... 2-95
2.15.2 Internal state immediately after reset ..................................................................... 2-96
2.15.3 Notes for poweron reset........................................................................................... 2-99
2.16 Clock generating circuit................................................................................................ 2-100
2.17 Oscillation circuit............................................................................................................ 2-101
CHAPTER 3. ELECTRICAL CHARACTERISTICS
3.1 Electrical characteristics..................................................................................................... 3-2
3.2 Standard characteristics...................................................................................................... 3-6

7220 Group User’s Manual iii
Table of contents
CHAPTER 4. M37220M3-XXXSP/FP
4.1 Performance overview.......................................................................................................... 4-2
4.2 Pin configuration................................................................................................................... 4-4
4.3 Pin description ...................................................................................................................... 4-6
4.4 Functional block diagram ................................................................................................... 4-8
4.5 Functional description ......................................................................................................... 4-9
4.5.1 Access area.................................................................................................................. 4-10
4.5.2 Memory assignment..................................................................................................... 4-11
4.5.3 Input/Output pins ......................................................................................................... 4-14
4.5.4 Interrupts....................................................................................................................... 4-15
4.5.5 D-A converter ............................................................................................................... 4-17
4.5.6 CRT Display function .................................................................................................. 4-19
4.5.7 Internal state immediately after reset ....................................................................... 4-26
4.6 Electrical characteristics................................................................................................... 4-28
4.7 Standard characteristics.................................................................................................... 4-32
CHAPTER 5. APPLICATION
5.1 Example of multi-line display............................................................................................. 5-2
5.1.1 Specifications ................................................................................................................. 5-2
5.1.2 Connection example ...................................................................................................... 5-2
5.1.3 General flowchart........................................................................................................... 5-3
5.1.4 Set of display character data....................................................................................... 5-6
5.1.5 Line counter.................................................................................................................... 5-7
5.1.6 Processing time ............................................................................................................. 5-8
5.1.7 Set of multiple interrupts .............................................................................................. 5-9
5.2 Notes on programming for OSD (M37220M3-XXXSP/FP) ...........................................5-13
5.2.1 Setting of color registers ............................................................................................ 5-13
5.2.2 Setting of border selection register........................................................................... 5-14
5.2.3 Number of display characters .................................................................................... 5-14
5.3 Usage example of ROM correction function (M37221M8/MA-XXXSP) .....................5-15
5.3.1 Connection example .................................................................................................... 5-15
5.3.2 Correction example...................................................................................................... 5-15
5.3.3 E2PROM map ............................................................................................................... 5-17
5.3.4 General flowchart......................................................................................................... 5-19
5.3.5 Notes on use................................................................................................................ 5-20
5.4 Example of I2C-BUS interface control (M37221Mx-XXXSP/FP)..................................5-21
5.4.1 Specifications ............................................................................................................... 5-21
5.4.2 Connection example .................................................................................................... 5-21
5.4.3 E2PROM functions ....................................................................................................... 5-22
5.4.4 General flowchart......................................................................................................... 5-23
5.5 Example of I2C-BUS control by software (M37220M3-XXXSP/FP)............................5-26
5.5.1 Specifications ............................................................................................................... 5-26
5.5.2 Connection example .................................................................................................... 5-26
5.5.3 Single-chip color TV signal processor function .......................................................5-27
5.5.4 General flowchart......................................................................................................... 5-28
5.5.5 Data setting according to key processing ................................................................5-34
5.5.6 Flowchart of data setting according to key processing..........................................5-36
5.5.7 Register map................................................................................................................ 5-39
5.6 Application circuit example.............................................................................................. 5-45
5.6.1 Application circuit example 1 ..................................................................................... 5-45
5.6.2 Application circuit example 2 ..................................................................................... 5-46

Table of contents
7220 Group User’s Manual
iv
CHAPTER 6. APPENDIX
6.1 Package outline..................................................................................................................... 6-2
6.2 Termination of unused pins ............................................................................................... 6-3
6.3 Notes on use ......................................................................................................................... 6-4
6.3.1 Notes on processor status register ............................................................................. 6-4
6.3.2 Notes on decimal operation ......................................................................................... 6-5
6.3.3 Notes on Interrupts........................................................................................................ 6-5
6.3.4 Notes on serial I/O........................................................................................................ 6-6
6.3.5 Notes on timer ............................................................................................................... 6-7
6.3.6 Notes on A-D comparator............................................................................................. 6-8
6.3.7 Note on RESET pin....................................................................................................... 6-8
6.3.8 Notes on input and output pins................................................................................... 6-9
6.3.9 Note on JMP instruction ............................................................................................... 6-9
6.3.10 Note on multi-master I2C-BUS interface................................................................. 6-10
6.3.11 Termination of unused pins...................................................................................... 6-10
6.4 Counter measures against noise .................................................................................... 6-11
6.4.1 Shortest wiring length ................................................................................................. 6-11
6.4.2 connection of a bypass capacitor across VSS line and VCC line............................6-13
6.4.3 Wiring to analog input pins ........................................................................................ 6-13
6.4.4 Oscillator concerns ...................................................................................................... 6-14
6.4.5 Setup for I/O ports ...................................................................................................... 6-15
6.4.6 Providing of watchdog timer function by software ..................................................6-16
6.5 Memory assignment ........................................................................................................... 6-17
6.6 SFR assignment .................................................................................................................. 6-20
6.7 Control registers ................................................................................................................. 6-30
6.8 Ports ...................................................................................................................................... 6-51
6.9 Machine instruction table.................................................................................................. 6-53
6.10 Instruction code table...................................................................................................... 6-63
6.11 Mask ROM ordering method........................................................................................... 6-64
6.12 Mark specification form................................................................................................... 6-80

7220 Group User’s Manual v
List of figures
List of figures
CHAPTER 1. OVERVIEW
Fig. 1.2.1 Pin configuration (top view) (1) ................................................................................. 1-5
Fig. 1.2.2 Pin configuration (top view) (2) ................................................................................. 1-6
Fig. 1.4.1 Functional block diagram............................................................................................ 1-9
CHAPTER 2. FUNCTIONAL DESCRIPTION
Fig. 2.1.1 Registers configuration diagram ................................................................................ 2-2
Fig. 2.1.2 CPU mode register...................................................................................................... 2-3
Fig. 2.1.3 Sequence of push onto/pop from a stack during interrupts and
subroutine calls............................................................................................................ 2-5
Fig. 2.1.4 Contents of stack after execution of BRK instruction.............................................2-7
Fig. 2.2.1 Access area of M37221M4-XXXSP and M37221M6-XXXSP/FP ...........................2-8
Fig. 2.2.2 Access area of M37221M8-XXXSP and M37221MA-XXXSP.................................2-9
Fig. 2.3.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............2-11
Fig. 2.3.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP..................2-12
Fig. 2.3.3 Memory map of SFR (special function register) (1) .............................................2-13
Fig. 2.3.4 Memory map of SFR (special function register) (2) .............................................2-14
Fig. 2.3.5 Memory map of 2 page register (only M37221M8-XXXSP and
M37221MA-XXXSP)................................................................................................... 2-15
Fig. 2.3.6 I/O setting example of port ...................................................................................... 2-16
Fig. 2.3.7 Access to timer registers.......................................................................................... 2-18
Fig. 2.4.1 I/O pin block diagram (1) ......................................................................................... 2-24
Fig. 2.4.2 I/O pin block diagram (2) ......................................................................................... 2-25
Fig. 2.5.1 VSYNC interrupt generation timing.............................................................................. 2-27
Fig. 2.5.2 Interrupt control logic ................................................................................................ 2-29
Fig. 2.5.3 Interrupt request register 1 (address 00FC16) ........................................................2-30
Fig. 2.5.4 Interrupt request register 2 (address 00FD16) ........................................................2-30
Fig. 2.5.5 Interrupt control register 1 (address 00FE16) .........................................................2-31
Fig. 2.5.6 Interrupt control register 2 (address 00FF16)..........................................................2-31
Fig. 2.5.7 Interrupt input polatiry register (address 00F916)...................................................2-32
Fig. 2.5.8 CRT port control register (address 00EC16) ...........................................................2-32
Fig. 2.5.9 Interrupt control system ............................................................................................ 2-33
Fig. 2.5.10 Interrupt vector table............................................................................................... 2-33
Fig. 2.6.1 Timer 1, timer 2, timer 3, and timer 4 block diagram..........................................2-34
Fig. 2.6.2 Timer overflow timing................................................................................................ 2-35
Fig. 2.6.3 Timer 12 mode register (address 00F416) ..............................................................2-36
Fig. 2.6.4 Timer 34 mode register (address 00F516) ..............................................................2-37
Fig. 2.6.5 Example of timer system .......................................................................................... 2-38
Fig. 2.7.1 Serial I/O block diagram........................................................................................... 2-41
Fig. 2.7.2 Serial I/O mode register (address 00DC16) ............................................................2-41
Fig. 2.7.3 Serial input/output common transfer mode block diagram...................................2-42
Fig. 2.7.4 Serial I/O register when receiving (when SM5 = “0”)...........................................2-43
Fig. 2.7.5 Serial I/O register when transmitting (when SM5 = “0”) ......................................2-44
Fig. 2.7.6 Timing diagram of serial I/O .................................................................................... 2-45
Fig. 2.7.7 Connection example for serial I/O transmit/receive ..............................................2-46
Fig. 2.7.8 Serial data transmit/receive processing sequence ................................................2-46

vi
List of figures
7220 Group User’s Manual
Fig. 2.8.1 Block diagram of multi-masteer I2C-BUS interface................................................2-48
Fig. 2.8.2 I2C data shift register ................................................................................................ 2-49
Fig. 2.8.3 I2C address register................................................................................................... 2-50
Fig. 2.8.4 I2C clock control register .......................................................................................... 2-52
Fig. 2.8.5 Connection port control by BSEL0 and BSEL1.....................................................2-53
Fig. 2.8.6 I2C control register..................................................................................................... 2-54
Fig. 2.8.7 Interrupt request signal generating timing.............................................................. 2-57
Fig. 2.8.8 I2C status register...................................................................................................... 2-57
Fig. 2.8.9 START condition generation timing diagram ........................................................2-58
Fig. 2.8.10 STOP condition generation timing diagram ........................................................2-58
Fig. 2.8.11 START condition/STOP condition detect timing diagram ...................................2-59
Fig. 2.8.12 Address data communication format ................................................................... 2-60
Fig. 2.9.1 A-D comparator block diagram ................................................................................ 2-61
Fig. 2.9.2 A-D control register 1 (address 00EE16)................................................................. 2-62
Fig. 2.9.3 A-D control register 2 (address 00EF16) ................................................................. 2-62
Fig. 2.10.1 14-bit PWM (DA) block diagram............................................................................ 2-63
Fig. 2.10.2 8-bit PWM block diagram ....................................................................................... 2-64
Fig. 2.10.3 14-bit PWM output example (f(XIN) = 8 MHz)...................................................... 2-66
Fig. 2.10.4 Pulse waveforms corresponding to weight of each bit of 8-bit PWM register 2-68
Fig. 2.10.5 Example of 8-bit PWM output................................................................................ 2-68
Fig. 2.10.6 PWM output control register 1 (address 00D516) ................................................2-69
Fig. 2.10.7 PWM output control register 2 (address 00D616) ................................................2-70
Fig. 2.11.1 Structure of CRT display character....................................................................... 2-71
Fig. 2.11.2 CRT display circuit block diagram......................................................................... 2-72
Fig. 2.11.3 CRT control register (address 00EA16) ................................................................. 2-73
Fig. 2.11.4 Count method of synchronous signal.................................................................... 2-74
Fig. 2.11.5 Display position........................................................................................................ 2-75
Fig. 2.11.6 Vertical position register n (addresses 00E116 and 00E216)...............................2-76
Fig. 2.11.7 Horizontal position register (address 00E016).......................................................2-76
Fig. 2.11.8 Character size register (address 00E416) ............................................................. 2-77
Fig. 2.11.9 Display start position (horizontal direction) for each character size.................2-77
Fig. 2.11.10 Example of display character data storing form................................................2-78
Fig. 2.11.11 Structure of CRT display RAM ............................................................................ 2-81
Fig. 2.11.12 Color register n (addresses 00E616 to 00E916) ..................................................2-82
Fig. 2.11.13 Generation timing of CRT interrupt request.......................................................2-84
Fig. 2.11.14 Display state of blocks and occurrence of CRT interrupt request..................2-84
Fig. 2.11.15 Border example...................................................................................................... 2-85
Fig. 2.11.16 Border selection register (address 00E516) ........................................................2-85
Fig. 2.11.17 CRT port control register (address 00EC16).......................................................2-86
Fig. 2.11.18 MUTE signal output example............................................................................... 2-87
Fig. 2.11.19 CRT clock selection register................................................................................ 2-88
Fig. 2.12.1 ROM correction address registers......................................................................... 2-89
Fig. 2.12.2 ROM correction enable register............................................................................. 2-89
Fig. 2.13.1 Sequence at detecting software runaway detection............................................2-90
Fig. 2.14.1 Oscillation stabilizing time at return by reset input.............................................2-92
Fig. 2.14.2 Execution sequence example at return by occurrence of INT0 interrupt
request ...................................................................................................................... 2-92
Fig. 2.14.3 Reset input time....................................................................................................... 2-93
Fig. 2.14.4 State transitions of low-power dissipation mode .................................................2-94

7220 Group User’s Manual vii
List of figures
Fig. 2.15.1 Timing diagram at reset.......................................................................................... 2-95
Fig. 2.15.2 Internal state immediately after reset (1) .............................................................2-96
Fig. 2.15.3 Internal state immediately after reset (2) .............................................................2-97
Fig. 2.15.4 Internal state immediately after reset (3) (only M37221M8/MA-XXXSP) ........ 2-98
Fig. 2.15.5 Voltage at poweron reset ....................................................................................... 2-99
Fig. 2.15.6 Example of reset circuit (1).................................................................................... 2-99
Fig. 2.15.7 Example of reset circuit (2).................................................................................... 2-99
Fig. 2.16.1 Clock generating circuit block diagram...............................................................2-100
Fig. 2.17.1 Clock oscillation circuit using a ceramic resonator...........................................2-101
Fig. 2.17.2 External clock input circuit example....................................................................2-101
Fig. 2.17.3 Clock oscillation circuit for CRT display.............................................................2-101
CHAPTER 3. ELECTRICAL CHARACTERISTICS
Fig. 3.1.1 Definition diagram of timing on multi-master I2C-BUS............................................ 3-5
CHAPTER 4. M37220M3-XXXSP/FP
Fig. 4.2.1 Pin configuration (top view) (1) ................................................................................. 4-4
Fig. 4.2.2 Pin configuration (top view) (2) ................................................................................. 4-5
Fig. 4.4.1 Functional block diagram............................................................................................ 4-8
Fig. 4.5.1 Access area................................................................................................................ 4-10
Fig. 4.5.2 Memory assignment................................................................................................... 4-11
Fig. 4.5.3 Memory map of SFR (special function register) (1) .............................................4-12
Fig. 4.5.4 Memory map of SFR (special function register) (2) .............................................4-13
Fig. 4.5.5 Interrupt request register 1 (address 00FC16)........................................................ 4-16
Fig. 4.5.6 Interrupt control register 1 (address 00FE16) .........................................................4-16
Fig. 4.5.7 D-A converter block diagram.................................................................................... 4-17
Fig. 4.5.8 DA n conversion register (addresses 00DE16 and 00DF16) ..................................4-18
Fig. 4.5.9 Port P3 output mode control register (address 00CD16) ......................................4-18
Fig. 4.5.10 CRT display circuit block diagram......................................................................... 4-20
Fig. 4.5.11 Example of display character data storing form..................................................4-21
Fig. 4.5.12 Structure of CRT display RAM .............................................................................. 4-23
Fig. 4.5.13 Border selection register (addresses 00E516) ......................................................4-24
Fig. 4.5.14 Color register n (addresses 00E616 to 00E916) ....................................................4-24
Fig. 4.5.15 CRT control register (address 00EA16) ................................................................. 4-25
Fig. 4.5.16 CRT port control register (address 00EC16) ......................................................... 4-25
Fig. 4.5.17 Internal state immediately after reset (1) .............................................................4-26
Fig. 4.5.18 Internal state immediately after reset (2) .............................................................4-27
CHAPTER 5. APPLICATION
Fig. 5.1.1 Connection example .................................................................................................... 5-2
Fig. 5.1.2 Display example........................................................................................................... 5-2
Fig. 5.1.3 Flowchart of initialization processing routine ........................................................... 5-3
Fig. 5.1.4 Flowchart of VSYNC interrupt processing routine ....................................................... 5-4
Fig. 5.1.5 Flowchart of CRT interrupt processing routine........................................................ 5-5
Fig. 5.1.6 Set of display character data..................................................................................... 5-6
Fig. 5.1.7 Example of setup timing for line counter and display character data..................5-7
Fig. 5.1.8 Timing of interrupt processing when not setting multiple interrupts .....................5-9
Fig. 5.1.9 Timing when all interrupt request bits are “1” at the same sampling point ..... 5-10

viii
List of figures
7220 Group User’s Manual
Fig. 5.1.10 Flowchart of CRT interrupt processing routine
(when setting multiple interrupts) .......................................................................... 5-11
Fig. 5.1.11 Flowchart of VSYNC interrupt processing routine
(when setting multiple interrupts) .......................................................................... 5-12
Fig. 5.2.1 Color register n (M37221ERSS) .............................................................................. 5-13
Fig. 5.2.2 Color register n (M37220M3-XXXSP/FP)................................................................5-14
Fig. 5.2.3 Border selection register (M37220M3-XXXSP/FP) ................................................5-14
Fig. 5.3.1 Connection example .................................................................................................. 5-15
Fig. 5.3.2 Correction example (1) ............................................................................................. 5-15
Fig. 5.3.3 Correction example (2) ............................................................................................. 5-16
Fig. 5.3.4 E2PROM map when using ROM correction function (1).......................................5-17
Fig. 5.3.5 E2PROM map when using ROM correction function (2).......................................5-18
Fig. 5.3.6 General flowchart when using ROM correction function ......................................5-19
Fig. 5.4.1 Connection example .................................................................................................. 5-21
Fig. 5.4.2 Byte write timing ........................................................................................................ 5-22
Fig. 5.4.3 Random address read timing................................................................................... 5-22
Fig. 5.4.4 Flowchart of write processing routine ..................................................................... 5-23
Fig. 5.4.5 Flowchart of read processing routine...................................................................... 5-24
Fig. 5.4.6 Flowchart of data output processing routine.......................................................... 5-25
Fig. 5.5.1 Connection example .................................................................................................. 5-26
Fig. 5.5.2 Staus read timing....................................................................................................... 5-27
Fig. 5.5.3 Byte write timing ........................................................................................................ 5-27
Fig. 5.5.4 Flowchart of write processing routine ..................................................................... 5-28
Fig. 5.5.5 Flowchart of read processing routine...................................................................... 5-29
Fig. 5.5.6 Flowchart of data output processing routine.......................................................... 5-30
Fig. 5.5.7 Flowchart of START condition processing routine ................................................5-31
Fig. 5.5.8 Flowchart of STOP condition processing routine ..................................................5-31
Fig. 5.5.9 Flowchart of bus H processing routine................................................................... 5-31
Fig. 5.5.10 Flowchart of data input processing routine.......................................................... 5-32
Fig. 5.5.11 Flowchart of return ACK processing routine........................................................ 5-33
Fig. 5.5.12 Flowchart of return NACK processing routine .....................................................5-33
Fig. 5.5.13 Flowchart of power on processing ........................................................................ 5-36
Fig. 5.5.14 Flowchart of “CH UP/DOWN key” input processing............................................5-37
Fig. 5.5.15 Flowchart of “picture memory switching key” input processing.........................5-38
Fig. 5.5.16 Status data register................................................................................................. 5-39
Fig. 5.5.17 Map of write data register...................................................................................... 5-41
Fig. 5.6.1 Application circuit example 1 (I2C-BUS chassis) ...................................................5-45
Fig. 5.6.2 Application circuit example 2 (Non-BUS chassis) .................................................5-46
CHAPTER 6. APPENDIX
Fig. 6.3.1 Initialization of flags in PS ......................................................................................... 6-4
Fig. 6.3.2 Stack contents after PHP instruction execution ...................................................... 6-4
Fig. 6.3.3 Note when executing PLP instruction ....................................................................... 6-4
Fig. 6.3.4 Note in decimal arithmetic operation ........................................................................ 6-5
Fig. 6.3.5 Execution of BBC or BBS instruction ....................................................................... 6-5
Fig. 6.3.6 Sequence for switching an external interrupt detection edge................................6-6
Fig. 6.3.7 Initialization for serial I/O............................................................................................ 6-6
Fig. 6.3.8 Relation between timer values and their values read
(timer setting value = 2).............................................................................................. 6-7
Fig. 6.3.9 Relation between timer values and their values read when two timers are
connected in series (timers 1 and 2 are connected, timer 1 setting value = 2,
timer 2 setting value = 1)............................................................................................ 6-7

7220 Group User’s Manual ix
List of figures
Fig. 6.4.1 Wiring for RESET input pin...................................................................................... 6-11
Fig. 6.4.2 Wiring for clock I/O pin............................................................................................. 6-11
Fig. 6.4.3 Wiring for CNVSS pin ................................................................................................. 6-12
Fig. 6.4.4 Wiring for VPP pin of One Time PROM and EPROM version..............................6-12
Fig. 6.4.5 Bypass capacitor across VSS line and VCC line...................................................... 6-13
Fig. 6.4.6 Analog signal line and resistor and capacitor .......................................................6-13
Fig. 6.4.7 Wiring for large current signal line.......................................................................... 6-14
Fig. 6.4.8 Wiring for signal line where potential levels charge frequently...........................6-14
Fig. 6.4.9 VSS pattern on underside of an oscillator............................................................... 6-14
Fig. 6.4.10 Setup for I/O ports .................................................................................................. 6-15
Fig. 6.4.11 Watchidog timer by software.................................................................................. 6-16
Fig. 6.5.1 Memory assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP ............6-17
Fig. 6.5.2 Memory assignment of M37221M8-XXXSP and M37221MA-XXXSP..................6-18
Fig. 6.5.3 Memory assignment of M37220M3-XXXSP/FP ...................................................... 6-19
Fig. 6.6.1 SFR assignment (including internal state immediately after reset and access
access characteristics) (1) (M37221Mx-XXXSP/FP)..............................................6-20
Fig. 6.6.2 SFR assignment (including internal state immediately after reset and access
access characteristics) (2) (M37221Mx-XXXSP/FP)..............................................6-22
Fig. 6.6.3 Memory map of 2 page register (including internal state immediately after reset and
after reset and access characteristics) (3)
(only M37221M8-XXXSP and M37221MA-XXXSP) ...............................................6-24
Fig. 6.6.4 SFR assignment (including internal state immediately after reset and access
after reset and access characteristics) (4) (M37220M3-XXXSP/FP) ..................6-26
Fig. 6.6.5 SFR assignment (including internal state immediately after reset and access
after reset and access characteristics) (5) (M37220M3-XXXSP/FP) ..................6-28
Fig. 6.7.1 Port Pi direction register........................................................................................... 6-30
Fig. 6.7.2 Port P3 direction register.......................................................................................... 6-30
Fig. 6.7.3 Port P5 direction register.......................................................................................... 6-31
Fig. 6.7.4 Port P3 output mode control register...................................................................... 6-31
Fig. 6.7.5 PWM output control register 1................................................................................. 6-32
Fig. 6.7.6 PWM output control register 2................................................................................. 6-32
Fig. 6.7.7 I2C data shift register ................................................................................................ 6-33
Fig. 6.7.8 I2C address register................................................................................................... 6-33
Fig. 6.7.9 I2C status register...................................................................................................... 6-34
Fig. 6.7.10 I2C control register................................................................................................... 6-35
Fig. 6.7.11 I2C clock contorol register ...................................................................................... 6-36
Fig. 6.7.12 Serial I/O mode register ......................................................................................... 6-37
Fig. 6.7.13 DA conversion register n (only M37220M3-XXXSP/FP).....................................6-38
Fig. 6.7.14 Horizontal position register..................................................................................... 6-38
Fig. 6.7.15 Vertical position register n...................................................................................... 6-39
Fig. 6.7.16 Character size register............................................................................................ 6-39
Fig. 6.7.17 Border selection register......................................................................................... 6-40
Fig. 6.7.18 Color register n........................................................................................................ 6-41
Fig. 6.7.19 CRT control register................................................................................................ 6-42
Fig. 6.7.20 CRT port control register........................................................................................ 6-43
Fig. 6.7.21 CRT clock selection register .................................................................................. 6-44
Fig. 6.7.22 CRT A-D control register 1 .................................................................................... 6-45
Fig. 6.7.23 A-D control register 2 ............................................................................................. 6-45
Fig. 6.7.24 Timer 12 mode register .......................................................................................... 6-46
Fig. 6.7.25 Timer 34 mode register .......................................................................................... 6-47
Fig. 6.7.26 Interrupt input polarity register............................................................................... 6-47
Fig. 6.7.27 CPU mode register.................................................................................................. 6-48

x
List of figures
7220 Group User’s Manual
Fig. 6.7.28 Interrupt request register 1..................................................................................... 6-48
Fig. 6.7.29 Interrupt request register 2..................................................................................... 6-49
Fig. 6.7.30 Interrupt control register 1...................................................................................... 6-49
Fig. 6.7.31 Interrupt control register 2...................................................................................... 6-50
Fig. 6.7.32 ROM correction enable register............................................................................. 6-50
Fig. 6.8.1 I/O pin block diagram (1) ......................................................................................... 6-51
Fig. 6.8.2 I/O pin block diagram (2) ......................................................................................... 6-52

7220 Group User’s Manual xi
List of tables
7220 Group User’s Manual xi
List of tables
CHAPTER 1. OVERVIEW
Table 1.1.1 Performance overview (1)........................................................................................ 1-3
Table 1.1.2 Performance overview (2)........................................................................................ 1-4
Table 1.3.1 Pin description (1) .................................................................................................... 1-7
Table 1.3.2 Pin description (2) .................................................................................................... 1-8
CHAPTER 2. FUNCTIONAL DESCRIPTION
Table 2.2.1 Zero page addressing ............................................................................................ 2-10
Table 2.2.2 Special page addressing........................................................................................ 2-10
Table 2.4.1 List of programmable port functions .................................................................... 2-22
Table 2.5.1 Interrupt sources, vector addresses and priority................................................2-26
Table 2.6.1 Memory map of timer-related registers................................................................ 2-37
Table 2.6.2 Contents of timers 3 and 4 when reset or when executing STP instruction 2-39
Table 2.7.1 Clock source selection........................................................................................... 2-42
Table 2.8.1 Multi-master I2C-BUS interface functions.............................................................2-47
Table 2.8.2 START condition/STOP condition generation timing table................................2-58
Table 2.8.3 START condition/STOP condition detect conditions ..........................................2-59
Table 2.9.1 Relationship between contents of A-D control register 2 and reference
voltage “Vref” .......................................................................................................... 2-62
Table 2.10.1 PWM function performance (at oscillation frequency = 8 MHz).....................2-63
Table 2.10.2 The relation between DLand tm(m= “0” to “63”).............................................2-65
Table 2.11.1 Outline of CRT display function.......................................................................... 2-71
Table 2.11.2 Relationship between set value in character size register and character
size......................................................................................................................... 2-77
Table 2.11.3 Character code table (be omitted partly) .......................................................... 2-79
Table 2.11.4 Contents of CRT display RAM............................................................................ 2-80
Table 2.11.5 Display example of character background coloring (when green is set for
a character and blue is set for background color) ..........................................2-83
Table 2.11.6 Relationship between set value of border selection register and character
border function...................................................................................................... 2-85
Table 2.14.1 State in stop mode............................................................................................... 2-91
Table 2.14.2 State in wait mode ............................................................................................... 2-93
Table 2.14.3 Invalid interrupts in the wait mode..................................................................... 2-93

xii
List of tables
7220 Group User’s Manual
CHAPTER 4. M37220M3-XXXSP/FP
Table 4.1.1 Performance overview (1)........................................................................................ 4-2
Table 4.1.2 Performance overview (2)........................................................................................ 4-3
Table 4.3.1 Pin description (1) .................................................................................................... 4-6
Table 4.3.2 Pin description (2) .................................................................................................... 4-7
Table 4.5.1 Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP ...........4-9
Table 4.5.2 Difference of programmable ports between M37221M6-XXXSP/FP and
M37220M3-XXXSP/FP ........................................................................................... 4-14
Table 4.5.3 Interrupt sources, vector addresses and priority................................................4-15
Table 4.5.4 Relationship between contents of D-A conversion register and output voltage “V”
output voltage “V”................................................................................................... 4-17
Table 4.5.5 Outline of CRT display function............................................................................ 4-19
Table 4.5.6 Character code table (be omitted partly).............................................................4-22
Table 4.5.7 Contents of CRT display RAM.............................................................................. 4-22
CHAPTER 5. APPLICATION
Table 5.5.1 Data setting at tuning and searching................................................................... 5-34
Table 5.5.2 Data setting at “volume UP/DOWN key” input ...................................................5-34
Table 5.5.3 Data setting at “screen-size-related keys” input.................................................5-34
Table 5.5.4 Data setting at “picture data control key” and
“picture memory switching key” input .................................................................. 5-34
Table 5.5.5 Data setting when changing AFT state ............................................................... 5-35
Table 5.5.6 Data setting when changing audio mute state ...................................................5-35
Table 5.5.7 Data setting when changing video mute state ...................................................5-35
Table 5.5.8 Data setting when adjusting white balance......................................................... 5-35
Table 5.5.9 Relationship between DFA and DL TIME............................................................ 5-42
Table 5.5.10 Setting of color system (at sub-address 0916, write data) ..............................5-43
CHAPTER 6. APPENDIX
Table 6.2.1 Termination of unused pins..................................................................................... 6-3

CHAPTER 1
OVERVIEW
1.1 Performance overview
1.2 Pin configuration
1.3 Pin description
1.4 Functional block diagram

1-2 7220 Group User’s Manual
OVERVIEW
1.1 Performance overview
1.1 Performance overview
The 8-bit microcomputers:
-M37221M4-XXXSP
-M37221M6-XXXSP/FP
-M37221M8-XXXSP
-M37221MA-XXXSP
-M37220M3-XXXSP/FP
have their simple instruction set; the ROM, RAM, and I/O addresses are placed on the same memory map
to enable easy programming.
Furthermore, they have many additional functions for tuning system for TV:
●PWM output (14-bit and 8-bit)
●CRT display
●A-D comparator (resistance string method)
●Software runaway detection
●Multi-master I2C-BUS interface function
●ROM correction function
And also, they can allow low power dissipation by the use of CMOS processing.
The M37221M6-XXXSP/FP is used as a general example in describing the functions of the above microcomputers,
unless otherwise noted.