Cypress Semiconductor CY62157CV30 User manual

512K x 16 Static RAM
CY62157CV30/33
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05014 Rev. *F Revised August 31, 2006
Features
• Temperature Ranges
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
•Voltage range:
— CY62157CV30: 2.7V–3.3V
— CY62157CV33: 3.0V–3.6V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 5.5 mA @ f = fmax
• Low standby power
• Easy memory expansionwithCE1,CE2andOE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free and non Pb-free 48-ball FBGA
package
Functional Description[1]
The CY62157CV30/33 are high-performance CMOS static
RAMs organized as 512K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active
current. This is ideal for providing More Battery Life™
(MoBL™) in portable applications such as cellular telephones.
The devices also have an automatic power-down feature that
significantly reduces power consumption by 80% when
addresses are not toggling. The device can also be put into
standbymodereducingpowerconsumptionbymore than99%
when deselected (CE1HIGH or CE2LOW or both BLE and
BHE are HIGH). The input/output pins (I/O0through I/O15) are
placed in a high-impedance state when: deselected (CE1
HIGH or CE2LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE1LOW and CE2
HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from
I/O pins (I/O0through I/O7), is written into the location
specified on the address pins (A0through A18). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8through
I/O15) is written into the location specified on the address pins
(A0through A18).
Reading from the device is accomplished by taking Chip
Enable 1 (CE1) and Output Enable (OE) LOW and Chip
Enable 2 (CE2) HIGH while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O0to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8to I/O15. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
The CY62157CV30/33 are available in a 48-ball FBGA
package.
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Logic Block Diagram
512K × 16
RAM Array I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
WE
BLE
BHE
A
16
A
0
A
1
A
17
A
9
A
18
A
10
Power-down
Circuit
BHE
BLE
CE
2
CE
1
CE
2
CE
1
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 2 of 13
Product Portfolio
Product Range VCC Range
Power Dissipation
Operating (ICC) mA Standby (ISB2)
µAf = 1 MHz f = fmax
Min. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max. Typ.[2] Max.
CY62157CV30 Automotive-E 2.7V 3.0V 3.3V 1.5 3 7 15 8 70
CY62157CV33 Automotive-A 3.0V 3.3V 3.6V 1.5 3 5.5 12 10 30
Automotive-E 1.5 3 7 15 10 80
Pin Configurations[2, 3, 4]
FBGA (Top View)
Pin Definitions
Name Definition
Input A0-A18. Address Inputs
Input/Output I/O0-I/O15. Data lines. Used as input or output lines depending on operation
Input/Control WE. Write Enable, Active LOW. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted.
Input/Control CE1. Chip Enable 1, Active LOW.
Input/Control CE2. Chip Enable 2, Active HIGH.
Input/Control OE. Output Enable, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins
Ground Vss. Ground for the device
Power Supply Vcc. Power supply for the device
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA= 25°C.
3. NC pins are not connected on the die.
4. E3 (DNU) can be left as NC or VSS to ensure proper application.
WE
A
11
A
10
A
6
A
0
A
3
CE
1
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
CE
2
A
17
A
2
A
1
BLE
V
CC
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
NC
A
18
NC
D
E
B
A
C
F
G
H
A
16
DNU
V
SS
V
CC
326541
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 3 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage to Ground Potential...–0.5V to Vccmax + 0.5V
DC Voltage Applied to Outputs
in High-Z State[5]....................................–0.5V to VCC + 0.3V
DC Input Voltage[5].................................–0.5V to VCC + 0.3V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
Device Range
Ambient
Temperature
[TA][6] VCC
CY62157CV30 Automotive-E –40°Cto+125°C 2.7V–3.3V
CY62157CV33 Automotive-A –40°C to +85°C 3.0V–3.6V
Automotive-E –40°Cto+125°C
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62157CV30-70
UnitMin. Typ.[2] Max.
VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3V V
VIL Input LOW Voltage –0.3 0.8 V
IIX Input Leakage
Current GND <VI< VCC –10 +10 µA
IOZ Output Leakage
Current GND < VO <VCC, Output Disabled –10 +10 µA
ICC VCC Operating
Supply
Current
f = fMAX = 1/tRC VCC = 3.3V
IOUT = 0 mA
CMOS Levels
715mA
f = 1 MHz 1.5 3
ISB1 Automatic CE
Power-Down
Current— CMOS
Inputs
CE1> VCC – 0.2V or CE2< 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = fmax (Address and Data Only),
f=0(OE
, WE, BHE and BLE)
870µA
ISB2 Automatic CE
Power-Down
Current—CMOS
Inputs
CE1> VCC – 0.2V or CE2< 0.2V
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.3V
870µA
Notes:
5. VIL(min.) = –2.0V for pulse durations less than 20 ns.
6. TAis the “Instant-On” case temperature.
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 4 of 13
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
CY62157CV33-70
UnitMin. Typ.[2] Max.
VOH Output HIGH
Voltage IOH = –1.0 mA VCC = 3.0V 2.4 V
VOL Output LOW
Voltage IOL = 2.1 mA VCC = 3.0V 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3V V
VIL Input LOW Voltage –0.3 0.8 V
IIX Input Leakage
Current GND <VI< VCC Auto-A –1 +1 µA
Auto-E –10 +10 µA
IOZ Output Leakage
Current GND < VO <VCC, Output Disabled Auto-A –1 +1 µA
Auto-E –10 +10 µA
ICC VCC Operating
Supply
Current
f = fMAX = 1/tRC VCC = 3.6V
IOUT = 0 mA
CMOSLevels
Auto-A 5.5 12 mA
Auto-E 7 15
f = 1 MHz Auto-A/
Auto-E 1.5 3
ISB1 Automatic CE
Power-Down
Current—CMOS
Inputs
CE1> VCC – 0.2V or
CE2< 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V,
f = fmax (Address and Data
Only),
f = 0 (OE,WE,BHE,and BLE)
Auto-A 10 30 µA
Auto-E 10 80 µA
ISB2 Automatic CE
Power-Down
Current—CMOS
Inputs
CE1> VCC – 0.2V or
CE2< 0.2V
VIN > VCC – 0.2V or
VIN < 0.2V,
f = 0, VCC = 3.6V
Auto-A 10 30 µA
Auto-E 10 80 µA
Thermal Resistance[7]
Parameter Description Test Conditions FBGA Unit
ΘJA Thermal Resistance
(Junction to Ambient) Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 °C/W
ΘJC Thermal Resistance
(Junction to Case) 16 °C/W
Note:
7. Tested initially and after any design or process changes that may affect these parameters.
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 5 of 13
Capacitance[7]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = VCC(typ.) 6pF
COUT Output Capacitance 8 pF
AC Test Loads and Waveforms
V
CC
Typ
V
CC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
OUTPUT V
TH
Equivalent to: THÉVENIN EQUIVALENT
ALL INPUT PULSES
R
TH
R1
Rise TIme: 1 V/ns Fall Time: 1 V/ns
Parameters 3.0V 3.3V Unit
R1 1.105 1.216 ΚΩ
R2 1.550 1.374 ΚΩ
RTH 0.645 0.645 ΚΩ
VTH 1.75 1.75 V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions Min. Typ.[2] Max. Unit
VDR VCC for Data Retention 1.5 V
ICCDR Data Retention Current VCC = 1.5V, CE1> VCC – 0.2V or
CE2< 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V
Auto-A 4 20 µA
Auto-E 460µA
tCDR[8] Chip Deselect to Data
Retention Time 0ns
tR[8] Operation Recovery Time tRC ns
Data Retention Waveform[9]
Notes:
8. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) >100 µs.
9. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE.
V
CC(min.)
V
CC(min.)
t
CDR
V
DR
>1.5 V
DATA RETENTION MODE
t
R
CE
1
or
V
CC
BHE.BLE
CE
2
or
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 6 of 13
Switching Characteristics Over the Operating Range [10]
Parameter Description
70 ns
UnitMin. Max.
Read Cycle
tRC Read Cycle Time 70 ns
tAA Address to Data Valid 70 ns
tOHA Data Hold from Address Change 10 ns
tACE CE1 LOW and CE2 HIGH to Data Valid 70 ns
tDOE OE LOW to Data Valid 35 ns
tLZOE OE LOW to Low-Z[11] 5ns
tHZOE OE HIGH to High-Z[11, 12] 25 ns
tLZCE CE1 LOW and CE2 HIGH to Low-Z[11] 10 ns
tHZCE CE1 HIGH or CE2 LOW to High-Z[11, 12] 25 ns
tPU CE1 LOW and CE2 HIGH to Power-up 0 ns
tPD CE1 HIGH or CE2 LOW to Power-down 70 ns
tDBE BHE/BLE LOW to Data Valid 70 ns
tLZBE[11] BHE/BLE LOW to Low-Z[13] 5ns
tHZBE BHE/BLE HIGH to High-Z[11, 12] 25 ns
Write Cycle[14]
tWC Write Cycle Time 70 ns
tSCE CE1 LOW and CE2 HIGH to Write End 60 ns
tAW Address Set-up to Write End 60 ns
tHA Address Hold from Write End 0 ns
tSA Address Set-up to Write Start 0 ns
tPWE WE Pulse Width 50 ns
tBW BHE/BLE Pulse Width 60 ns
tSD Data Set-up to Write End 30 ns
tHD Data Hold from Write End 0 ns
tHZWE WE LOW to High-Z[11, 12] 25 ns
tLZWE WE HIGH to Low-Z[11] 5ns
Notes:
10.Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the
specified IOL/IOH and 30-pF load capacitance.
11.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any
given device.
12.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
13.When both byte enables are toggled together this value is 10 ns.
14.The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. All signals must be ACTIVE to initiate a
Write and any of these signals can terminate a Write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal
that terminates the Write.
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 7 of 13
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[15, 16]
Read Cycle No. 2 (OE Controlled)[16, 17]
Notes:
15.Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH.
16.WE is HIGH for Read cycle.
17.Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2transition HIGH.
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE1
ICC
ISB
IMPEDANCE
ADDRESS
CE2
DATA OUT
VCC
SUPPLY
CURRENT
BHE/BLE
tLZBE
tHZBE
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 8 of 13
Write Cycle No. 1 (WE Controlled)[14, 18, 19]
Notes:
18.Data I/O is high-impedance if OE = VIH.
19.If CE1goes HIGH or CE2goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
20.During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 20
BHE/BLE tBW
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 9 of 13
Write Cycle No. 2 (CE1or CE2Controlled) [14, 18, 19]
Write Cycle No. 3 (WE Controlled, OE LOW)[19]
Switching Waveforms (continued)
tHD
tSD
tPWE
tHA tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE1
ADDRESS
CE2
WE
DATA I/O
OE
NOTE 20
BHE/BLE tBW
tSA
DATAIN VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
CE1
ADDRESS
CE2
WE
DATAI/O NOTE 20
tBW
BHE/BLE
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CY62157CV30/33
Document #: 38-05014 Rev. *F Page 10 of 13
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
Truth Table
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X X High Z Deselect/Power-Down Standby (ISB)
X L X X X X High Z Deselect/Power-Down Standby (ISB)
X X X X H H High Z Deselect/Power-Down Standby (ISB)
L H H L L L Data Out (I/OO–I/O15) Read Active (ICC)
L H H L H L Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z Read Active (ICC)
L H H L L H Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z Read Active (ICC)
L H H H L L High Z Output Disabled Active (ICC)
L H H H H L High Z Output Disabled Active (ICC)
L H H H L H High Z Output Disabled Active (ICC)
L H L X L L Data In (I/OO–I/O15) Write Active (ICC)
L H L X H L Data In (I/OO–I/O7);
I/O8–I/O15 in High Z Write Active (ICC)
L H L X L H Data In (I/O8–I/O15);
I/O0–I/O7 in High Z Write Active (ICC)
Switching Waveforms (continued)
DATA I/O
ADDRESS
t
HD
t
SD
t
SA
t
HA
t
AW
tWC
CE1
WE
DATA
IN
VALID
NOTE 20
t
BW
BHE/BLE
tSCE
CE2
t
PWE
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