Cypress CapSense CY8CMBR2010 Guide

AN75999
CY8CMBR2010 CapSense®Design Guide
Doc. No. 001-75999 Rev. *E
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
http://www.cypress.com

Copyrights
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 2
© Cypress Semiconductor Corporation, 2012–2017. This document is the property of Cypress Semiconductor Corporation and
its subsidiaries, including Spansion LLC (―Cypress‖). This document, including any software or firmware included or
referenced in this document (―Software‖), is owned by Cypress under the intellectual property laws and treaties of the United
States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as
specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with
Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable
license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code
form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your
organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through
resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents
that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software
solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without
further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in
this document. Any information provided in this document, including any sample design information or programming code, is
provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test
the functionality and safety of any application made of this information and any resulting product. Cypress products are not
designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems
(including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other
uses where the failure of the device or system could cause personal injury, death, or property damage (―Unintended Uses‖). A
critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the
failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall
and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of
Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-
RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more
complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their
respective owners.

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 3
Contents
1. Introduction....................................................................................................................................................................5
1.1 Abstract .................................................................................................................................................................5
1.2 Cypress’s CapSense Documentation Ecosystem..................................................................................................5
1.3 CY8CMBR2010 CapSense®Express Device Features.........................................................................................7
1.4 Document Conventions .........................................................................................................................................8
2. CapSense Technology..................................................................................................................................................9
2.1 CapSense Fundamentals......................................................................................................................................9
2.2 Capacitive Sensing Method.................................................................................................................................11
2.2.1 CapSense Sigma-Delta (CSD) ...............................................................................................................11
2.3 SmartSense Auto-Tuning ....................................................................................................................................12
2.3.1 Process Variation....................................................................................................................................12
2.3.2 Reduced Design Cycle Time ..................................................................................................................12
3. CapSense Schematic Design .....................................................................................................................................13
3.1 CY8CMBR2010 CapSense Controller Pins.........................................................................................................13
3.1.1 CapSense Buttons (CSx Pins)................................................................................................................13
3.1.2 General Purpose Outputs (GPOx Pins)..................................................................................................13
3.1.3 Modulation Capacitor (CMOD Pin) .........................................................................................................13
3.1.4 Button Auto Reset (ARST/EMC Pin).......................................................................................................14
3.1.5 Noise Immunity (ARST/EMC Pin)...........................................................................................................14
3.1.6 Toggle ON/OFF (Toggle/FSS Pin)..........................................................................................................14
3.1.7 Flanking Sensor Suppression (Toggle/FSS Pin).....................................................................................15
3.1.8 LED ON Time (Delay Pin).......................................................................................................................15
3.1.9 Power-On LED Effects (LEDFading Pin) ................................................................................................16
3.1.10 Analog Voltage Support (LEDFading Pin)...............................................................................................18
3.1.11 Backlighting (Backlighting Pin)................................................................................................................19
3.1.12 CS0 Sensitivity (CS0Sensitivity Pin).......................................................................................................19
3.1.13 CS0 Debounce (CS0Sensitivity Pin).......................................................................................................20
3.1.14 System Diagnostics ................................................................................................................................20
3.1.15 Button Scan Rate (ScanRate/Sleep Pin) ................................................................................................22
3.1.16 Sleep Modes (ScanRate/Sleep Pin) .......................................................................................................23
3.1.17 Serial Debug Data Out (Delay Pin).........................................................................................................23
3.2 Design Toolbox....................................................................................................................................................28
3.2.1 General Layout Guidelines .....................................................................................................................28
3.2.2 Layout Estimator.....................................................................................................................................29
3.2.3 CP, Power Consumption, and Response Time Calculator ......................................................................30
3.2.4 Design Validation....................................................................................................................................31

Contents
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 4
4. Electrical and Mechanical Design Considerations...................................................................................................33
4.1 Overlay Selection.................................................................................................................................................33
4.1.1 Bonding Overlay to PCB.........................................................................................................................34
4.2 ESD Protection....................................................................................................................................................34
4.2.1 Prevent ...................................................................................................................................................34
4.2.2 Redirect ..................................................................................................................................................34
4.2.3 Clamp .....................................................................................................................................................34
4.3 Electromagnetic Compatibility (EMC) Considerations .........................................................................................35
4.3.1 Radiated Interference .............................................................................................................................35
4.3.2 Conducted Immunity and Emissions.......................................................................................................35
4.4 PCB Layout Guidelines........................................................................................................................................35
5. Low-Power Design Considerations............................................................................................................................36
5.1 System Design Recommendations......................................................................................................................36
5.2 Calculating Average Power .................................................................................................................................36
5.2.1 Button Scan Rate (TR) ............................................................................................................................36
5.2.2 Scan Time (TS) .......................................................................................................................................37
5.2.3 Average Current in NO TOUCH State (IAVE_NT).......................................................................................38
5.2.4 Average Current in TOUCH State (IAVE_T)...............................................................................................38
5.2.5 Average Use Current (IAVE_U)..................................................................................................................38
5.2.6 Average Current (IAVE) ............................................................................................................................38
5.2.7 Average Power (PAVE).............................................................................................................................39
5.2.8 Example Calculation...............................................................................................................................39
5.3 Sleep Modes........................................................................................................................................................40
5.3.1 Low-Power Sleep Mode..........................................................................................................................40
5.3.2 Deep Sleep Mode...................................................................................................................................40
6. Resources ....................................................................................................................................................................41
6.1 Website................................................................................................................................................................41
6.2 Datasheet............................................................................................................................................................41
6.3 Design Toolbox....................................................................................................................................................41
6.4 Design Support....................................................................................................................................................41
A. Appendix ......................................................................................................................................................................42
A.1 Schematic Example.............................................................................................................................................42
A.1.1 Schematic 1: Ten Buttons and Ten GPOs..............................................................................................42
A.1.2 Schematic 2: Eight Buttons and Eight GPOs..........................................................................................44
A.2 Acronyms.............................................................................................................................................................45
Glossary................................................................................................................................................................................46
Revision History...................................................................................................................................................................51

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 5
1. Introduction
1.1 Abstract
This document describes how to implement capacitive sensing functionality using Cypress’s CapSense®Express™
CY8CMBR2010 device. The following topics are covered in this guide:
Features of the CY8CMBR2010
CapSense principles of operation
Configuration options of the CY8CMBR2010 device
Using the Design Toolbox with the CY8CMBR2010
System electrical and mechanical design considerations for the CY8CMBR2010
Low-power design considerations for the CY8CMBR2010
Additional resources and support for designing CapSense into your system
1.2 Cypress’s CapSense Documentation Ecosystem
Figure 1-1 and Table 1-1 summarize the CapSense documentation ecosystem. These resources allow the implementers to
quickly access the information needed to complete a CapSense product design. Figure 1-1 shows a typical product design
cycle with capacitive sensing; this document covers the topics highlighted in green. Table 1-1 offers links to the supporting
documents for each of the numbered tasks in Figure 1-1.

Introduction
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 6
Figure 1-1. Typical CapSense Product Design Flow

Introduction
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 7
Table 1-1. Cypress Documents Supporting Numbered Design Tasks of Figure 1-1
Numbered Design Task of
Figure 1-1
Supporting Cypress CapSense Documentation
1
Getting Started with CapSense
2
CY8CMBR2010 Device Datasheet
3
Getting Started with CapSense
4
This document
5
This document
6
Not applicable for CY8CMBR2010
7
Not applicable for CY8CMBR2010
8
Not applicable for CY8CMBR2010
9
Not applicable for CY8CMBR2010
10
This document
11
This document
1.3 CY8CMBR2010 CapSense®Express Device Features
Cypress’s low-power CapSense controller can easily add capacitive touch sensing to your user interface. The device’s
features include:
Hardware Configurable CapSense Controller
Does not require software tools or programming
Ten button solution configurable through hardware straps
Ten general-purpose outputs (GPOs)
GPOs are linked to CapSense buttons
GPOs support direct LED drive
SmartSense™ Auto-Tuning
Maintains optimal button performance even in noisy environment
CapSense parameters dynamically set in runtime
Saves time and effort in device tuning
Wide parasitic capacitance (CP) range (5—40 pF)
Advanced Features
Robust sensing with closely spaced buttons –Flanking Sensor Suppression (FSS)
User-configurable LED Effects
oOn-system power-on
oLED ON Time after button release
Analog voltage output
oUsing external resistor bridge
Serial debug data output
oSimplifies production-line testing and system debug

Introduction
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 8
Noise Immunity
Specifically designed for superior noise immunity to external radiated and conducted noise
Low radiated noise emission
System Diagnostics
Button shorts
Improper value of modulating capacitor (CMOD)
Parasitic capacitance (CP) value out of range
Wide operating voltage range
1.71—5.5 V
Ideal for both regulated and unregulated battery applications
Low power consumption
Average current consumption of 21 µA[1] per button
Deep sleep current: 100 nA
Industrial temperature range: –40 °C to +85 °C.
32-pin QFN package (5 mm x 5 mm x 0.6 mm)
1.4 Document Conventions
Convention
Usage
Courier New
Displays file locations, user entered text, and source code:
C:\ ...cd\icc\
Italics
Displays file names and reference documentation:
Read about the sourcefile.hex file in the PSoC Designer User Guide.
[Bracketed, Bold]
Displays keyboard commands in procedures:
[Enter] or [Ctrl] [C]
File > Open
Represents menu paths:
File > Open > New Project
Bold
Displays commands, menu paths, and icon names in procedures:
Click the File icon and then click Open.
Times New Roman
Displays an equation:
2 + 2 = 4
Text in gray boxes
Describes Cautions or unique functionality of the product.
1Four buttons used, 3% touch time, 10 pF < (Cp of all buttons) < 20 pF, Button Scan Rate = 556 ms, power consumption optimized, Noise
Immunity level "Normal", CS0 sensitivity "High"

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 9
2. CapSense Technology
2.1 CapSense Fundamentals
CapSense is a touch sensing technology that works by measuring the capacitance of each sensor input pin on the CapSense
controller. The total capacitance on each of the sensor pins can be modeled as equivalent lumped capacitors with values of
CX,1 through CX,n as shown in Figure 2-1. Circuitry internal to the CY8CMBR2010 device converts the magnitude of each CX
into a digital code that is stored for post-processing. A modulating capacitor, CMOD, is used by the CapSense controller’s
internal circuitry. CMOD is discussed in more detail in Capacitive Sensing Method.
Figure 2-1. CapSense Implementation in a CY8CMBR2010 Device
Each sensor input pin is connected to a sensor pad by traces, vias, or both, as necessary. A nonconductive overlay is required
to cover the sensor pad and constitutes the product’s touch interface. When a finger comes into contact with the overlay, the
conductivity and mass of the body effectively introduces a grounded conductive plane parallel to the sensor pad. This action is
represented in Figure 2-2. This arrangement constitutes a parallel plate capacitor, whose capacitance is given by Equation 1:
=0
Equation 1
Where:
CF= The capacitance affected by a finger in contact with the overlay over a sensor
ε0= Free space permittivity
εr= Dielectric constant (relative permittivity) of overlay
A = Area of finger and sensor pad overlap
D = Overlay thickness
CY
8
CMBR
2010
C
MOD
Sensor
Capacitors
C
X
,
1
C
X
,
2
C
X
,
n

CapSense Technology
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 10
Figure 2-2. Section of Typical CapSense PCB with the Sensor Being Activated by a Finger
In addition to the parallel plate capacitance, a finger in contact with the overlay causes electric field fringing between itself and
other conductors in the immediate vicinity. Typically, the effect of these fringing fields is minor, and it can usually be ignored.
Even without a finger touching the overlay, the sensor input pin has some parasitic capacitance (CP). CPresults from the
combination of the CapSense controller internal parasitic and electric field coupling among the sensor pad, traces, and vias,
and other conductors in the system, such as ground plane, other traces, any metal in the product’s chassis or enclosure, and
so on. The CapSense controller measures the total capacitance (CX) connected to a sensor pin.
When a finger is not touching a sensor:
= Equation 2
With a finger on the sensor, CXequals the sum of CPand CF:
=+Equation 3
In general, CPis an order of magnitude greater than CF. CPusually ranges from 10—20 pF, but in extreme cases it can be as
high as 40 pF. CFusually ranges from 0.1—0.4 pF.

CapSense Technology
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 11
2.2 Capacitive Sensing Method
CY8CMBR2010 device supports the CapSense Sigma Delta (CSD) with SmartSense Auto-Tuning for converting sensor
capacitance (CX) into digital counts. The CSD method is described in the following sections.
2.2.1 CapSense Sigma-Delta (CSD)
The CSD method in the CY8CMBR2010 device incorporates CX into a switched capacitor circuit, as shown in Figure 2-3. CXis
alternatively connected to Gnd and the AMUX bus by the non-overlapping switches Sw1 and Sw2. Sw1 and Sw2 are driven by
the Precharge clock to bleed a current, isensor from the AMUX bus. The magnitude of isensor is directly proportional to the
magnitude of CX. The sigma-delta converter samples the AMUX bus voltage and generates a modulating bit stream that
controls the constant current source, IDAC. The IDAC charges AMUX such that the average AMUX bus voltage is maintained
at Vref. The sensor bleeds off the charge isensor from Cmod which, in combination with Rbus, forms a low-pass filter that
attenuates precharge switching transients at the sigma-delta converter input.
Figure 2-3. CSD Block Diagram
Cx isensor
Sigma-Delta
Converter
Precharge
Clock
Cmod
High-Z
input
Sw1
Sw2
CY8CMBR2010
Gnd
= External Connection
AMUX
Bus
Vref
Rbus
Gnd
IDAC
In order to maintain the AMUX bus voltage at Vref, the sigma-delta converter matches IDAC to isensor by controlling the bit
stream duty cycle. The sigma-delta converter stores the bit stream over the duration of a sensor scan, and the accumulated
result is a digital output, raw count, which is directly proportional to CX. This raw count is interpreted by high-level algorithms to
resolve the sensor state. Figure 2-4 plots the CSD raw counts from a number of consecutive scans during which the sensor is
touched and then released by a finger. As explained in CapSense Technology, the finger touch causes CX to increase by CF,
which in turn causes raw counts to increase proportionally. By comparing the shift in steady state raw count level to a
predetermined threshold, the high-level algorithms can determine whether the sensor is in an ON (Touch) or OFF (No Touch)
state. To learn more about Raw Counts, Finger Threshold, and Signal-to-Noise Ratio (SNR), refer to Getting Started with
CapSense.
Figure 2-4. CSD Raw Counts During a Finger Touch

CapSense Technology
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 12
2.3 SmartSense Auto-Tuning
Tuning the touch-sensing user interface is critical for proper system operation and a pleasant user experience. Unfortunately,
tuning is time-consuming because it is an iterative process. In a typical development cycle, the interface is tuned in the initial
design phase, during system integration, and before production ramp. SmartSense Auto-Tuning was developed to simplify the
user interface development cycle. It is easy to use and reduces design cycle time by eliminating manual tuning during the
prototype and manufacturing stages. SmartSense Auto-Tuning tunes each CapSense button automatically at power up and
maintains optimum button performance during runtime. SmartSense Auto-Tuning adapts for manufacturing variation in PCBs
and overlays and automatically tunes out noise from sources such as LCD inverters, AC lines, and switch-mode power
supplies.
2.3.1 Process Variation
The CY8CMBR2010 device’s SmartSense Auto-Tuning is designed to work with CPvalues in the range of 5—40 pF. The
sensitivity parameter for each button is set automatically, based on its characteristics. This parameter improves yield in mass
production because every button maintains a consistent response regardless of CPvariation between the buttons. CPcan vary
due to PCB layout and trace length, PCB manufacturing process variation, or vendor-to-vendor PCB variation within a multi-
sourced supply chain. The sensitivity of a button depends on CP; higher CPvalues decrease sensitivity, resulting in decreased
finger touch signal amplitude. A change in CPcan result in a button becoming too sensitive, not sensitive enough, or non-
operational. When this happens, you must retune the system and, in some cases, re-qualify the user interface subsystem.
SmartSense Auto-Tuning resolves these issues.
SmartSense Auto-Tuning makes platform designs possible. For example, consider the capacitive touch sensing multimedia
keys on a laptop computer. The parasitic capacitance of the CapSense buttons can vary in different models of the same
platform design depending on the size of the laptop and the keyboard layout. In this example, a wide-screen laptop model
would have larger spaces between the buttons than a standard-screen model. Therefore, a wide-screen model would have
longer traces between each button and the CapSense controller, which would result in higher CPvalues. Though the buttons’
functionality is identical for all of the laptop models, the buttons must be tuned for each model. SmartSense Auto-Tuning lets
you do platform designs using the recommended practices shown in the PCB Layout in Getting Started with CapSense.
Figure 2-5. Design of Laptop Multimedia Keys for a 21-Inch Model
Figure 2-6. Design of Laptop Multimedia Keys for a 15-Inch Model with Identical Functionality and Button Size
2.3.2 Reduced Design Cycle Time
When you design a capacitive button interface, the most time-consuming tasks are firmware development, layout, and button
tuning. With a typical touch-sensing controller, the button must be retuned when the same design is ported to different models
or when the mechanical dimensions change in the PCB or the button PCB layout. A design with SmartSense Auto-Tuning
meets these challenges because it does not require firmware development, manual tuning, or retuning. In addition,
SmartSense Auto-Tuning speeds up a typical design cycle. Figure 2-7 compares the design cycles of a typical touch-sensing
controller and a SmartSense Auto-Tuning-based design.
Figure 2-7. Typical Capacitive Interface Design Cycle Comparison
Feasibility
Study Schematics
Design PCB Layout Design
Mechanical Design Review
System
Integration
Retuning for any
changes Tuning process
Production Fine
Tuning Design Validation Production
Typical capacitive user interface Design Cycle
Firmware
Development Feasibility Study
Schematics
Design PCB Layout Design
Mechanical Design Review
System
Integration
Design
Validation Production
CapSense® Express with SmartSense™ Auto-Tuning based
capacitive user interface Design Cycle
Device
Configuration

CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 13
3. CapSense Schematic Design
Cypress’s CY8CMBR2010 is hardware-configurable. This section gives an overview of the CapSense controller pins and how
to configure them.
3.1 CY8CMBR2010 CapSense Controller Pins
Figure 3-1. CY8CMBR2010 Pin Diagram
CY8CMBR2010
QFN
(Top View)
9
10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28 27 26
25
CS 0
CS 1
CS 2 CS 3
CS 4
CS 5
CS 6
CS 7
CS 8
CS 9
GPO 0
GPO 1
GPO 2
GPO 4
GPO 5
GPO 6
GPO 7
GPO 8
GPO 9
CMOD
XRES
VSS
Backlighting
LEDFading
CS0Sensitivity
Delay
ARST/EMC
Toggle/FSS
ScanRate/Sleep
VSS
VDD
GPO 3
3.1.1 CapSense Buttons (CSx Pins)
The CY8CMBR2010 controller has ten capacitive sense inputs, CS0—CS9. Each capacitive button requires a connection to
one of the capacitive sense inputs. You must ground all unused CapSense (CSx) input pins.
3.1.2 General Purpose Outputs (GPOx Pins)
There are ten active low outputs on the CY8CMBR2010 controller, GPO0—GPO9. Each output is driven by its corresponding
capacitive sensing input, CSx. You can use GPOs to directly drive LEDs or replace mechanical switches. GPOs are in strong
drive2mode. All unused GPO pins must be floated.
3.1.3 Modulation Capacitor (CMOD Pin)
Connect a 2.2-nF (±10%) capacitor to the CMOD pin.
2When a pin is in strong drive mode, it is pulled up to VDD when the output is HIGH and pulled down to Ground when the output is LOW.

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 14
3.1.4 Button Auto Reset (ARST/EMC Pin)
Button Auto Reset determines the maximum time a button is considered to be ON when CSx is continuously touched. The
button is turned OFF after the ARST period. This feature prevents a button from getting stuck if a metal object is placed too
close to it. The Button Auto Reset period is defined in Table 3-1 and shown in Figure 3-2.
Table 3-1. ARST/EMC Pin Configuration
ARST/EMC Pin Connection
Button Auto Reset Period
(seconds)
Noise Immunity
Level
Ground / Floating[3]
No Limit
Normal
1.5 kΩ(±5%) resistor to ground
20
Normal
5.1 kΩ(±5%) resistor to ground
No Limit
High
VDD
20
High
Figure 3-2. Button Auto Reset
CS0
GPO0
Auto Reset period
GPO0 not driven as CS0
is considered to be OFF
Button is touched for more
than the Auto Reset period
After the CSx is turned off because of Button Auto Reset and after the button is released, do not touch CSx for a specific
amount of time (T), where:
T = 550 ms if CSx is released within 15 seconds of the Auto Reset period elapsing
T = 550 ms + (Scan Rate) if CSx is released after 15 seconds after the Auto Reset period elapsed
3.1.5 Noise Immunity (ARST/EMC Pin)
This setting determines the device’s immunity to external radiated and conducted noise such as audio frequency noise from
power amplifiers, radio frequency noise from wireless transmitters, ESD, and power line surges.
In a system without major noise concerns, select ―Normal‖ Noise Immunity. For a system in a high-noise environment, select
―High‖ Noise Immunity. Power consumption and response time increase when Noise Immunity is ―High‖. Noise Immunity
configuration is defined in Table 3-1.
3.1.6 Toggle ON/OFF (Toggle/FSS Pin)
When Toggle ON/OFF is enabled, the state of GPOx changes on every rising edge of CSx. Toggle ON/OFF configuration is
defined in Table 3-2 and shown in Figure 3-3.
Table 3-2. Toggle/FSS Pin Configuration
Toggle/FSS Pin Connection
Toggle ON/OFF
FSS
Ground / Floating[3]
Disabled
Disabled
1.5 kΩ (±5%) resistor to ground
Enabled
Disabled
5.1 kΩ (±5%) resistor to ground
Disabled
Enabled
VDD
Enabled
Enabled
3Floating is not recommended in high noise environment, except for LEDFading pin.

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 15
Figure 3-3. Example of Toggle ON/OFF Feature
CS0
GPO0
3.1.7 Flanking Sensor Suppression (Toggle/FSS Pin)
FSS allows only one CSx to be in the TOUCH state at a time. This means you can distinguish TOUCH states for closely
spaced buttons. If a finger contacts multiple CSx buttons, only the first one to sense a TOUCH state will turn ON.
FSS also is useful when nearby buttons can produce opposite effects such as an interface with two buttons for brightness
control (UP or DOWN).
FSS configuration is defined in Table 3-2 and shown in Figure 3-4 and Figure 3-5.
Figure 3-4. FSS When Only One Button is Touched
CS0 CS1 CS2 CS3 CS0 CS1 CS2 CS3
Figure 3-5. FSS When Multiple Buttons are Touched With One Button ON Previously
3.1.8 LED ON Time (Delay Pin)
LED ON Time specifies the duration for which GPOx is driven low after CSx is released as shown in Figure 3-6. LED ON Time
can range from 0—2000 ms, with a resolution of 20 ms.
Figure 3-6. LED ON Time
CS0
GPO0
Start LED ON
Time Counter
Reset LED ON
Time Counter
LED ON Time
LED ON Time, D, is configured by connecting a resistor, RDELAY, between the Delay pin and ground.
Equation 4
 =󰇡D
20 × 30󰇢+ 300 if Serial Debug Data Out disabled
 =󰇡D
20 × 30󰇢+ 7000 if Serial Debug Data Out enabled
Where D is a multiple of 20 ms
CS1 is reported as ON upon touch
No button is ON prior to the touch
CS1 is touched; reported ON
CS2 also touched along with CS1; only
CS1 is reported ON

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 16
Table 3-3 provides some example values for RDELAY. Resistor tolerance RDELAY should be less than 1 percent.
Table 3-3. Delay Pin Configuration
Delay Pin Connection
Approx. LED ON Time
(ms)
Serial Debug Data
Ground / 300 Ω(±1%) resistor to ground
0
Disabled
330 Ω(±1%) resistor to ground
20
360 Ω(±1%) resistor to ground
40
390 Ω(±1%) resistor to ground
60
…
…
3300 Ω(±1%) resistor to ground
2000
7000 Ω(±1%) resistor to ground
0
Enabled
7030 Ω(±1%) resistor to ground
20
7060 Ω(±1%) resistor to ground
40
7090 Ω(±1%) resistor to ground
60
…
…
10000 Ω(±1%) resistor to ground
2000
LED ON Time varies from device to device. Accuracy is ±25% at a range of -40 °C to +85 °C (excluding resistor tolerance).
If a Button Auto Reset (ARST/EMC Pin) is triggered for CSx, LED ON Time is not applied on GPOx. LED ON Time is disabled
if Toggle ON/OFF is enabled.
LED ON Time applies only to one GPOx at a time, meaning the LED ON Time counter resets every time a CSx transitions to a
NO TOUCH state. Figure 3-7 illustrates how LED ON Time operates when multiple buttons are touched. CS1 resets the LED
ON Time counter, causing GPO0 to turn OFF prematurely.
Figure 3-7. LED ON Timing for Multiple Buttons
CS0
GPO0
CS1
GPO1
Start LED ON Time
Counter
Restart LED ON
Time Counter
Reset LED ON
Time Counter
LED ON Time
3.1.9 Power-On LED Effects (LEDFading Pin)
If this feature is enabled, all LEDs connected to GPOs show one of three selectable brightening and fading effects for an initial
time, at system power-on. All CapSense buttons are disabled during this time. The device responds to any button touch only
after the effects are complete.
Power-On LED Effects use the following parameters:
Low-brightness: Minimum LED intensity
Low-brightness time: The time period the LED remains in a low-brightness state
Ramp-up time: The time period the LED transitions from low-brightness to high-brightness
High-brightness: Maximum LED intensity

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 17
High-brightness time: The time period the LED remains in a high-brightness state
Ramp-down time: The time period the LED transitions from high-brightness to low-brightness
Repeat rate: The number of times the effects are repeated
Power-On LED Effect 1: All LEDs go to high brightness and return to low brightness simultaneously one time as shown in
Figure 3-8.
Figure 3-8. Power-on LED Effect 1
LED
Brightness
100%
0%
1000
ms
400
ms
1000
ms
400
ms
Power on
350 ms/
1000 ms
Normal
Operation
Effects
completed
0%
Ramp Up
Ramp Down
3150 ms / 3800 ms
Power-On LED Effect 2: All LEDs go to high brightness and return to low brightness simultaneously two times as shown in
Figure 3-9.
Figure 3-9. Power-on LED Effect 2
LED
Brightness
100%
Ramp Up
Ramp Down
0%
500
ms
200
ms
500
ms
200
ms
Power on
350 ms/
1000 ms
100%
Ramp Down
0%
500
ms
200
ms
500
ms
200
ms
Ramp Up
Normal
Operation
Effects
completed
0%
3150 ms / 3800 ms

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 18
Power-On LED Effect 3: All LEDs go to high brightness and return to low brightness sequentially one time as shown in
Figure 3-10.
Figure 3-10. Power-on LED Effect 3 with Two Button Design
GPO0 LED
Brightness
Ramp Up
Ramp Down
300
ms
300
ms
Power on
350ms/
1000 ms
Normal
Operation
Effects
completed
Ramp Down
Ramp Up
GPO1 LED
Brightness
300
ms
300
ms
1550 ms / 2200 ms
0% 0%
0%
100%
100%
Power-on LED effects are configured using the LEDFading pin as shown in Table 3-4.
Table 3-4. LEDFading Pin Configuration
LEDFading Pin Connection
Power-on LED Effects
Analog Voltage Support
LED Backlighting
Ground
Disabled
Enabled
1.5 kΩ(±5%) resistor to ground
Effect 1
Disabled
5.1 kΩ(±5%) resistor to ground
Effect 2
Disabled
VDD
Effect 3
Disabled
Floating
Disabled
Disabled
The effects are seen after the device initialization time from power-on. This time is less than 350 ms if Noise Immunity is
―Normal‖ and less than 1000 ms if Noise Immunity is ―High‖.
After power-on, system diagnostics, including a Power-on Self Test are performed. If any CapSense button fails, the effects
are not seen on the corresponding GPO. To learn more about this test, see System Diagnostics.
3.1.10 Analog Voltage Support (LEDFading Pin)
A general external resistive network with a host processor, such as the one shown in Figure 3-11, can configure the host to
perform different functions based on the voltage level seen at the input pin. Vary this voltage level by using a combination of
resistors and switches between VDD and ground.

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 19
Figure 3-11. A General External Resistive Network
Host Processor
VDD
VDD
R1
R2
R3
R4
R7R6 R8
R5
Key 1
Key 2
The analog voltage support feature of CY8CMBR2010 gives you the option to control these switches using CapSense buttons.
Each switch can be replaced with one GPOx. When a CSx button is touched, the corresponding GPOx goes low; therefore,
the switch is closed (shorted to ground). When the button is released, the corresponding switch is left open. This is shown in
Figure 3-12.
Figure 3-12. Analog Voltage Support from CY8CMBR2010
Host Processor
VDD
VDD
R1
R2
R3
R4
R7R6 R8
R5
Key 1
Key 2
GPO2 GPO1GPO3GPO4
GPO6 GPO5GPO7GPO8
If this feature is enabled, the GPOs cannot be used simultaneously in the external resistive network and for the LED drive.
Instead, the Backlighting pin acts as a common GPO for LED drive, controlled by all the CSx buttons. If only one button needs
to be ON for analog voltage support, enable FSS along with this feature.
Usually, the GPOs are in strong drive mode. But when this feature is enabled, the GPOs are in Open Drain Low drive mode.
Analog voltage support is configured using the LEDFading pin as shown in Table 3-4.
3.1.11 Backlighting (Backlighting Pin)
When analog voltage support is enabled, the Backlighting pin acts as a common GPO for the LED drive, as the GPOx cannot
be used for LED drive. This pin can be controlled by all CSx inputs.
Backlighting is a strong drive, active low output and it goes low if any button is touched. This pin is disabled if analog voltage
support is disabled.
3.1.12 CS0 Sensitivity (CS0Sensitivity Pin)
The capacitive sense input CS0 can be used for special functions in a design. Unlike other inputs, CS0’s sensitivity and
debounce settings are configurable. For example, if CS0 is being used as the system power button it needs to be less
sensitive to avoid falsely switching the power ON and OFF.

CapSense Schematic Design
CY8CMBR2010 CapSense®Design Guide Doc. No. 001-75999 Rev. *E 20
The configuration for CS0Sensitivity is shown in Table 3-5.
Table 3-5. CS0Sensitivity Pin Configuration
CS0Sensitivity Pin Connection
CS0Sensitivity
CS0 Debounce
Ground / Floating4
High
3
1.5 kΩ (±5%) resistor to ground
High
24
5.1 kΩ (±5%) resistor to ground
High
48
VDD
Low
99
3.1.13 CS0 Debounce (CS0Sensitivity Pin)
Debounce avoids false button triggering from noise spikes or system glitches, by specifying the minimum time a CS0 has to be
touched for a valid touch input. CS0’s debounce time can vary depending on the button’s function. For example, the power
button should have a long debounce time to avoid inadvertently switching the system ON/OFF. Shorter debounce times speed
up the device’s response to a button touch.
Configurable debounce can provide added functionality to the design. For example, a system may reset when a particular
button is touched for a specific time. In such a case, CS0 can be used with the highest debounce value, to provide that
functionality. Such functionalities can be implemented at the user end applications.
The configuration for CS0 Debounce is shown in Table 3-5.
3.1.14 System Diagnostics
A built-in Power-on Self Test (POST) mechanism performs five tests at power-on reset (POR), which can be useful in
production testing. If any button fails, a 5 ms pulse is sent out on the corresponding GPO within 350 ms if Noise Immunity is
―Normal‖ or 1000 ms if Noise Immunity is ―High‖ as shown in Figure 3-13.
Figure 3-13. Example Showing CS0, CS1 Passing the POST and CS2, CS3 Failing
5ms pulse
GPO3
GPO2
GPO1
(High)
GPO0
(High)
5ms pulse
4Floating is not recommended in high noise environment, except for LEDFading pin.