Cypress CYTVII-B-H-8M-176-CPU User manual

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CYTVII-B-H-8M-176-CPU
Evaluation board user guide
Document Number: 002-25907 Rev. *D
Cypress Semiconductor
An Infineon Technologies Company
198 Champion Court
San Jose, CA 95134-1709
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CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 2
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CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 3
Contents
1. Introduction 4
1.1 Precautions and warnings ...........................................................................................4
2. Overview 5
2.1 Functional overview .....................................................................................................7
3. Operation 15
4. Connections and settings 17
4.1 Evaluation board connections....................................................................................17
4.2 Power supply settings................................................................................................23
4.3 External power supply control signal settings............................................................24
4.4 Ethernet settings........................................................................................................24
4.5 Settings.....................................................................................................................25
5. Power management IC (PMIC) 26
5.1 Power management IC (PMIC) module.....................................................................26
A. CPU board schematics 28
B. CPU board component assembly 60
C. Baseboard schematics 63
D. Baseboard component assembly 80
Revision history 83

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 4
1. Introduction
This user guide provides instructions to handle the CYTVII-B-H-8M-176-CPU and CYTVII-B-H-176-SO evaluation boards,
collectively referred to as ‘CPU board’ in this document. This is an evaluation platform for the CYT4BF8C TRAVEO™ T2G
device. The board can be used as a standalone for basic validation or in combination with the CYTVII-B-E-BB TRAVEO™
T2G baseboard (available separately from Infineon). This document assumes that you will work with the combination (CPU
board + baseboard), and provides guidance on how to use the features of the evaluation platform.
1.1 Precautions and warnings
The board is a delicate PCB; make sure that the evaluation board is handled by qualified personnel who are aware of the
capabilities of the board. Handle the board carefully and make sure it is not bent or subjected to stress. Ensure your own
safety arising from electrical hazards and other sources.
The CPU board is shipped with a 12 V DC power adapter. This adapter can be plugged into the AC mains supply anywhere
in the world and is designed to receive 100-240 V AC V @ 50/60 Hz. While powering the board, you must connect only the
power adapter supplied with the evaluation board and not any other part.

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 5
2. Overview
Figure 2-1 shows the CYTVII-B-H-176-SO board. Insert a TRAVEO™ T2G device into the IC socket (highlighted in red) while
the evaluation board is powered OFF.
Figure 2-1. CYTVII-B-H-176-SO board

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 6
Overview
A variant of the CPU board (CYTVII-B-H-8M-176-CPU) is also available, where the TRAVEO™ T2G device is soldered
directly onto the PCB. Functionally, the CYTVII-B-H-8M-176-CPU and CYTVII-B-H-176-SO boards are identical, except that
the device can be easily replaced in the latter.
For CYTVII-B-H-176-SO kit open the four screws with a screwdriver, insert the device. Make sure that the device pin number
1 mark is facing the white arrow on the PCB, which is near C21. After inserting the device close the socket cover, tighten the
screws. Make sure that the three holes on the socket cover are aligned as shown in Figure 2-1 for the proper working of the
device.
The CPU board is meant to be used along with a TRAVEO™ T2G baseboard (CYTVII-B-E-BB). The baseboard brings out all
important interface connections such as CAN, LIN, SPI EEPROM, CXPI, and Flexray, and can be used in conjunction with
several CPU boards of the TRAVEO™ T2G family. Figure 2-2 shows the baseboard.
Figure 2-2. TRAVEO™ T2G baseboard (CYTVII-B-E-BB)

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 7
Overview
Two Samtec connectors on the CPU board and corresponding mating connectors on the baseboard are used to connect sig-
nals across the two boards. When put together, the boards appear as shown in Figure 2-3.
Figure 2-3. Combination of CPU board and TRAVEO™ T2G baseboard
2.1 Functional overview
The CPU board has the following components:
1. One TRAVEO™ T2G device, either soldered or mounted on a socket (U3)
2. PMIC to generate the 5-V, 3.3-V, and 1.1-V output, which powers the CPU board and the baseboard (if connected)
3. Programming interface (Arm® Standard JTAG, Cortex® Debug, Cortex® Debug + ETM and Arm® ETM Mictor) to connect
several programming tools such as IAR I-jet, Green Hills MULTI, also Infineon MiniProg
4. USB-UART interface for terminal logging (J25)
5. Two user switches (SW2 and SW4) and two user LEDs (LED4 and LED5) for standalone operation without the baseboard
6. One hibernate wakeup switch. (SW3)

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 8
Overview
7. Reset controller with manual reset switch (SW5) and voltage supervision
8. Measurement of device current on VCCD using jumper J5, VDDD using jumper J6, VDDIO_1 using jumper J7, VDDIO_2
using jumper J9, and VDDA using jumper J11 respectively
9. Samtec connector interface (J34 and J35) for connecting to the baseboard CYTVII-B-E-BB
10. SMIF connector (J33) so that the SMIF module can be mounted
The TRAVEO™ T2G baseboard has the following components:
1. Six CAN-FD transceivers based on TJA1057GT (Dual connectors P6, P7, P8)
2. Four CAN-FD transceivers based on TJA1145T, with SPI-based transceiver configuration (Dual connectors P9, P10)
3. Six LIN transceivers based on TJA1021T (Dual connectors P3, P4, P5)
4. Two Flexray transceivers based on TJA1081TS (Dual connector P2)
5. One CXPI transceiver based on S6BT112A01 (Connector P1)
6. One SPI EEPROM 25LC320A (U9)
7. Five user switches (SW1 through SW5), 10 user LEDs (USER_LED0 through USER_LED9), and one potentiometer
(POT1) for analog input
8. Pin headers to access all I/Os of the TRAVEO™ T2G device (when a CPU board is connected to the baseboard)
9. Samtec connector interface (J38 and J84) for connecting to a CPU board

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 9
Overview
2.1.1 Block diagram
Figure 2-4. Block diagram
S6BP501A,
S6BP502A
(PMIC)
Pass Transistor
USB-UART
Traveo II
CYT4BF Series
176-Pin MCU
eMMC
Connector
SMIF
Connector
Debug
Interfaces
I
2
S Audio
Interface
3.5mm
Audio Jack
HyperFlash HyperRAM
Reset
Controller
Dual Quad
SPI Flash
Automotive
Ethernet
D-sub
9 Pin
180 Pin Q SH
Connector (Samtec)
J34
180 Pin QSH
Connector (Samtec)
J35
180 Pin QTH
Connector (Samtec)
J84
180 Pin QTH
Connector (Samtec)
J38
CYTVII-B-H-8M-176pin CPU Board Traveo II
Base Board

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 10
Overview
2.1.2 USB connector
Figure 2-5. USB connector

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 11
Overview
2.1.3 Ethernet connector
Figure 2-6. Ethernet connector

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 12
Overview
2.1.4 SMIF connector
Figure 2-7. SMIF connector

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 13
Overview
2.1.5 eMMC connector
Figure 2-8. eMMC connector

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 14
Overview
2.1.6 Audio connector
Figure 2-9. Audio Connector

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 15
3. Operation
This section describes the operation of the CPU board and the baseboard. It is assumed that you have connected the CPU
board to the baseboard using the Samtec interface and inserted a TRAVEO™ T2G device into the IC socket (applicable to
CYTVII-B-H-176-SO boards only). Follow these steps to operate the CPU board and the baseboard:
1. For the socketed CPU board, ensure that the device is inserted into the socket. Remove the four screws on the socket
using the screwdriver provided in the box and open the socket cover. If the device is not present, place one carefully using
a vacuum picker or a pair of tweezers.
2. Ensure that pin 1 of the device is near the pin 1 marking on the PCB, as shown in Figure 3-1. Also, ensure that the device
is placed in an angle such that the pins on all four sides of the LQFP package match well with the socket pins. Align the
device slightly, if required.
Figure 3-1. Orientation of the device when inserted in the socket
3. Replace the socket cover and fix the four screws so that the socket cover tightly sits on the socket base.
4. A 12 V wall adapter board is supplied along with the CPU board. Connect the 12 V wall adapter to the barrel connector
marked "12V DC" on the CPU board. Connect its plug to a mains socket using one of the four plug adapters provided in
the white box (depending on the geographical location and the socket type available).
5. Ensure that jumpers J45 (default “2-3”), J5, J6, J8, J7, J10, J9, J11 (current measurement jumpers) are inserted on the
CPU board.
6. Turn ON the mains supply to the wall adapter. Turn ON the switch SW1 on the CPU board. The LED labeled PWR should
light up.
7. Connect an appropriate programming tool to one of the programming interfaces (J19, J20, J21, J22). Programming tool
options are:
Arm® ETM MICTOR on J19
Cortex® DEBUG on J20
Arm® Standard JTAG on J21
Cortex® DEBUG and ETM on J22

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 16
Operation
8. Install the appropriate programming integrated design environment (IDE) on a PC. The programming IDE (GHS MULTI,
IAR Embedded Workbench, Cypress Programmer, and so on) should be able to detect a device (read the device ID) and
to load a firmware HEX file (.srec) into the device flash successfully.
As part of the release package, various firmware examples compiled in .srec programming IDEs are available. Some
examples use specific transceivers on the baseboard.
9. To start with, use the LED blink example provided with the release package to test the functioning of the board.
10. Connect a USB-mini cable to J25 and the other end to a PC. Open Tera Term or your preferred terminal logging
application and set the appropriate port and baud rate (typically 115,200 baud, 8, N, 1). Ensure that jumpers J24 and J26
are inserted on the CPU board. Some firmware examples provide data logs from the device or ask for user inputs over the
terminal.

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 17
4. Connections and settings
4.1 Evaluation board connections
4.1.1 Baseboard connections
Make sure that the following jumpers are inserted on the baseboard, so that each transceiver on the baseboard can be used
with the respective firmware example that activate each functionality of the device:
CAN0.0 from the device uses the CAN0 transceiver on the baseboard (connect jumpers J70, J71, J72).
CAN0.1 from the device uses the CAN1 transceiver on the baseboard (connect jumpers J66, J67, J68).
CAN0.2 from the device uses the CAN2 transceiver on the baseboard (connect jumpers J81, J82, J83).
CAN1.0 from the device uses the CAN3 transceiver on the baseboard (connect jumpers J76, J77, J78).
CAN1.1 from the device uses the CAN4 transceiver on the baseboard (connect jumpers J91, J92, J93).
CAN1.2 from the device uses the CAN5 transceiver on the baseboard (connect jumpers J86, J87, J88).
LIN0 from the device uses the LIN0 transceiver on the baseboard (connect jumpers J58, J59, J60, J63).
LIN1 from the device uses the LIN1 transceiver on the baseboard (connect jumpers J51, J52, J53, J56).
LIN2 from the device uses the LIN2 transceiver on the baseboard (connect jumpers J37, J39, J40, J43).
LIN3 from the device uses the LIN3 transceiver on the baseboard (connect jumpers J30, J31, J32, J35).
LIN4 from the device uses the LIN4 transceiver on the baseboard (connect jumpers J22, J23, J24, J27).
LIN5 from the device uses the LIN5 transceiver on the baseboard (connect jumpers J10, J16, J17, J20).
EEPROM on the baseboard is enabled by connecting jumpers J47, J48, J49.
The user switch functionality is enabled by connecting jumper J102.
The potentiometer functionality is enabled by connecting jumper J89.
In addition, power is supplied to the baseboard by connecting jumper J80 to the 3 V or 5 V select jumper pin in the ‘5 V’
position. Make sure that jumper J80 is always connected. Once a specific functionality is chosen by connecting the jumpers
listed above, ensure that the appropriate firmware is loaded onto the device. Incorrect firmware can result in port pins being
configured incorrectly leading to bus contention and damage to hardware. For example, if you connect jumpers related to
CAN0.0, you must ensure that firmware configures the related ports as CAN pins. Contact technical support for firmware
examples.
Apart from these interface transceivers that can be used for specific functions, all pins of the device are also accessible on
the baseboard using pin headers JP1 through JP12.
The device port pins are connected to pin headers on the baseboard as listed in Table 4-1.

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 18
Connections and settings
Table 4-1. Device port pin connections on the baseboard
MCU port pin Connection 1
Signal name of schematics
Connection 1
CPU board
Test point
Connection 1
Base board
Test point
VSSD GND TP2 Not applicable
P0.0 GPIO_P0_0 Not applicable JP12.11
P0.1 GPIO_P0_1 Not applicable JP12.15
P0.2 GPIO_P0_2 Not applicable JP6.17
P0.3 GPIO_P0_3 Not applicable JP12.18
P1.0 BB_SPI0_MISO Not applicable JP3.18
P1.1 BB_SPI0_MOSI Not applicable JP3.16
P1.2 BB_SPI0_CLK Not applicable JP9.17
P1.3 BB_SPI0_SS0 Not applicable JP9.18
P2.0 GPIO_P2_0 R257.1, R258.1 Not applicable
P2.1 GPIO_P2_1 Not applicable JP12.12
P2.2 ETH_RXER TP137 Not applicable
P2.3 GPIO_P2_3 Not applicable JP12.17
P2.4 BB_SPI0_HOLD TP122 JP12.4
P2.5 BB_SPI0_WP TP123 JP2.3
P3.0 ETH_MDIO TP142 Not applicable
P3.1 ETH_MDC TP143 Not applicable
P3.2 USER_LED1 J16.2 Not applicable
P3.3 USER_LED2 J17.2 Not applicable
P3.4 USER_SW1 J13.1 Not applicable
P3.5 USER_SW2 J15.1 Not applicable
VDDD Not applicable TP9 Not applicable
VSSD GND TP2 Not applicable
P4.0 BB_LIN1_RXD TP130 JP6.15
P4.1 BB_LIN1_TXD TP131 JP6.14
P4.2 BB_LIN1_SLP TP132 JP6.3
P4.3 BB_CAN1_TXD TP133 JP6.9
P4.4 BB_CAN1_RXD TP134 JP6.8
P5.0 GPIO_P5_0 Not applicable Not applicable
P5.1 GPIO_P5_1 Not applicable JP12.13
P5.2 GPIO_P5_2 Not applicable JP6.13
P5.3 GPIO_P5_3 Not applicable JP5.18
P5.4 GPIO_P5_4 TP140 JP6.10
P5.5 BB_LIN1_WAKE TP139 JP6.4
P6.0 UART_RX TP185 JP7.3
P6.1 UART_TX TP186 JP7.6
P6.2 EMMC_WP TP277 Not applicable
P6.3 GPIO_P6_3 R197.1, R247.1 Not applicable
P6.4 GPIO_P6_4 R196.1, R221.1 Not applicable
P6.5 GPIO_P6_5 R198.1, R223.1 Not applicable
P6.6 GPIO_P6_6 Not applicable JP10.10
P6.7 GPIO_P6_7 Not applicable JP10.9
VDDD Not applicable TP9 Not applicable

CYTVII-B-H-8M-176-CPU Evaluation Board User Guide, Document Number: 002-25907 Rev. *D 19
Connections and settings
VDDIO_1 Not applicable TP10 Not applicable
VSSD GND TP2 Not applicable
VCCD Not applicable TP8 Not applicable
VCCD Not applicable TP8 Not applicable
P7.0 SPIHB_SEL1 R157.2, R170.1, R189 Not applicable
P7.1 GPIO_P7_1 R199.1, R250.1 Not applicable
P7.2 GPIO_P7_2 R200.1, R252.1 Not applicable
P7.3 GPIO_P7_3 R201.1, R254.1 Not applicable
P7.4 GPIO_P7_4 R202.1, R256.1 Not applicable
P7.5 SPIHB_DATA4 TP279 Not applicable
P7.6 BB_USER_LED0 TP155 JP7.18
P7.7 BB_USER_LED1 Not applicable JP7.10
P8.0 SPIHB_DATA5 TP281 Not applicable
P8.1 SPIHB_DATA6 TP283 Not applicable
P8.2 SPIHB_DATA7 TP282 Not applicable
P8.3 BB_USER_LED2 Not applicable JP7.13
P8.4 BB_USER_LED3 Not applicable JP7.9
P9.0 BB_USER_LED4 Not applicable JP7.14
P9.1 BB_USER_LED5 Not applicable JP7.8
P9.2 BB_USER_LED6 Not applicable JP7.15
P9.3 BB_USER_LED7 Not applicable JP7.7
P10.0 BB_USER_LED8 TP166 JP6.7
P10.1 BB_USER_LED9 TP167 JP6.6
P10.2 BB_FRA_RXD Not applicable Not applicable
P10.3 BB_FRA_TXD Not applicable Not applicable
P10.4 BB_FRA_TXEN Not applicable Not applicable
P10.5 BB_FRB_RXD Not applicable Not applicable
P10.6 BB_FRB_TXD Not applicable Not applicable
P10.7 BB_FRB_TXEN Not applicable Not applicable
P11.0 GPIO_P11_0 Not applicable JP5.16
P11.1 GPIO_P11_1 Not applicable JP5.15
P11.2 BB_FRA_STBN TP266 Not applicable
VREFL VREFL_BB R19.2 JP5.9
VSSA Not applicable R19.1 Not applicable
VDDA Not applicable R18.1 Not applicable
VREFH VREFH_BB R18.2 JP5.10
P12.0 BB_CAN2_TXD Not applicable JP10.8
P12.1 BB_CAN2_RXD Not applicable JP10.7
P12.2 GPIO_P12_2 Not applicable JP10.11
P12.3 GPIO_P12_3 Not applicable JP10.13
P12.4 BB_CAN4_TXD Not applicable JP11.8
P12.5 BB_CAN4_RXD Not applicable JP11.7
P12.6 BB_ADC_POT Not applicable JP7.11
P12.7 GPIO_P12_7 TP184 JP11.4
VDDIO_2 Not applicable TP11 Not applicable
Table 4-1. Device port pin connections on the baseboard (continued)
MCU port pin Connection 1
Signal name of schematics
Connection 1
CPU board
Test point
Connection 1
Base board
Test point