Dynamic Engineering PCIe8LXMCX2CB User manual

DYNAMIC ENGINEERING
150 Dubois St. Suite C, Santa Cruz, CA 95060
831-457-8891 Fax [phone]
http://www.dyneng.com
[email protected]
Est. 1988
User Manual
PCIe8LXMCX2CB
PCIe 8 Lane 2 Position XMC Compatible Carrier
Connector Bus Version
Shown With JN4 full CB, 4 fans installed, AP power connector
Revision A2 9/6/17
Corresponding Hardware: Revision A
Fab number 10-2017-0501

Embedded Solutions Page 2
PCIe8LXMCX2CB
PCIe and XMC Compatible Carrier
Dynamic Engineering
150 Dubois St. Suite C
Santa Cruz, CA 95060
831457-8891
831457-4793 FAX
This document contains information of
proprietary interest to Dynamic Engineering. It
has been supplied in confidence and the
recipient, by accepting this material, agrees that
the subject matter will not be copied or
reproduced, in whole or in part, nor its contents
revealed in any manner or to any person except
to meet the purpose for which it was delivered.
Dynamic Engineering has made every effort to
ensure that this manual is accurate and
complete. Still, the company reserves the right
to make improvements or changes in the
product described in this document at any time
and without notice. Furthermore, Dynamic
Engineering assumes no liability arising out of
the application or use of the device described
herein.
The electronic equipment described herein
generates, uses, and can radiate radio
frequency energy. Operation of this equipment
in a residential area is likely to cause radio
interference, in which case the user, at his own
expense, will be required to take whatever
measures may be required to correct the
interference.
Dynamic Engineering’s products are not
authorized for use as critical components in life
support devices or systems without the express
written approval of the president of Dynamic
Engineering.
Connection of incompatible hardware is likely to
cause serious damage.
©2012-2017 by Dynamic Engineering.
Other trademarks and registered trademarks are owned by their
respective manufactures.

Embedded Solutions Page 3
PRODUCT DESCRIPTION 4!
Headers and TestPoints 6!
DipSwitch Settings 7!
Options 8!
XMC Module Backplane IO Interface Pin Assignment 10!
XMC Module IO Resistor Selection 11!
XMC Module Connector Resistor Selection 13!
APPLICATIONS GUIDE 15!
Interfacing 15!
Construction and Reliability 16!
Thermal Considerations 16!
WARRANTY AND REPAIR 17!
Service Policy 17!
Out of Warranty Repairs 17!
For Service Contact: 17!
SPECIFICATIONS 18!
ORDER INFORMATION 19!
Table of Contents

Embedded Solutions Page 4
FIGURE 1!PCIE8LXMCX2CB JN4/JN6 INTERFACE STANDARD 10!
FIGURE 2!PCIE8LXMCX2CB RESISTOR SELECTION IO 12!
FIGURE 3!PCIE8LXMCX2CB RESISTOR SELECTION CONNECTOR 14!
Product Description
PCIe8LXMCX2CB is part of the Dynamic Engineering PCIe and XMC Compatible family
of modular I/O components. PCIe8LXMCX2CB adapts 2 XMC’s to one PCIe slot.
Embedded applications frequently require real time processing coupled with special
purpose IO. With PCIe8LXMCX2CB’s two XMC positions; a PrXMC can be matched
with another XMC to make a high bandwidth processing node. The PrXMC can
communicate with the host for set-up, and then use the local bus to control and transfer
data with the special purpose IO card.
The CB model has a Connector Bus between the two XMC rear IO connectors. 0 ohm
resistors are used to select which lines are cross-connected and which go to the
standard IO options. The resistors are located front and back with almost “0” stub
length for the unused feature. The connections are impedance controlled and matched
length routed as differential pairs. 100 ohms.
A selection table is provided to help with resistor stuffing selection. Both of the
corresponding CB resistors will need to be installed to make the CB connection. For
example IO0_0P can be connected to IO1_0P by selection of both CB resistors for that
line. The standard IO connections will normally not be selected in this case, and can
be if it makes sense for your system.
Since there are 64 rear IO lines per XMC and each need 4 resistors; a total of 512
resistors are available. Too many to have a standardized table of options. Contact
Dynamic Engineering with your requirement. We will create a new -# to cover your
configuration. A small charge is required to cover the cost of an updated programming
file for the PnP and test program.
1st select which connector is tied to the IO. This can be on a signal by signal basis.
Either, neither, both. 2nd select which IO to connect the selected connections. See
List of Figures

Embedded Solutions Page 5
figures 2 & 3 at the rear of this manual.
Install the RP/RX resistors to tie the XMC signal to the selection point – to distribute to
the SCSI or DIN connector and or other XMC position. Use RCB and/or RIO to select
the IO side of the connection. This “I” form made of 4 0402 resistors allows for selection
with almost no signal stub. Selectable on a signal by signal basis.
Special features:
• 24 lane Gen1/2 compliant Switch
• 8 lanes allocated to PCIe “gold finger” interface. 8 lanes each to the XMC’s
• Switch can store and forward locally to communicate directly between the XMC’s
• Voltage monitors, each with LED’s on plus 12V, minus 12V, plus 5V, plus 3.3V, and
switch power [1.0V]
• 10A regulator for XMC 3.3V and 5V supplies. Shunts for Delayed, not Delayed, Off
• Selection switch for VPWR [12V or 5V] per XMC. Option for hardwired 5V or 12V
• Front panel connector access through PCI bracket
• User IO [Jn4 and/or Jn6] available through one of two cable connectors (DIN IDC or
SCSI II compatible) Spare pins on SCSI connector can be shunt selected to power
or ground.
• Connector Bus available to cross connect XMC rear IO between modules
• Cooling cutout for increased airflow to XMC’s
• Optional Fan(s) for increased airflow
• JTAG programming support
• DIP switch to select global addressing on XMC’s
The PCIe8LXMCX2CB is ready to use with the default settings. Just install the XMC(s)
onto PCIe8LXMCX2CB and then into the system.
RP RX
RIO RCB
SCSI/DIN XMC
JN6
JN4

Embedded Solutions Page 6
Headers and TestPoints
J6 and J11 are used to select the VPWR source for position 0 and 1 respectively.
When the Shunt closes 1-2 – 12V is selected. With 2-3 closed 5V is selected. FET’s
are used to provide a low impedance path from the power supplies to VPWR for each
position. Options are in place on the PCB to allow hardwired selections for clients who
prefer a fixed voltage. The headers are not installed when the fixed voltage option is in
place. With pin 2 open VPWR will be open.
J12, 13, and 23 are used to select the bezel grounding option. 1-2 selects AC coupled,
2-3 selects DC coupled and open is open. J12 = PCIe Bezel. J13 = Slot 0. J23 = Slot
1.
J1 is an optional header for SMB connection. Pin 1 is data and pin 2 is clock. Both are
pulled up. 3rd party tools can be used to see the “innards” of the switch. Usually not
needed but handy if you are doing development or want to talk through the switch to the
XMC positions.
TP1 is an optional JTAG header used to connect to XMC 0. The pin definitions are in
the silk. 1: 3.3V, 2: GND, 3: TMS, 4: TDO, 5: TDI, 6: TCK, 7: TRST
J2 & J19 control the voltage on 33,67 of P2 and P7 respectively when the SCSI
connector options are selected. 1-2 selects 3.3V and 2-3 selects ground on those pins.
The shunt and traces are rated for 1A. Not fuse protected.
J3 & J20 control the voltage on 34,68 of P2 and P7 respectively when the SCSI
connector options are selected. 1-2 selects 3.3V and 2-3 selects ground on those pins.
The shunt and traces are rated for 1A. Not fuse protected.
P3, 4, 6 are optional power connectors to allow for added 12V power to be used by the
PCIe8LXMCX2. The PCIe gold fingers allow for about 60W of power to be consumed
by the board across all XMC voltages including power supply losses. In many cases
the power budget is more than sufficient. If your XMC’s require more power please
request one of the optional power connectors [discrete wire, 4 wire standard PC vert or
horizontal] to increase the 12V available. Both 12V entry points are diode coupled to
prevent the current back-feeding when an external or other supply is added.
P3: 1-2 = gnd, 3-4 = 12V. P4,6: 1= 12V, 2-3 = gnd.

Embedded Solutions Page 7
J4, J5 control the power sequencing for 3.3V and 5V respectively. 1-2 selects a
delayed start-up of the power supply, 2-3 for immediate start-up [based on 12V
available] and open is off [used for power savings when a supply is not required. Added
with Rev 03 boards. Resistor options are available to hardwire the selection.
DipSwitch Settings
Switch 1: Global Address Settings
Position 1-3 corresponds to XMC0 GA0-2. When closed the signal is ‘0’. When open
the signal is ‘1’.
Position 4 corresponds to XMC0-MVR0. When closed the signal is ‘0’. When open the
signal is ‘1’.
Position 5-7 corresponds to XMC1 GA0-2. When closed the signal is ‘0’. When open
the signal is ‘1’.
Position 8 corresponds to XMC1-MVR0. When closed the signal is ‘0’. When open the
signal is ‘1’.

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Options
Dynamic Engineering offers multiple versions of the PCIe8LXMCX2CB design.
PCIe8LXMCX2CB features cooling cutouts designed to support the addition of a fan in
one or two positions for each XMC. On PrXMC's and other XMC’s with high thermal
loads the fan option is a good idea. On cards with a lower thermal profile the fan is not
needed. The fan produces 5 CFM in a small area to create a high LFM rating suitable
for most cooling requirements. The fan used has a relatively low noise rating for quiet
operation. Position 1 is closest to the PCI bezel and position 2 is closer to the XMC
connectors. For position 3 and position 4 locations continue counting left to right.
In addition PCIe8LXMCX2CB has options for Jn4/Jn6 signal routing. VME style 2x32
pin header or a SCSI style connector for IO and the CB bus for interconnecting the two
XMC positions.
Please mix and match options, as you need them.

Embedded Solutions Page 9
The DIN connectors are oriented as shown by the pads under the SCSI connectors in
the picture and the diagram. Pin A1 is the lower left corner pin. Pin C1 corresponds to
the cable wire number 1 for a standard header inserted into the connector on the
PCIe8LXMCX2CB. The mating parts are available from a number of manufacturers.
Cables and breakouts are available from Dynamic Engineering – Please see DINterm64
and DINribn64 or HDEcabl68 and HDEterm68 products from the Dynamic Engineering
website.

Embedded Solutions Page 10
XMC Module Backplane IO Interface Pin Assignment
The figure below gives the pin assignments for the XMC Module IO Interface – from Jn4
and/or Jn6 to the PCIe8LXMCX2CB connectors. Also see the User Manual for your
XMC board for more information. Please note that P2 or P13, P7 or P5 are installed not
both.
DIN IDC [P13,P5] SCSI II [P2,P7] Sig/Sig Jn4 Jn6
A1 C1 1 35 0N/0P 3 1 B1 A1
A2 C2 2 36 1N/1P 4 2 E1 D1
A3 C3 3 37 2N/2P 7 5 C2 C1
A4 C4 4 38 3N/3P 8 6 F2 F1
A5 C5 5 39 4N/4P 11 9 B3 A3
A6 C6 6 40 5N/5P 12 10 E3 D3
A7 C7 7 41 6N/6P 15 13 C4 C3
A8 C8 8 42 7N/7P 16 14 F4 F3
A9 C9 9 43 8N/8P 19 17 B5 A5
A10 C10 10 44 9N/9P 20 18 E5 D5
A11 C11 11 45 10N/10P 23 21 C6 C5
A12 C12 12 46 11N/11P 24 22 F6 F5
A13 C13 13 47 12N/12P 27 25 B7 A7
A14 C14 14 48 13N/13P 28 26 E7 D7
A15 C15 15 49 14N/14P 31 29 C8 C7
A16 C16 16 50 15N/15P 32 30 F8 F7
A17 C17 17 51 16N/16P 35 33 B9 A9
A18 C18 18 52 17N/17P 36 34 E9 D9
A19 C19 19 53 18N/18P 39 37 C10 C9
A20 C20 20 54 19N/19P 40 38 F10 F9
A21 C21 21 55 20N/20P 43 41 B11 A11
A22 C22 22 56 21N/21P 44 42 E11 D11
A23 C23 23 57 22N/22P 47 45 C12 C11
A24 C24 24 58 23N/23P 48 46 F12 F11
A25 C25 25 59 24N/24P 51 49 B13 A13
A26 C26 26 60 25N/25P 52 50 E13 D13
A27 C27 27 61 26N/26P 55 53 B15 A15
A28 C28 28 62 27N/27P 56 54 E15 D15
A29 C29 29 63 28N/28P 59 57 B17 A17
A30 C30 30 64 29N/29P 60 58 E17 D17
A31 C31 31 65 30N/30P 63 61 B19 A19
A32 C32 32 66 31N/31P 64 62 E19 D19
33 67 Open, +3 or GND via J2,19 silk screen defined
34 68 Open, +3 or GND via J3,20
FIGURE 1 PCIE8LXMCX2CB JN4/JN6 INTERFACE STANDARD
Read table:
P13-C1 = P2-35 = Pn4-1 P13-A1 = P2-1 = Pn4-3 etc.
With Jn6: Pins: A, B, D, E of rows 2, 4, 6, 8, 10, 12 ,14, 16, 18 are grounded
Effective connections with RIO column of resistors installed and both connector
selectors.