DZ SIENNA User manual
Page
DZKit
SERVICE MANUAL
SIENNA
HF REcEIVER/Transceiver
Price: $30.00
DZ CompanY • LOVELAND, COLORADO
Page 2
DZ COMPANY CONTACT INFO
Orders, parts, phone assistance.....................................................................(970) 667-7382
Email orders............................................................................................... [email protected]
Email technical support .........................................................................[email protected]
Web site .......................................................................................................www.dzkit.com
Mail:
DZKit
710 Grove Ct.
Loveland, CO 80537
During your first ninety (90) days of ownership, DZ Company will replace or repair free of charge—as soon as
practical—any parts which are defective, either in materials or workmanship. You can obtain parts directly from
DZ Company by writing us, emailing us or telephoning us. And we’ll pay shipping charges to get those parts to
you—anywhere in the world.
We warrant that during the first ninety (90) days of ownership, our products, when correctly assembled,
calibrated, adjusted and used in accordance with our printed instructions, will meet published specifications.
You will receive free consultation (except for the cost of your long distance phone call) on any problem you may
encounter in the assembly or use of your DZKit product. Just drop us a line, email us, give us a call, or visit our
website and click on “Support”. That will give you access to free on-line support and a discussion group. Sorry,
we cannot accept collect calls.
Our warranty, both expressed and implied, does not cover damage caused by the use of corrosive solder,
defective tools, incorrect assembly, misuse, fire, customer-made modifications, floods or acts of God, nor does it
include reimbursement for customer assembly or setup time. The warranty covers only DZKit products and is
not extended to non-DZ allied equipment or components used in conjunction with our products or uses of our
products for purposes other than as advertised.
If you are ever dissatisfied with our service—warranty or otherwise– or our products, please write or email the
president, Brian Wood, W0DZ, and he will make certain your problems receive prompt, personal attention.
THE DZ COMPANY, LLC
LOVELAND, CO 80537
YOUR DZKIT 90-DAY FULLWARRANTY
Page 3
Service Manual for the
Sienna HF Transceiver
DZ COMPANY
LOVELAND, COLORADO
Copyright © 2011
The DZ Company., LLC
All rights reserved
3-6-11 Sienna
TABLE OF CONTENTS
Troubleshooting ............................... 4
Voltage, Resistance Charts ............... 6
Specifications................................. 10
Theory of Operation........................11
Block Diagram............................... 33
Schematics ..................................... 34
Page 4
TROUBLESHOOTING
Thenicethingaboutbuildingyourowntransceiverisbeingableto
fixitifitbreaks,ortofigureoutwhyit’snotworkingquiteright
asyouturnitonforthefirsttime,WITHOUThavingtosenditback
tousforrepair.Butwehavefoundthatmanypeoplelackbasictrou‐
bleshootingskills.Sohereareafewtipstohelpyounarrowdowna
problem:
1.StartbymeasuringthemainDCvoltagesoneveryboard.Isthe5V
supplyreally5V?Mostlogiccircuitscantoleratearangeof4.75
to5.25V.Ifit’slessthan4.75,lookintothecause—disconnect
allboardsfromtheDCDboard’spowerconnectorsandmeasurethe
voltagethere.IsitOK?Ifitis,plugtheotherboardsinoneat
atimetoseewhichoneisaffectingthevoltage.Ifnot,trouble‐
shootjusttheDCDboard.
2.Isolatetheproblemtoaboard,andthentoasectionofthat
board.Forexample,isthereceiverworkingbutnotthetransmit‐
ter?Sincethereceiverusesthesamelowpassfiltersasthe
transmitter,andtheyarelocatedonthetransmitterboard,youcan
ruleoutonewholesectionofthetransmitterboard(allthelow
passfiltertoroidsandassociatedrelays).
3.Figureoutwhatitcan’tbe,tohelpyouunderstandwhatitcanbe.
Forexample,ifplugginginthetransmittermakesthereceiverquit
working,itcouldbethatthetransmitterisloadingdownthe
shared8‐bitdatabus.Orperhapsitisdrawingtoomuchpowerand
causingthevoltagetodroptoolow.MeasureDCvoltagesfirst,to
makesurethatthecircuitsyoususpectarebadaregettingpower.
4.Replaceunknownsignalswithknowngoodones.Forexample,ifthe
receiverdoesn’twork,isasignalmakingitallthewayfromthe
antennajackthroughtheantennaswitchontheDCDboardthrough
theSWRmetercircuit,throughthetuner,throughthelowpassfil‐
tersonthetransmitter,throughtheT/Rswitch,throughtheband‐
passfiltersandpreampsontheRXBPFboardandallthewaytothe
RFinputjackonthereceiverboard?Lotsofcircuitsthere!Try
disconnectingthenormalRFinputandconnecttheantennainputor
anyothersourceofRFdirectlytothereceiverboard.BecauseSi‐
ennahasalotofcableinterconnects,youhavegreatflexibility
inseparatingonecircuitfromanother.
Page 5
SymptomPossibleCausesFix
5vSupplyreadslow,
frontpanelseems
lockedup
C24onDCDboardMakesureC24is
mountedtherightdi‐
rection,resolderit.
DCDTraygetsveryhotNormalwithoutcover
on
Attachtopcover.The
extraheatsinkingand
fanswillkeepthe
traycool
AntennaA/Brelays
don’tswitch
UnsolderedpinsRemoveDCDboardand
checksolderconnec‐
tionsonallrelays
Transmitterdoesnot
transmit
TXPVCCsignalinopera‐
tive
Makesurethereisno
voltageontheTxIn‐
hibitinputonthe
Linearinterfacecon‐
nector.CheckQ13base
(shouldread9.1V).
CheckR68,D18,R4,
R5,Q16.Makesure
LPTTgoeslowduring
transmit(gateof
Q16).Checkcontinuity
throughlowpassfil‐
ters.MakesureQ4and
Q5jumpersagreewith
installedtransistor
types.
IFFilterBoardfails
test
Solderconnections.
ICsmountedbackwards.
Cableattachedto
wrongsideofboard.
Jumpersontestboard
setwrong.
Inspectallsolder
joints.Makesurepin
1ofICsisinsquare
pad.Makesure8‐pin
cableisattachedto
bottomsideofboard.
Re‐checkthejumpers
onthetestboard.
RxBPFfailstestToroids,soldering,
filtersnotinstalled,
powerconnectorsin‐
stalledonwrongside
ofboard
Measurecontinuity
acrosstoroids,resol‐
der.Re‐heatallsol‐
derconnections.Make
sureconnectorsare
mountedright.
Page 6
VOLTAGE, RESISTANCE CHARTS
MeasurementpointVoltage
J10pin15.0V+/‐.15V
J10pin2‐9.5V+/‐.5V
J10pins3and50.0V+/‐.05V(ground)
J10pin4Appliedvoltage(11‐15V)
Anode(unbandedside)ofD70.25*appliedvoltage
Cathode(bandedside)ofD9andD52.7V
JunctionofR24andR250.17*appliedvoltage
Table1.DCVoltagesonDCD/TunerBoard
Page 7
PinVoltage(+/‐5%)
J5pin1+5.0V
J5pin2‐9.5V
J5pin4+11to+15V
J13pin49.0V
TP3>4.0V
U14pin1‐5.0V
U13pin3+5.0V
U18pin14+11to+15V
U19pin14+11to+15V
U4pin8+4.5V
U4pin4‐9.0V
U22pin8+5.0V
Q5gate1+2.0V
Q5source+1.9V
Q5drain+7.6V
Q20gate1+2.0V
Q20source+1.9V
Q20drain+7.7V
U25pin7+9.0V
U30pin8+9.0V
U30pin4‐5.0V
U5pin8+5.0V
U9pin2+8.5V
U26pin7+8.9V
U7pin8+5.0V
U11pin4+5.0V
U11pin11‐5.0V
Table2.DCVoltagesonReceiverBoard
Page 8
PinVoltageModeModeCommands
Menu
setting
J18pin1(right)5.0V
J5pin5(bottom)VCC
U18pin3(top)10.0V
TestPoint:CWFM9.5V
CWUSB,
CWLSB,FMmd3;md7;md4;
9.5V
AM,USB,
LSB,DIGUSB,
DIGLSB
md5;md2;md1;
md6;md9;
TestPoint:AM‐ESSB9.5V
AM,USB,
LSB,DIGUSB,
DIGLSB
md5;md2;md1;
ESSBon
(es1;)
md6;md9;
TestPoint:SSB9.5V
USB,LSB,
DIGUSB,
DIGLSB
md2;md1;
ESSBoff
(es0;)
md6;md9;
JP12(top)5.0V
JP12(bottom)5.0V
J6pin1(left)2.5V
JP3(top)2.5V
JP4(top)2.5V
USB,LSB,
DIGUSB,
DIGLSB
md2;md1;
ESSBoff
(es0;)
md6;md9;
U20pin12.5‐3.5V
USB,LSB,
DIGUSB,
DIGLSB
md2;md1;
ESSBoff
(es0;)md6;md9;
U20pin23.0V
U20pin42.5V
C162(bottom)1.8V
USB,LSB,
DIGUSB,
DIGLSB
md2;md1;
ESSBoff
(es0;)md6;md9;
U17pin12.5‐3.5V
AsTxdrive
isvariedmd3;md7;md4;
TxDrv
CW/FM
U17pin12.5‐3.5V
AM,USB,
LSB,DIGUSB,
DIGLSB
md5;md2;md1;
TxDrv
AM/SB
md6;md9;
U17pin23.0V
U17pin42.5V
U8pin12.5‐3.5V
asRFPower
isvaried
TxALC
off
U8pin23.0V
U8pin32.5V
U8pin42.5V
Table3.DCVoltagesonTransmitterBoard
Page 9
PinVoltageModeModeCommands
JP7(left)1.4V
Transmitter
keyed
Q3base(leftpin)1.2V
Transmitter
keyed
Q3emitter(rightpin)0.4V
Transmitter
keyed
Q3collector(centerpin)VCC
R21,C9orC133(top)9.5V
CWUSB,CWLSB,
FM
md3;md7;md4;
Transmitter
keyed
Q4collector
VCC
(centerpinon2SC1969)
Q5collector
VCC
(centerpinon2SC1969)
R42(top)5.0V
Transmitter
keyed
R42(top)<0.7V
Transmitter
keyed
(Keydownin
CWmodes,PTT
pressedin
phonemodes)
D3cathode4.3V
Transmitter
notkeyed
D3cathode(squarepad)<0.7V
Transmitter
keyed
(Keydownin
CWmodes,PTT
pressedin
phonemodes)
ToprightpinonK2<0.8VFreq<2MHzfa00001800000;
ToprightpinonK4<0.8VFreq2‐6MHzfa00003500000;
ToprightpinonK6<0.8VFreq6‐12MHzfa00007000000;
ToprightpinonK8<0.8VFreq12‐20MHzfa00014000000;
ToprightpinonK10<0.8VFreq20‐30MHzfa00021000000;
Page 10
Frequency range: 10 kHz to 30 MHz (Specs valid 500 kHz-30 MHz)
Modes: SSB, CW, AM, FM, (Digital via optional embedded PC)
FM modulation: frequency modulated carrier with pre-emphasis, selectable deviation (2.5,
4, 5kHz)
FM receive IF: 455kHz, includes two ECS LTM455DU 4-pole +/-10KHz ceramic filters
(can be replaced with filters as narrow as +/-3KHz)
Sensitivity: 0.4uV for 10dB S/N (preamps off, PSBTM off)
MDS (PSBoff): -120/-128/-132dBm (preamps: off/1/both)
MDS (PSBon): -125/-130/-132dBm (preamps: off/1/both)
BDR: >105dB at spacings greater than 1KHz, >125dB at >4KHz spacings with optional
Inrad roofing filter
Tx IMD: 3rd order: -40dB PEP @ 10W output, -36dB @ 100W, 5th order down > 50dB
Noise Blanker: Variable threshold
Freq stability: +/-1 ppm (0-50C) after 30 minute warm-up, using included TCXO
Displayed resolution: 1 or 10 Hz (internal resolution is sub-Hz)
Tuning step size: 1, 10, 100, 1K, 10K Hz
RIT, XIT range: +/-16MHz, with two speeds
Memories: 147, including 85 programmable GP memories preset to desired bandplan, one
scratchpad preset to WWV, all accessible using external keypad or PC, 5 VFOA memories
per band and one VFOB memory. 10 12-character CW buffers, editable in menu, activated
from external keypad. Farnsworth timing selectable from menu.
Mic input impedance: 200-1K Ohms
IF frequencies: 70.455 or 70.000 MHz, 9.0 MHz, 455 kHz
IF Filter selection: (see Inrad web site for filter specs) NOTE: Inrad filters must be
mounted on Yaesu-compatible "C" boards. If ordering directly from Inrad, be sure to
specify this option. Broadband IF frequency output: 455Khz +/-250KHz, 50 ohms
Transverter output: max 0dBm (1mW, 50 ohms)
Stereo audio output power: 1.5W/ch (available even while using headphones)
Linear control outputs: QSK via high-power MOSFET, TTL band data, ALC (range 0 to
-5v)
DSP (DSP - autonotch, variable bandwidth filters, NR, AGC) software from Silicon Pixels
included with PC option
DC power requirements: 2.5A receive (10-15v), 6A transmit @10W, 26A transmit
@100W output (13.8-15V), PC adds 1 or 2A depending on model
Dimensions: 3.5"H x 14"W x 16"D (feet located in a 12.25" x 14.0" area)
Weight: 10 lbs (base unit), 12.5 lbs with 100W amp and PC
Specifications subject to change without notice.
Specifications
Page 11
Theory of Operation
The Sienna HF transceiver is organized into five major blocks:
• DC Power conditioning (DCD board)
• Control (Controller, Front Panel and VFD boards)
• Receiver (Receiver, BPF and IF Filter boards)
• Transmitter (Transmitter, TXBPF, Tuner and 100W amplifier boards)
• PC (PCPS and PC boards)
Refer to the Block Diagram on page 43 and the Schematics starting on page 44.
DC Power Conditioning: DCD board
Over-voltage. Under-voltage, reverse polarity and overcurrent protection
Kit rigs sometimes fail to do some basic power conditioning on the input, making them failure-
prone. The Sienna includes over- and under-voltage protection, over-current protection (fuses),
and reverse polarity protection. In addition, the internal DC voltages of +5V, +9V and –9V are
derived from regulators which have additional input and output protection circuitry.
Refer to the DCD board, sheet 3. The DC input from Anderson Powerpole connectors is pro-
tected from reverse polarity by diode D6. Capacitor C21 adds some protection against static dis-
charge and shunts any high frequency energy to ground.
R26 and zener diode D9 tap a small amount of current from the input even when power is off in
order to provide a 2.7V DC reference for comparator U7, an LM393. Capacitor C22 assures
that any rapid changes in the input voltage will be swamped out, keeping the reference voltage
stable until the input voltage drops well below normal.
R9, R10, D7 and C20 provide a voltage divider with long attack and very fast decay, setting the
low trip point at about 1/3 of the input voltage. When the voltage rises above 2.7*3 (8.4V), the
output of comparator U7 (pin 1) goes high. As long as the other comparator output (pin 7) is not
low, the DC voltage will be enabled. Diode D7 assures that when the voltage drops, capacitor
C20 is discharged quickly.
R24, R25 and C23 form a similar divider and stabilizer to detect when the voltage is above
15V.
Resistors R11 and R12 on one comparator, and R13 and R23 on the other, add a couple of Volts
of hysteresis to keep the output of the comparators from oscillating at the trip points.
If the output of either comparator goes low, transistor Q2 turns off , causing K19, a 25A auto-
Page 12
motive relay, to open, which removes power. When the comparator outputs are both high, pul-
lup resistor R14 assures that Q2 will be on, enabling the relay to turn on. The relay cannot actu-
ally turn on unless the on/off switch is pushed because one side of the relay coil is routed
through the switch to DC power.
Fuse F1 protects the radio from overcurrent conditions. This is a 9A Resettable fuse. When it
warms up enough due to overcurrent conditions, it suddenly develops a high resistance, keeping
high current from flowing. As it cools, it automatically resets.
When Q2 and the on/off switch are on, DC voltage appears at pad W3, which provides power
for the 100W amplifier. Since this is a high current lead, it is located as close as possible to the
relay to minimize voltage drop. A short cable connects this point to the amp. When the tray is
rotated up for service, an extension cable is required. This extension cable will have noticeable
voltage drop when the 100W amp is in use, so performance could suffer. As a result, it should
not be used except for testing.
On/off switch LED
Comparator U6 is used to detect when the DC voltage going to the regulators has dropped to a
low enough level that they are about to shut down. When the voltage gets to a little over 10V,
the LED inside the on/off switch is turned from green to red. This is useful when operating the
radio from batteries.
Regulators
The 5V regulator, U8, is a low-drop-out regulator, which means that it does not require much
more voltage going in than it generates. However, excessive voltage going in would make it run
very hot, so its input voltage is dropped by pass transistor Q1 and regulator U9 from the input
of 11V-15V. Both regulators have input and output protection. They are mounted to the tray,
providing excellent heatsinking, and the dual fans in the compartment below the tray help keep
the tray cool during normal operation. During service, with the top open, the cooling effect of
the fans is greatly reduced, and the tray can get quite hot. Operation with the top off is not rec-
ommended for long periods of time.
U10 is a MAX765 negative voltage generator. It is a “chopper”, which turns the DC input volt-
age into an AC voltage which is then converted back to DC and output as a negative DC volt-
age. This negative voltage is used by the receiver to allow high performance dual supply op-
amps to be used. RFC1 helps keep the switching transients off the line, which could induce
noise into the sensitive receiver circuits.
The raw DC input is also fed to the receiver, controller and transmitter. The receiver uses the
Page 13
raw input voltage on the audio output amplifiers in order to allow them to handle the very high
instantaneous currents (up to an amp!) needed for good speech reproduction.
Antenna switch, SWR meter
The DCD board also has an antenna A/B switch and an SWR meter on it (see sheet 2 of 3 on
the DCD/Tuner schematic). Relay K17 and K18 switch between main antennas A and B. The
use of two relays instead of one provides better port-to-port isolation. A portion of the transmit-
ted signal, both forward and reflected signals, is picked up by transformer T1 and fed into
buffer U5. The outputs are clamped to keep the levels from exceeding 5V, and are fed to the
main controller’s A/D converters for measurement. C17, RV1 and RV2 are used to calibrate the
meter so that the measured voltages correspond to correct power levels as measured against an
external wattmeter. If no wattmeter is available, a 50 ohm dummy load allows the meter cali-
bration to come close.
In order to handle both 10W transmitters and 100W amplifiers, the output of U5 is scaled by
resistive dividers R5/R32 and R6/R33. A signal (/NOPA) from the amplifier goes high if the
amplifier is present and enabled. If it is not present, R31 keeps the voltage low, forcing Q6 and
Q7 to be off and removing the scaling factor.
Control circuits are discussed in the Controller theory section.
Page 14
Control: Controller, Front Panel and VFD Boards
The main Controller board is the heart of the Sienna. An Atmel Mega644P microcontroller (U9)
running at a clock frequency of 16MHz provides the main control functions, and a second
Mega644P (U30) is used for Keyer, VOX/AntiVOX detection, microphone sampling in FM,
keypad detection and meter backlight functions. A +/-1 PPM Temperature Compensated Crys-
tal Oscillator (TCXO), six Direct Digital Synthesis (DDS) chips and associated bandpass filters
and high bandwidth buffer/amplifiers provide a clean source of high purity, low phase noise
local oscillators for the transmitter and receiver.
Refer to the Controller schematic pages, Sheets 1 through 11. While this four layer board is
very dense and may look formidable, the circuitry is actually very straightforward. Sheet 1
shows the DC input conditioning. Two 3.3V regulators are used to drop the 5V down to 3.3V
for the DDS chips and the buffers that drive their data and address busses. R2/C3 and R38/C46
provide decoupling for the analog 5V supply that is used for the A/D converter circuits on the
microprocessors.
Main microprocessor
Sheet 2 shows the main microprocessor. This processor has 64K bytes of internal program stor-
age, 4K bytes of RAM and 2K bytes of Electrically Erasable Programmable Read-Only Mem-
ory (EEPROM). The EEPROM stores constants and lookup tables such as the filter parameters,
current state of the instrument, band plans and so on. A software timer writes data to the
EEPROM every 10 seconds if anything that needs to be saved has changed. Main memory and
EEPROM memory can be rewritten through the SPI bus (J6), which is what is used at the fac-
tory to initially program the processor, or through the RS-232C port (pins 9 and 10 on the proc-
essor, going to U7 on Sheet 4. The ST207E converts CMOS voltages into RS-232C levels
which are fed to the PC or the back panel via J4. Other RS-232C control lines (RTS, CTS) are
also converted to CMOS levels by U7 and fed to the secondary microprocessor to allow hand-
shake control and use of RTS as a CW key. RS-232C signal DTR is fed into the PTT circuitry
via Q2 and Q4. Q21 allows this signal to be disabled (via control bit SERDIS), since at boot-up,
the PC can pull the DTR line and we do not want it causing the rig to go into transmit mode!
U8 is a power-on reset chip providing a long reset pulse to start the processor correctly when
power is first applied.
LTxEn, HRcvEn
The signal that turns on (enables) the transmitter is called LTxEn. As with many signals, the
“L” means it is low true (0 Volts). (“/” is also used to indicate low true signals.) This signal is
generated by the main microprocessor in response to detection of a Push-To-Talk (/PTT) signal
from the microphone, or by the Keyer microprocessor (PTT_Keyer), which is responsible for
VOX detection and for CW keying, or by the DTR signal on the RS-232 port. DTR can be dis-
abled via an output port bit called SERDIS to keep RS-232 problems from holding the transmit-
ter on. These three signals are wire-or’d together and fed into an input port as HPTT so the
main microprocessor can tell when a transmitter enable signal is either being requested by the
Page 15
user (the mic’s /PTT) or when the Keyer is controlling it. An output port bit, PTTO, or the
Keyer, via PTT_Keyer, are used to generate LTxEn, which is fed to the 10W transmitter as well
as the 100W amplifier (Sheet 7).
The Keyer microprocessor also controls when the receiver is enabled, through the signal
HRcvEn. The two control signals, LTxEn and HRcvEn, are sequenced so that the receiver is
muted before the transmitter turns on, and so that the transmitter has time for the RF to make it
all the way through the various amplifier stages (and so that RF bleedthrough into the receiver
stages also have time to propagate) before the receiver is un-muted and its AGC controls re-
turned to normal.
Sheet 4 also shows the 5V to 3.3V level converter (U10) that drives address and data lines on
the DDS chips.
A-to-D (A/D) Converters
Going back to Sheet 2, the Mega644P has eight A/D converter inputs. There is actually only
one 10-bit A/D inside the chip, and it uses a multiplexer to look at one analog input at a time.
The signals fed into the first seven inputs are the FM squelch, AF Gain, RF Gain, Mic Gain,
Headphone Volume, RF Power and RF Processor pots that are located on the Front Panel board
and fed into the Controller on J9 (Sheet 6). The eighth analog input comes from U19 on Sheet
7. This CMOS analog multiplexer selects one of eight additional voltages: Forward and Re-
flected Power from the DCD/Tuner board; Supply voltage, ALC/compression and Driver Cur-
rent from the 10W transmitter board; Final Current from the 100W PA board, S-Meter value
from the Receiver board, and the value of the IF Filter switch on the Front Panel. An interrupt
routine in the microprocessor selects and samples one of these 15 voltages every time an A/D
conversion completes (about every 64 microseconds).
Parallel Data Bus
Also on Sheet 2, Port C of the processor is used as an 8-bit parallel data bus for all boards. This
bus is buffered by U15 to become the “XBus”. Its output is enabled only when data on one of
the boards needs to be changed, otherwise pull-up resistors on each board terminate the bus and
keep it quiet to avoid causing unnecessary digital interference to the transmitter or receiver.
U20 is an address decoder. AS0, AS1 and AS2 (U34, Sheet 6) select one of eight data strobe
pulses for the DDS chips and read/write pulses to the Keyer microprocessor.
I/O Strobes, inter-processor communications and address decoding
Port B on the microprocessor is used for I/O control. IOStrobe1 and /IOStrobe2 serve as clock
pulses to output data from Port C to the various I/O chips on the Controller board. (The “/” in
front means that the signal is low true, meaning that it is normally high and pulses low when
active.) DispRDY and /DispCk are signals from and to the Vacuum Fluorescent Display board
that are fed to the Controller board from J17 on Sheet 7. KeyerRDY is a signal from the Keyer
microprocessor (U30, pin 42, Sheet 3) that tells the main processor that data is either ready on
Page 16
port C or has been accepted from port C. Q12 provides a Frequency Update pulse for all DDS
chips. A4 and A5 are address lines for the DDS chips.
Port D has the RS-232C data lines TXD and RXD, Rotary Pulse Generator (RPG) outputs from
the two tuning dials, and additional address lines for the internal I/O ports and DDS chips.
Sheet 5 shows address decoding for the 16 data strobe lines /Strobe1 though /StrobeG. These
are used to output and input (“strobe”) data on port C to and from all boards in the rig as well as
various control functions on the Controller board. Sheets 5 and 6 show most of the internal
ports. /Strobe1 and /Strobe2 read switch data from the Front Panel board. /Strobe2 also reads
the state of the internal PTT line so that the processor knows when an external device
(microphone, etc.) has activated the Push-to-Talk. /Strobe4 (Sheet6) and /Strobe7 (Sheet 5) pro-
vide outputs that directly drive LEDs inside the pushbutton switches on the Front Panel board. /
Strobe6 (Sheet 5) and /Strobe5 (Sheet 6) provide 16 outputs that are used for a variety of con-
trol functions.
/Strobe8 through /StrobeG are fed to the Receiver, Transmitter and Tuner boards along with the
XBus to program those boards. (See Sheet 7).
Serial Bus
A serial bus is also fed to the Receiver and Transmitter boards. SCL (U13 pin 9) and SDA (U13
pin 12, as well as U12 pin 17) (Sheet 5) form a high speed I2C bus that is used to control DACs
and Digitally Controlled Potentiometers (DCPs) on the Receiver and Transmitter boards. This
bus is quiescent (not active) unless changes are needed, which helps avoid digital interference
to sensitive receiver and transmitter circuits.
DDS
Sheets 8 through 11 show the DDS chips, bandpass filters on each output, and buffer amplifiers.
Normally, DDS chips only require low pass filters on their outputs. Sienna uses bandpass filters
so as to provide a much more constant impedance across the frequencies they must output,
which helps to keep the level constant without the need for complex AGC circuitry. These de-
vices take five bytes (AD9851) or 6 bytes (AD9852) of digital data and convert it directly to a
frequency. The 0-512mV output must be converted to +/-256mV, amplified, and filtered to re-
move harmonics and other spurious signals (spurs). Close in spurs are typically down at least
70dB. A +/-1PPM TCXO provides a stable, low phase-noise 30MHz reference oscillator for all
six DDS’s.
The TV (Transmit VFO, not television!) signal coming from the TXVFO DDS (U5) on Sheet 8
is routed to a pair of Hittite GaAsFET switches which are controlled by TXVFILT (Sheet 5, pin
2 of U13). These switches allow one of two low pass filters to be applied to the output of the
TXVFO amplifier. The TXVFO covers the frequency range 12.5 to 40.4MHz, so a low pass
filter tuned for, say, 41MHz, would allow harmonics from frequencies at the lower end of the
range to pass though, so a dual range filter helps keep the output pure. The firmware performs
the switch at a TXVFO frequency of 22MHz (operating frequency of approx 11.3MHz).
Page 17
Note that a similar switch is not needed for the RXVFO, because it operates at a much higher
frequency range of 70-100MHz. Any harmonics of 70MHz fall well outside the upper cutoff of
the Butterworth bandpass filter (105MHz).
LED Backlight
Sheet 7 shows backlighting circuitry for the meters. Q13, Q14 and Q15, along with the associ-
ated resistors, form a 3-bit binary control, allowing up to 8 brightness levels. The control lines
for these MOSFETs come from the Keyer processor. High intensity LEDs D1-D4 provide
plenty of light for the two meters.
MIC Bias
A 9V bias for electret mics can be turned on and off via Q16 (Sheet 7). The MICBIAS control
bit from U13, pin 19 on Sheet 5 is used for this.
Keyer microprocessor
Sheet 3 is a diagram of the Keyer processor. The keyer speed, dot weight, dash weight and pitch
pots from the Front Panel board are fed into the first four A/D inputs on port A (ADC0-3), simi-
lar to those of the main processor. A/D input 4 (the 5th input) comes from the transmitter
(routed through the receiver board) and is a buffered, uncompressed version of the microphone
audio, level shifted so that it idles at 2.5V with a peak-to-peak AC voltage of up to 5V. For
VOX detection, the processor takes a running average of the AC voltage and computes an RMS
value that is tested against a trip threshold set by a menu option. (During FM transmit, all A/D
inputs are disabled except the mic, so that rapid sampling of the audio can occur, with this in-
formation passed to the main microprocessor in order to re-program the DDS chip controlling
the BFO in real-time.) Similarly, the buffered and level-shifted speaker output is fed into A/D
input 7 to form the Antivox input. Another RMS calculation is done on this signal and used
along with a menu item to adjust the trip point of the VOX input up or down. A/D input 5 is the
external keypad input. Yaesu designed the FH-1 keypad as a set of 12 buttons with resistors in
series with them such that 12 different DC voltages from 0 to 5V are produced. The firmware
tests these voltages to determine which button has been pushed and sends this coded informa-
tion over the internal inter-processor bus (port C on both processors, with KeyerRDY,
/KeyerRd and /KeyerWr). The Keypad input from the back panel is routed to A/D input 5,
which reads the 0V to 5V signal to determine which of 12 buttons was pushed.
A/D input 6 is grounded. This bit allows the processor to determine if the controller board is rev
A or B. Rev A boards left this line floating (pulled high by an internal pullup inside the proces-
sor). Different code is executed depending upon whether the board uses rev A or B hardware.
Port B, bit 3 is used as a Pulse Width Modulated output signal whose frequency is determined
by the Pitch pot. The output is filtered by an RLC network and routed to the Front Panel board
where it goes through the Sidetone pot and back to J11 which then goes to the Receiver board’s
audio output stage. If no front panel is present, jumper JP2 (Sheet 7), assures that the Sidetone
(at full volume) will make it to the receiver board.
Page 18
The dot paddle and dash paddle inputs are filtered and fed to two edge-driven interrupt lines
(port D, bits 2 and 3). The manual key input is fed to bit 0, where it is sampled continuously in
the 1ms interrupt routine. Outputs from the Keyer are the PTT_Keyer line, which is routed to
the controller to allow the Keyer to control the PTT line, and the Key line, which is routed to
the transmitter.
The Keyer processor also has its own SPI bus for programming and a power-on reset chip. This
processor is not programmable by the user. Any changes to its internal firmware must be done
either by the factory or in the field through the use of an inexpensive Atmel programmer board
(STK500).
Display board
The VFD board is a Noritake GU256x64C-3900 model that is programmed with ASCII control
command sequences. It connects to port C as just another I/O device. DispRDY and /DispCk
signals provide the handshaking. Jumper JP1 on the Keyer processor tells the main controller if
a front panel is present. One of the effects of this is to cause the display routines to be ignored if
no front panel is present.
Receiver: BPF, Receiver and IF Filter Boards
Refer to the block diagram on page xxx and to the schematics on pages xxx-xxx.
Antenna to bandpass filters
RF from the main antenna ports (A and B) passes through low pass filters and a transmit/
receive (T/R) PIN diode switch on the transmitter or 100W amplifier boards. From there, the
signal enters the antenna input (J2) on the RXBPF board (See RXBPF schematic, Sheet 2). Re-
lay K6 selects either this input or one from the Receive Antenna input (J3) after the latter is
passed through a 35MHz low pass filter. The Receive Antenna does not pass through band-
specific low pass filters or a T/R switch as does the main antenna, which reduces the loss, but
also exposes it to potential intermodulation distortion (intermod) from strong shortwave sta-
tions. If you experience intermod when using the receive antenna, we recommend use of an ex-
ternal bandpass filter such as those made by Array Solutions. Back to back zener diodes on the
Receive Antenna input protect against extremely strong signals.RFC1 is a 1mH choke that
routes low frequencies to ground, reducing hum from power lines.
High-pass and bandpass filters, attenuator1, PSBTM
The selected signal is then fed through a high-pass filter located between GaAsFET switches
U5 and U6. This filter reduces the chance of intermod from strong AM broadcast stations and is
engaged automatically when the receive frequency is above 1.6MHz. The signal then passes
through a 10dB attenuator which can also be switched out. Pressing the front panel Pre2/Atten
button activates this attenuator unless preamp1 is on. The output, “A” on the schematic, is then
passed through eleven bandpass filters, each controlled by a pair of GaAsFET switches, with
each filter handling a different segment of the HF spectrum. In addition, one pair of GaAsFETs
Page 19
(U20/U21 on Sheet 8 of the RXBPF board) is allocated as a bypass. This circuit represents the
DZKit exclusive Passive Signal Boost (PSB)TM. By skipping the BPFs, any associated front-end
loss is eliminated at the expense of a potential increase in intermod, and an increase in the noise
floor, since more spectrum is allowed in. However, on a fading band, that extra 5dB of
“gain” (actually “lack of loss”) can spell the difference between hearing and not hearing a weak
signal. PSB is not intended to be used except under such conditions. We do not recommend that
you leave it enabled permanently even though signals will sound stronger.
Preamps, attenuator2
The selected bandpass filter’s output is point “B”. Referring to Sheet 9 on the RXBPF board, B
is routed directly to the first preamp (Q4 and associated circuitry) and to relay K4, where it can
be fed to the RF output without preamps. The first preamp’s output can be switched on by relay
K1 and appears at point R2, which feeds preamp2 (Q4 and associated parts) and relay K5. If K5
is disabled, so is K2, and thus Q4 has no power and provides only a weak load for preamp1. If
K2 and K5 are enabled, preamp1 is fed into preamp2 and then out to the RF output.
The preamps are low noise 2N5109 bipolar transistors set up for a power gain of about 12dB
and coupled via broadband toroid transformers T1 and T2.
Receiver first IF
The final RF output of the BPF board feeds into the Receiver board at J14 (Sheet 2 of Rx
Board). It is applied directly to a Minicircuits TUF-3 diode ring mixer (U6). Local oscillator
LO1 from the controller, which is the VFO, is set to the displayed receive frequency plus
70.455MHz (or 70.000MHz if the 20kHz roofing filter is used) and fed into the LO port. The
output, consisting of sum and difference frequencies and a number of other mixing products,
splits into two paths via a 50 ohm resistive pad, with one leg driving an Inrad 4KHz bandpass
filter at 70.455MHz and the other driving the FM receive and IF output circuitry.
The output of the bandpass filter is amplified by Q5, a dual-gate MOSFET with about 10dB of
power gain. The second gate of Q5 is derived from the AGC circuitry on Sheet 6, buffered and
inverted by U1 to provide a nominal 4V on gate 2, decreasing to 2V under full AGC action and
reducing the gain accordingly. The source is biased at 1.9V, so the 4V on gate 2 represents 2.1V
of gain enhancement. When the control voltage goes down to 2V in response to a strong signal
detected by the 3rd IF, the differential of 0.1V reduces the gain to its minimum level. Diodes
D11 and D12 provide temperature compensation while contributing to the source bias of 1.9V.
The output of Q5 feeds a Darlington transistor configuration, which provides high input imped-
ance and low output impedance, necessary to successfully drive the next RF mixer. Resistors
R101 and R126 set Q5’s load impedance to about 2K ohms to provide a moderately high im-
pedance load for the amplifier, whose nominal output impedance is about 200 ohms, while bias-
ing the Darlington stage at a reasonable level. This preserves the power gain while allowing the
stage to drive the low impedance (50 ohm) mixer load.
Page 20
Receiver second IF
The 70MHz 1st IF output of the Darlington driver feeds U8, another TUF-3 mixer, along with
LO2 from the controller set to 61.455Mhz (+/-, depending on filters in use and desired side-
band). The difference product of about 9MHz is used for the 2nd IF, allowing a wide variety of
Inrad crystal filters to be used. Transformer T4 boosts the 50 ohm output impedance of the
mixer up to 1800 ohms while providing a factor of 6 voltage gain. The signal is fed into another
amplifier (Q20, Sheet 3) that is identical to that of the previous stage. R54 and C51 decouple
the buffered AGC voltage from the first stage.
Noise Blanker
The amplified 9MHz output of Q20 drives another Darlington buffer which then drives the
noise blanker circuitry on Sheet 4. The noise blanker is placed ahead of the crystal filters so that
it can detect broadband noise pulses (limited only by the roofing filter). The noise blanker is a
simple 9MHz bandpass filter with an input and output impedance of about 120 ohms having a
group delay of several microseconds, long enough for the IF amplifier, U12, to detect a signal
and generate a blanking pulse just as the signal arrives at NBOUT. Three pulse widths are al-
lowed using control bits NBPWA and NBPWB that are latched into U2 (Sheet 1). Currently,
only the longest pulse width is used since we anticipate future changes to the Noise Blanker cir-
cuit. The NBOnOff bit enables or disables the noise blanker by controlling whether power is
applied to the detection circuit. When unpowered, the gating transistor, Q7, is always off. A
DAC output, NBThr, provides a variable trip point, which is routed into Q8 by resistor R73.
Note that NBThr is derived from either the Squelch control or the NBT1 DACs. Since the FM
receiver does not use the noise blanker, the same control is used for both circuits. NBT1 is not
currently used and is reserved for future use, should a dedicated control for the NB threshold
become available.
Since there is about 8dB of loss in the noise blanker, and up to 15dB of additional loss in the
crystal filters and associated resistive pads, the output of the noise blanker is boosted by high
bandwidth amplifier U25, an Analog Devices AD8000 op-amp in a gain of 11 configuration.
The op-amp has high input impedance, allowing resistors R150 and R151 to set the input im-
pedance to a value that matches the output impedance of the noise blanker, while providing
enough gain to offset the loss in the noise blanker and crystal filters and a low output imped-
ance capable of driving the crystal filters.
Crystal Filters
The crystal filters are plugged into 4 slots on the IF Filter board. Up to four filters can be in-
stalled on the IF Filter board at the 9MHz IF frequency. The first one is an Inrad 2311 6KHz
filter. This provides enough bandwidth for AM reception. The standard filter is a 4-pole 2.4KHz
Inrad model, providing good bandwidth for SSB and CW reception. All filters are switched via
1N914 diodes, and impedance matched on input and output via Minicircuits transformers and
resistive pads (attenuators) . These pads serve several purposes. A portion of the pad is used to
provide DC biasing for the diodes. They also serve to isolate the stages from each other and to
help prevent downstream amplifier byproducts from feeding back into previous amplifiers,
which would cause distortion. Finally, the presence of pads allows the attenuation to be
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