Epiq Solutions Sidekiq Mini PCIe Instructions for use

Sidekiq™ Mini PCIe
RF Transceiver • Low SWaP
HARDWARE USER MANUAL
V1.4 - DECEMBER 03, 2021

Sidekiq™ Mini PCIe | Hardware User Manual
CHANGELOG
Revision Date Description Author
0.1 2014-04-02 Initial version Barry L
0.2 2014-05-02 Updates with substantially more technical details Barry L
0.4 2014-05-09 Added JTAG section Barry L
0.5 2014-05-17
-Corrected reference to SMBus interface on MiniPCIe edge connector (lines aren't
hooked up by default) -Swapped Xilinx/Digilent JTAG header pins on JTAG board
diagram
Barry L
0.6 2014-07-04 Added Sidekiq dimensioned drawing Barry L
0.7 2014-08-11 Updated Sidekiq MiniPCIe pinout to specify preferred GPIO signals between host
and Sidekiq, as well as preferred PPS signal between host and Sidekiq Barry L
0.8 2015-09-03 -Added specs for external ref clock input -Updated example power consumption
numbers to match RevC hardware -Added electrical specification table Barry L
0.9 2017-11-02
-Updated section 8.3 to include component temperature ratings -Added section 10.4
discussing thermal dissipation recommendations -Updated Table 3 (MiniPCIe pinout)
to include FPGA I/O pins reserved for use by Dropkiq HF/VHF low frequency
extension card -Added section 10.6 to clarify use of internal vs external reference
clocks -Added section 10.7 discussing the maximum RF input power levels -Updated
power consumption info
Barry L
1.0 2018-05-28
-Updated figure 2 by adding accelerometer axis orientation & temperature sensor
location -Added section 9.8 accel & temp sensor device part numbers -Added
nominal tolerance of the 3.3V rail to section 10.3 -Updated section 9.5 External
1PPS Input, 2.5V logic-level -Added libsidekiq handles / RF port mapping
information tosections 9.1, 9.2, and created table 2 -Updated section 9.6, table 3
input level 0dBm -Updated section 8.2 Gain Control Range -Added description to
table 4, pin#52 -Added doc hyper-links & updated URLs. -Updated Windows OS info
in sections 10.1.2 & 10.5 -Added Appendix A
Barry L
1.1 2019-08-27 Updated table 3, added Appendix B Barry L
1.2 2020-02-25 Added section 12, updated Appendix A Barry L
1.3 2020-09-03 Markdown conversion, updated JTAG section Barry L
1.4 2021-12-03 Added NUC 8 and NUC 11 GPIO tables, format cleanup Barry L

Sidekiq™ Mini PCIe | Hardware User Manual
DISCLAIMER
Epiq Solutions is disclosing this document (“Documentation”) as a general guideline for development. Epiq
Solutions expressly disclaims any liability arising out of your use of the Documentation. Epiq Solutions
reserves the right, at its sole discretion, to change the Documentation without notice at any time. Epiq
Solutions assumes no obligation to correct any errors contained in the Documentation, or to advise you of any
corrections or updates. Epiq Solutions expressly disclaims any liability in connection with technical support or
assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS
DISCLOSED TO YOU “AS IS” WITH NO WARRANTY OF ANY KIND. EPIQ SOLUTIONS MAKES NO
OTHER WARRANTIES, WHETHER EXPRESSED, IMPLIED, OR STATUTORY, REGARDING THE
DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY RIGHTS. IN NO EVENT WILL
EPIQ SOLUTIONS BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR
INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR
USE OF THE DOCUMENTATION.

Sidekiq™ Mini PCIe | Hardware User Manual
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TABLE OF CONTENTS
Introduction
Legal Considerations
Proper Care and Handling
Overview
References
Terms and Definitions
System Overview
Hardware Specification
RF Receiver Specification
RF Transmitter Specification
Hardware Specification
Hardware Interfaces
Rx1
Tx1 / Rx2
User LED #1
User LED #2
External 1PPS Input
External Reference Clock Input
Primary Thermal Relief (RF Shield)
Sidekiq Accelerometer & Temperature Sensor
MiniPCIe Edge Connector
Basic Usage in a Host System
Host System Compatibility
BIOS Compatibility
Operating System Compatibility
Signaling Interfaces
RF Interfaces
System Interface Options
MiniPCIe Slot
Expresscard Slot
PCIe Slot
Power Consumption
Thermal Dissipation
Proper Detection of Sidekiq in a Host System
Internal/External Reference Clock Options
Maximum RF Power Input at RF Input Connector
Support for Host System Sleep/Hibernation

Sidekiq™ Mini PCIe | Hardware User Manual
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JTAG Access on Sidekiq
JTAG Board Usage Notes
Sidekiq Mechanical Outline
Sidekiq NUC Platform Development Kit (PDK)
Sidekiq NUC PDK Overview
Sidekiq NUC PDK Setup
Sidekiq NUC RF Ports
Sidekiq NUC GPIO Connector
Sidekiq NUC JTAG Connector
Accessing Sidekiq NUC JTAG Connector
Appendix A – Sidekiq Statement of Volatility
Appendix B – Failure Rate & MTBF

Sidekiq™ Mini PCIe | Hardware User Manual Introduction
Epiq Solutions Proprietary Page 6
This document provides an overview of Epiq Solutions' Sidekiq SDR [1], a MiniPCIe card with
integrated RF tuner, FPGA, and PCIe/USB interfaces to a host. The following topics will be
discussed:
Overview of the Sidekiq hardware and available interfaces
Sidekiq usage/integration options
Sidekiq JTAG breakout board usage
Sidekiq NUC Platform Development Kit (PDK)
All documentation and support for Sidekiq is provided through Epiq Solutions' support website [2],
which can be found at:
https://support.epiqsolutions.com
Please note that it is necessary to register prior to accessing the relevant information for your
purchase.
INTRODUCTION

Sidekiq™ Mini PCIe | Hardware User Manual Legal Considerations
Epiq Solutions Proprietary Page 7
The Sidekiq is distributed all over the world. Each country has its own laws governing reception and
transmission of radio frequencies. The user of the Sidekiq and associated software is solely
responsible for insuring that it is used in a manner consistent with the laws of the jurisdiction in
which it is used. Many countries, including the United States, prohibit the transmission and reception
of certain frequency bands, or receiving certain transmissions without proper authorization. Again,
the user is solely responsible for the user's own actions.
LEGAL CONSIDERATIONS

Sidekiq™ Mini PCIe | Hardware User Manual Proper Care and Handling
Epiq Solutions Proprietary Page 8
The Sidekiq unit is fully tested by Epiq Solutions before shipment, and is guaranteed functional at
the time it is received by the customer, and ONLY AT THAT TIME. Improper use of the Sidekiq unit
can cause it to become non-functional. In particular, a list of actions that may cause damage to the
hardware include the following:
Handling the unit without proper static precautions (ESD protection) when the housing is
removed or opened up
Inserting or removing Sidekiq from a host system when power is applied to the host system
Connecting a transmitter to the RX port without proper attenuation
A max input of -10 dBm is recommended
Executing custom software and/or an FPGA bitstream that was not developed according to
guidelines
The above list is not comprehensive, and experience with the appropriate measures for handling
electronic devices is required.
PROPER CARE AND HANDLING

Sidekiq™ Mini PCIe | Hardware User Manual Overview
Epiq Solutions Proprietary Page 9
This guide provides an overview of the Sidekiq software defined radio hardware platform, associated
capabilities, and basic usage. This includes the following:
System level block diagram of the platform
Overview of the externally accessible hardware ports
Powering the system up and down
All documentation and support for Sidekiq is provided through Epiq Solutions' support website [2]
which can be found at: https://support.epiqsolutions.com
Please note that it is necessary to register prior to accessing the relevant information for your
purchase.
OVERVIEW

Sidekiq™ Mini PCIe | Hardware User Manual References
Epiq Solutions Proprietary Page 10
1. Sidekiq Product Page
https://epiqsolutions.com/rf-transceiver/sidekiq
2. Epiq Solutions Support Page
https://suppport.epiqsolutions.com
3. Lenovo Group, Ltd
https://lenovo.com
4. Dell, Inc
https://dell.com
5. Expresscard Wikipedia Page
https://en.wikipedia.org/wiki/ExpressCard
6. Expresscard-to-MiniPCIe Adapter Product Page
https://www.mfactors.com/products/PE3B-252d-Mini-PCIe-Card-to-ExpressCard-adapter.html
7. Sidekiq FPGA Developer's Manual
https://epiqsolutions.com/downloads/sidekiq-mini-pcie/
8. Berquist Thermal Gap Pad Material
https://www.henkel-adhesives.com/us/en/products/thermal-management-materials.html
REFERENCES

Sidekiq™ Mini PCIe | Hardware User Manual Terms and Definitions
Epiq Solutions Proprietary Page 11
Term Definition
A/D Analog to Digital converter
COTS Commercial Off The Shelf
D/A Digital to Analog converter
dB Decibel
dBm Decibels referenced to one milliwatt (mW)
ESD ElectroStatic Discharge
FPGA Field Programmable Gate Array
GHz gigaherz
GPIO General Purpose Input / Output (I/O)
GPS Global Positioning System
HSC Murata brand of micro-miniature RF coax connector, manufactured for use as the antenna interface on M.2
cards
IF Intermediate Frequency
I/Q In-Phase / Quadrature Phase
JTAG Joint Test Action Group
kHz kilohertz
LED Light Emitting Diode
MHF4 Micro miniature RF coax connector, manufactured for use as the antenna interface on M.2 cards
MHz megahertz
MIMO Multiple Input Multiple Output
ms millisecond
PDK Platform Development Kit
PPS Pulse Per Second
PPM Parts Per Million
RF Radio Frequency
Rx Receive
SDK Software Development Kit
SDR Software Defined Radio
TCVCXO Temperature Compensated Voltage Controlled Crystal Oscillator
TERMS AND DEFINITIONS

Sidekiq™ Mini PCIe | Hardware User Manual Terms and Definitions
Epiq Solutions Proprietary Page 12
TDD Time-division duplex
Tx Transmit
UART Universal Asynchronous Receiver Transmitter
USB Universal Serial Bus
W.FL Micro-Miniature RF coaxial connector manufactured by Hirose
Table 1: Terms and Definitions

Sidekiq™ Mini PCIe | Hardware User Manual System Overview
Epiq Solutions Proprietary Page 13
Sidekiq is a miniature software defined radio card in a MiniPCIe form factor, providing a flexible
wideband RF transceiver that can be used by a host system. The features of the platform include the
following:
RF transceiver covering 70 MHz to 6 GHz, with independent Tx and Rx frequencies
Supports RF channel bandwidths up to 50 MHz
A/D and D/A quadrature sample rates from 200 Ksamples/sec up to 61.44 Msamples/sec, with
12-bit precision
User programmable FPGA for signal processing applications (Xilinx Spartan 6 LX45-T, part #
XC6SLX45T-3CSG324I)
SPI flash for storage and automatic FPGA bitstream loading at boot-up (Micron N25Q032A11)
On-board 40 MHz TCVCXO, with support for external reference clock input
8051-compatible microcontroller providing a USB 2.0 high speed interface to the host platform
(Cypress FX2-based CY7C68053)
PCIe x1 interface to the host platform
Support for external 1PPS input signal for sample time alignment across multiple Sidekiq units
Dimensions: 30mm x 51mm x 5mm
Weight: 8 grams
Power: ~2 W (application dependent)
Two different versions of Sidekiq are available:
SKIQ-001 supports operation as a two-channel phase coherent RF receiver, or as a 1x1 RF
transceiver (with one RF receiver and one RF transmitter)
SKIQ-002 supports operation as a 1x1 RF transceiver (with one RF transmitter and one RF
receiver)
For the purposes of this document, the remaining documentation will be in reference to SKIQ-001. A
block diagram of Sidekiq is shown in the figure below.
SYSTEM OVERVIEW

Sidekiq™ Mini PCIe | Hardware User Manual System Overview
Epiq Solutions Proprietary Page 14
Figure 1: Block diagram of the Sidekiq MiniPCIe card

Sidekiq™ Mini PCIe | Hardware User Manual Hardware Specification
Epiq Solutions Proprietary Page 15
RF Input U.FL miniature coaxial connector (50 ohms)
Architecture Zero-IF (direct conversion)
Tuning Range 70 MHz to 6 GHz
Tuning Step Size ~2.4 Hz
Tuning Time ~1 mS
Typical Noise Figure 8 dB
Typical IIP3 -10 dBm
Max RF Input Power Level See Maximum RF Power Input in RF Input Connector section
Gain Control Range 0 to 76 dB, 1 dB steps
A/D Converter Sample Rate 200 Ksamples/sec to 61.44 Msamples/sec
A/D Converter Sample Width 12 bits
Typical I/Q balance > 60 dB
On-board Reference Clock 40 MHz, +/- 1PPM accuracy (shared with Tx)
Table 2: RF Receiver Specs
RF Input U.FL miniature coaxial connector (50 ohms)
Architecture Zero-IF (direct conversion)
Tuning Range 70 MHz to 6 GHz
Tuning Step Size ~2.4 Hz
Tuning Time ~1 mS
Gain Control Range 0 to 89.75 dB, 0.25 dB steps
RF Output Power +13 dBm < 2 GHz, +10 dBm above 2 GHz
D/A Converter Sample Rate 200 Ksamples/sec to 61.44 Msamples/sec
D/A Converter Sample Width 12 bits
HARDWARE SPECIFICATION
RF RECEIVER SPECIFICATION
RF TRANSMITTER SPECIFICATION

Sidekiq™ Mini PCIe | Hardware User Manual Hardware Specification
Epiq Solutions Proprietary Page 16
Typical I/Q balance > 60 dB
On-board Reference Clock 40 MHz, +/- 1PPM accuracy (shared with Rx)
Table 3: RF Transmitter Specs
FPGA Xilinx Spartan-6 LX45T (speed grade “-3I”) with x1 PCIe interface to host
USB Cypress FX2 microcontroller with USB 2.0 high-speed interface to host
FPGA
Reprogramming Over USB or PCIe
Accelerometer 3-axis
Temperature
Sensor -55 deg C to +125 deg C (+/- 2 deg C resolution)
Component
Temperature Rating
-30 deg C* to + 85 deg C *Operation down to -40 deg C is supported, though the TCVCXO will
operate outside of the +/- 1PPM accuracy specification.
Table 4: Hardware Specs
HARDWARE SPECIFICATION

Sidekiq™ Mini PCIe | Hardware User Manual Hardware Interfaces
Epiq Solutions Proprietary Page 17
Sidekiq provides a variety of different hardware interfaces for use by an end user. Each of these
hardware interfaces is shown below.
Figure 2: Annotated diagram of Sidekiq hardware I/O interfaces
The Rx1 interface is a U.FL jack connector that provides an RF input path for the primary RF
receiver in Sidekiq. U.FL is the standard interface utilized by MiniPCIe cards, and thus many host
systems supporting MiniPCIe are already pre-wired with antennas that terminate with a U.FL plug
connector. This Rx port supports RF input frequencies between 70 MHz and 6 GHz. The libsidekiq
software library RxA1 handle (sidekiq_rx_hdl_A1) is mapped to the Rx1 interface.
HARDWARE INTERFACES
RX1
TX1 / RX2

Sidekiq™ Mini PCIe | Hardware User Manual Hardware Interfaces
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The Tx1 / Rx2 interface is a U.FL jack connector that provides access to either the primary RF
transmitter or the secondary RF receiver in Sidekiq. U.FL is the standard interface utilized by
MiniPCIe cards, and thus many host systems supporting MiniPCIe are already pre-wired with
antennas that terminate with a U.FL plug connector. This port supports RF frequencies between 70
MHz and 6 GHz. The libsidekiq software API provides the facility for selecting whether this port is
configured for reception or transmission, and sets an on-board RF switch appropriately.
This port can provide access to both Tx1 (sidekiq_tx_hdl_A1) and Rx2 (sidekiq_rx_hdl_A2), where
the operating mode can be selected through software. The ability to switch between Tx and Rx on
this antenna port is controlled from the FPGA, and is accessible via the libsidekiq software library.
Handle RF Port
skiq_rx_hdl_A1 skiq_rf_port_Jxxx_RX1
skiq_rx_hdl_A2 skiq_rf_port_Jxxx_TX1RX2
skiq_tx_hdl_A1 skiq_rf_port__Jxxx_TX1RX2
Table 5: RF Port Mapping introduced in libsidekiq v4.6.0
The User LED #1 provides a visual status indicator that can be controlled through the libsidekiq
software API. By default, this LED is used to provide an indication that a PCIe link has been
successfully negotiated between the host CPU and the FPGA on Sidekiq. When this LED is
illuminated, a link has been established. When the LED is not illuminated, a link is not established.
During FPGA reprogramming, PCIe link is lost and then re-established after the bitstream has been
successfully loaded.
The User LED #2 provides a visual status indicator that can be controlled through the libsidekiq API.
By default, this LED is used to provide an indication that the FPGA has successfully loaded and is
running an FPGA bitstream.
The External 1PPS Input interface is a W.FL jack connector that allows an external 1PPS signal to
be brought in to the on-board FPGA (2.5V logic-level) on Sidekiq for use in time synchronization. A
USER LED #1
USER LED #2
EXTERNAL 1PPS INPUT

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maximum of 3.3V can be safely applied to this input port. This 1PPS input is optional. Note: Since
this signal is routed directly into the on-board FPGA, it is possible to also use this signal as a general
purpose input. Contact Epiq Solutions for details of alternate usage of this port.
The External Reference Clock Input interface is a W.FL jack connector that allows an external 40
MHz reference clock to be brought in to Sidekiq and utilized instead of the default on-board 40 MHz
TCVCXO. This provides the facility to have multiple Sidekiq cards share a common external 40 MHz
reference clock. Note: On RevB Sidekiq cards, a hardware modification (resistor swap) is required to
disable the on-board 40 MHz TCVCXO, and to accept the external 40 MHz reference clock input.
Contact Epiq Solutions for details. RevC Sidekiq and beyond provide a means to switch between the
on-board reference clock and external reference clock through the libsidekiq software API.
The electrical specification for this input signal is defined below.
Input Level 0.8 – 1.3 Vpp, 0 dBm max from 50 ohm source
Input Impedance AC-Coupled high impedance
Frequency 40 MHz
Waveform Square or Sinewave
Connector Type W.FL
Table 6: Electrical specification for external reference clock input
The RF shield (used to minimize the effects of RF noise entering the RF front end) serves as the
primary thermal relief path for heat dissipation in the system. Underneath the shield, thermal gap
pad material is used to transfer heat from components to the shield itself, yielding a minimal thermal
resistance. If no air flow is available in the host system where Sidekiq is being integrated, it is highly
recommended that the user provide a thermal dissipation path from this shield to a thermally
conductive surface in the host system, such as a metal back plate or other metal housing. The use
of thermal gap pad material [8] can provide a flexible yet efficient thermal path between the RF
shield and the host system.
In addition to the RF shield, the other primary component generating heat in Sidekiq is the Xilinx
Spartan 6 FPGA (which is located right next to the RF shield). If an end user is developing a thermal
dissipation path for the RF shield, it is also recommended to include the FPGA in the thermal
EXTERNAL REFERENCE CLOCK INPUT
PRIMARY THERMAL RELIEF (RF SHIELD)

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transfer path as well. Similar to the RF shield, use of a thermal gap pad material can be very
effective in ensuring good thermal conductivity between this component and the host system.
The Sidekiq is equipped with temperature and accelerometer devices.
Analog Devices 3-Axis Accelerometer ADXL346ACCZ
Texas Instruments Temperature Sensor TMP103AYFFR
Please refer to the annotated diagram for the Sidekiq accelerometer axis orientation & temperature
sensor location.
The libsidekiq software API provides access to these peripherals, test applications read_accel and
read_temp are included with the sidekiq software.
Additional information can be found in the Sidekiq Software Development manual.
The MiniPCIe Edge Connector is used to route various signals between the MiniPCIe host system
and the Sidekiq card. A complete table enumerating the pins and their usage on Sidekiq is shown in
the following table.
Pin
#
MiniPCIe
Pin
Name
Description as used in Sidekiq Pin
#
MiniPCIe
Pin Name
Description as used in
Sidekiq
1 WAKE_ Wakeup signal routed to both FX2 as well as FPGA
(pin N18, 2.5V I/O) 27 GND Ground
2 +3.3Vaux +3.3V supply 28 1.5V Unused (floating)
3 COEX1
-GPIO routed to FPGA pin J7, 2.5V I/O -Used as
RESET_ signal for Dropkiq HF/VHF low frequency
extension card
29 GND Ground
4 GND Ground 30 SMB_CLK
Not connected by
default (to prevent I2C
address conflicts with
host)
5 COEX2 GPIO routed to FPGA pin J6, 2.5V I/O 31 PETn0
PCIe differential
transmit lane 0, negative
leg
SIDEKIQ ACCELEROMETER & TEMPERATURE SENSOR
MINIPCIE EDGE CONNECTOR