Espressif Systems ESP32 Series Instruction Manual

ESP32 Hardware Design Guidelines
Version 2.1
Espressif Systems

About This Guide
The guidelines outline recommended design practices when developing standalone or add-on systems based on
the ESP32 series of products, including ESP32, the ESP32-WROOM-32(ESP-WROOM-32) module, and ESP32-
DevKitC — the development board.
About This Guide
This document provides the specifications of ESP32 hardware.
Revision History
For the revision history of this document, please refer to the last page.
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Disclaimer and Copyright Notice
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PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
ITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this docu-
ment is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights
are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.
Copyright © 2018 Espressif Inc. All rights reserved.

Contents
1 Overview 6
2 Schematic Checklist and PCB Layout Design 7
2.1 Schematic Checklist 7
2.1.1 Power Supply 8
2.1.1.1 Digital Power Supply 8
2.1.1.2 Analog Power Supply 8
2.1.2 Power-on Sequence and System Reset 9
2.1.2.1 Power-on Sequence 9
2.1.2.2 Reset 10
2.1.3 Flash 10
2.1.4 Crystal Oscillator 10
2.1.4.1 External Clock Source (Compulsory) 10
2.1.4.2 RTC (Optional) 12
2.1.5 RF 12
2.1.6 ADC 12
2.1.7 External Capacitor 13
2.1.8 UART 13
2.2 PCB Layout Design 14
2.2.1 Standalone ESP32 Module 14
2.2.1.1 General Principles of PCB Layout 14
2.2.1.2 Positioning a ESP32 Module on a Base Board 15
2.2.1.3 Power Supply 16
2.2.1.4 Crystal Oscillator 17
2.2.1.5 RF 18
2.2.1.6 External RC 19
2.2.1.7 UART 19
2.2.1.8 Touch Sensor 19
2.2.2 ESP32 as a Slave Device 20
2.2.3 Typical Layout Problems and Solutions 21
2.2.3.1 Q: The current ripple is not large, but the Tx performance of RF is rather poor. 21
2.2.3.2 Q: The power ripple is small, but RF Tx performance is poor. 22
2.2.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 22
2.2.3.4 Q: Tx performance is not bad, but the Rx sensitivity is low. 22
3 Hardware Development 23
3.1 ESP32-PICO-D4 Module 23
3.2 ESP32-WROOM-32(ESP-WROOM-32) Module 23
3.3 ESP32-WROOM-32D(ESP-WROOM-32D) Module 24
3.4 ESP32-WROOM-32U Module 24
3.5 ESP32-WROVER Module 25
3.6 Notes on Using Modules 26
3.7 ESP32-DevKitC Development Board 26

3.8 ESP-WROVER-KIT Development Board 27
4 Applications 29
4.1 UART to Wi-Fi Smart Device 29
4.2 ESP32-PICO-KIT Mini Development Kit 29
4.3 ESP32-LyraT Smart Audio Platform 29

List of Tables
1 Pin Definition of UART Interfaces 29

List of Figures
1 ESP32 Schematics 7
2 ESP32 Digital Power Supply Pins 8
3 ESP32 Analog Power Supply Pins 9
4 ESP32 Flash 10
5 ESP32 Crystal Oscillator 11
6 ESP32 Crystal Oscillator (RTC) 12
7 ESP32 RF Matching Schematics 12
8 ESP32 External Capacitor 13
9 ESP32 UART 13
10 ESP32 PCB Layout 14
11 ESP32 Module Antenna Position on Base Board 15
12 Keepout Zone for ESP32 Module’s Antenna on the Base Board 16
13 ESP32 Power Supply Design 17
14 ESP32 Crystal Oscillator Layout 18
15 ESP32 RF Layout 18
16 A Typical Touch Sensor Application 19
17 Electrode Pattern Requirements 20
18 Sensor Track Routing Requirements 20
19 PAD/TV Box Layout 21
20 ESP32-PICO-D4 Module 23
21 ESP32-WROOM-32(ESP-WROOM-32) Module 24
22 ESP32-WROOM-32D(ESP-WROOM-32D) Module 24
23 ESP32-WROOM-32U Module 25
24 ESP32-WROVER Module 25
25 Front Side of ESP32-DevKitC 27
26 Front Side of the ESP-WROVER-KIT Layout 27
27 Rear Side of the ESP-WROVER-KIT Layout 28

1. OVERVIEW
1. Overview
ESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip designed with TSMC ultra-low-power 40 nm technol-
ogy. It is designed to achieve the best power and RF performance, robustness, versatility, and reliability in a wide
variety of applications and different power profiles.
ESP32 is a highly-integrated solution for Wi-Fi + Bluetooth applications in the IoT industry with around 20 external
components. ESP32 integrates the antenna switch, RF balun, power amplifier, low noise receive amplifier, filters,
and power management modules. As such, the entire solution occupies minimal Printed Circuit Board (PCB)
area.
ESP32 uses CMOS for single-chip fully-integrated radio and baseband, and also integrates advanced calibration
circuitries that allow the solution to dynamically adjust itself to remove external circuit imperfections or adjust to
changes in external conditions. As such, the mass production of ESP32 solutions does not require expensive and
specialized Wi-Fi test equipment.
The ESP32 series of chips include ESP32-D0WDQ6, ESP32-D0WD, ESP32-D2WD and ESP32-S0WD. For details
of part number and ordering information, please refer to ESP32 Datasheet.
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
2. Schematic Checklist and PCB Layout Design
ESP32’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash
memory chip. ESP32 integrates the complete transmit/receive RF functionality including the antenna switches, RF
balun, power amplifier, low noise receive amplifier, filters, power management module, and advanced calibration
circuitries.
ESP32’s high integration allows for simple peripheral circuit design. This document details ESP32 schematics and
PCB layout design.
While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.
2.1 Schematic Checklist
ESP32 schematics is as shown in Figure 1.
CHIP_PU
GPIO35
SCK/CLK
SCS/CMD
SENSOR_VP
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
SENSOR_VN
GPIO34
GPIO32
U0TXD
GPIO33
GPIO25
GPIO26 GPIO27 GPIO14 GPIO12 GPIO15 GPIO13 GPIO2 GPIO0 GPIO4
GPIO16
GPIO17
SDO/SD0
SDI/SD1
SCK/CLK
SWP/SD3
SCS/CMD
SHD/SD2
GPIO18
GPIO5
GPIO23
GPIO19
GPIO22
U0RXD
GPIO21
CHIP_PU
VDD33
GND
VDD33
VDD33
GND
GND
VDD_SDIO
VDD33
GND
GND
GND
GNDGND
GND
GND
GND
VDD_SDIO
VDD33
GND
GNDGND
GND
GND
GND
GND GND
GNDGND
VDD33
GND
C18
1uF
C14
2.7pF±0.1pF
R1 20K
C13
10uF
C22
0.1uF
C5
10nF
C21
NC
L5 2.0nH
C9
0.1uF
C2
22pF
R2 0R
C15
2.0pF±0.1pF
L4 2.7nH±0.1nH
C10
0.1uF
C17
270pF(NC)
C6 3.3nF
C20
1uF
C16
270pF(NC)
C3
100pF
R4
10K
C4
0.1uF
ANT1
PCB ANT
1
2
C11
1uF
C12
NC
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C19
0.1uF
R3 499R
U2 ESP32
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
GPIO26
15
GPIO27
16
MTMS
17
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
GND 49
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39 GPIO21 42
VDD3P3_CPU 37
CAP1 48
VDDA 46
U0RXD 40
C1
22pF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
Figure 1: ESP32 Schematics
Any basic ESP32 circuit design may be broken down into seven major sections:
• Power supply
• Power-on sequence and system reset
• Flash
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
• Crystal oscillator
• RF
• External capacitors
• UART
2.1.1 Power Supply
For further details of using the power supply pins, please refer to Section 2.3 Power Scheme in ESP32 Datasheet.
2.1.1.1 Digital Power Supply
Pin19 and Pin37 are the power supply pins for RTC and CPU, respectively. The digital power supply operates in
a voltage range of 1.8V ~3.6V. We recommend adding extra filter capacitors of 0.1 µF close to the digital power
supply pins.
The voltage of VDD_SDIO is produced by the internal LDO. It can be used as the power supply for the external
circuitry, with a maximum current of about 40 mA when using the 3.3V LDO. When the VDD_SDIO outputs 1.8V,
the value of GPIO12 should be set to 1 when the chip boots. The user can add a 1 µF filter capacitor close to
VDD_SDIO. When the VDD_SDIO outputs 3.3V, the value of GPIO12 is 0 (default) when the chip boots and it is
recommended that users add 2 kΩresistor to ground and a 1 µF capacitor close to VDD3P3_RTC.
When using VDD_SDIO as the power supply pin for the external 3.3V flash/PSRAM, the supply voltage should be
2.7V or above, so as to meet the requirements of flash/PSRAM’s working voltage.
GPIO12
GPIO15 GPIO13 GPIO2 GPIO0 GPIO4
GPIO16
GPIO17
SDO/SD0
SDI/SD1
SCK/CLK
SWP/SD3
SCS/CMD
SHD/SD2
GPIO18
GPIO5
GPIO23
GPIO19
GND
VDD33
GND
VDD_SDIO
VDD33
GND
C18
1uF
C4
0.1uF
C19
0.1uF
ESP32
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
VDDA 43
XTAL_N
44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39 GPIO21 42
VDD3P3_CPU 37
U0RXD 40
Figure 2: ESP32 Digital Power Supply Pins
2.1.1.2 Analog Power Supply
Pin1, Pin43 and Pin46 are the analog power supply pins. Pin3 and Pin4 are the power supply pins for the power
amplifiers. It should be noted that the sudden increase in current draw, when ESP32 is in transmission mode, may
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
cause a power rail collapse. Therefore, it is highly recommended to add another 10 µF capacitor to the power
trace, which can work in conjunction with the 0.1 µF capacitor. LC filter circuit needs to be added to near the
power pin so as to suppress high-frequency harmonics. The inductor’s rated current is preferably 500 mA and
above.
SENSOR_VP
VDD33
GND
VDD33
VDD33
GND
GND
GND
GNDGND
GND
GND
GNDGND
R1 20K
C14
2.7pF±0.1pF
C13
10uF
C5
10nF
C9
0.1uF
L5 2.0nH
C21
NC
C15
2.0pF±0.1pF
R2 0R
C10
0.1uF
L4 2.7nH±0.1nH
C16
270pF(NC)
C20
1uF
C6 3.3nF
C3
100pF
ANT1
PCB ANT
1
2
C12
NC
C11
1uF
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
6
GND 49
CAP2 47
VDDA
43
XTAL_N 44
XTAL_P 45
GPIO21 42
CAP1 48
VDDA 46
Figure 3: ESP32 Analog Power Supply Pins
Notice:
• The recommended voltage of the power supply for ESP32 is 3.3V, and its recommended output current
is 500 mA or more.
• It is suggested that users add an ESD tube at the power entrance.
2.1.2 Power-on Sequence and System Reset
2.1.2.1 Power-on Sequence
ESP32 uses a 3.3V system power supply. The chip should be activated after the power rails have stabilized. This is
achieved by delaying the activation of CHIP_PU (Pin9) by time T after the 3.3V rails have been brought up. The rec-
ommended delay time (T) is given by the parameter of the RC(R = 10 kΩ, C = 0.1 µF) circuit. For reference design,
please refer to Figure ESP-WROOM-32 Peripheral Schematics in the ESP-WROOM-32 Datasheet.
Notice:
If CHIP_PU is driven by a power management chip, then the power management chip controls the
ESP32 power state. When the power management chip turns on/off Wi-Fi through the high/low level
on GPIO, a pulse current may be generated. To avoid level instability on CHIP_PU, an RC delay (R = 10
kΩ, C = 0.1 µF) circuit is required.
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2.1.2.2 Reset
CHIP_PU serves as the reset pin of ESP32. ESP32 will reset when CHIP_PU is held low and the input level is
below 0.6V and stays for at least 200 µs. To avoid reboots caused by external interferences, the CHIP_PU trace
should be as short as possible and routed away from the clock lines. A pull-up resistor and a ground capacitor
are highly recommended.
Notice:
CHIP_PU pin must not be left floating.
2.1.3 Flash
ESP32 can support up to four 16 MB external QSPI flash and SRAM chips. The demo flash used currently is an
SPI flash with 4 MB ROM, in an SOP8 (208 mil) package. The VDD_SDIO acts as the power supply pin. Make
sure you select the appropriate flash according to the power voltage on VDD_SDIO. Users can add a serial resistor
to Pin21 SD_CLK and connect it to the flash CLK pin.
SCK/CLK
SCS/CMD
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
GPIO16
GPIO17
SHD/SD2
SWP/SD3
SCS/CMD
SCK/CLK
SDO/SD0
SDI/SD1
GPIO5
GPIO18
GPIO23
GPIO19
GND
VDD_SDIO
GND
VDD_SDIO
GND
VDD33
C18
1uF
C4
0.1uF
ESP32_5x5
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
GPIO23 36
VDD3P3_CPU 37
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
Figure 4: ESP32 Flash
2.1.4 Crystal Oscillator
There are two clock sources for the ESP32, that is, an external crystal oscillator clock source and an RTC clock
source.
2.1.4.1 External Clock Source (Compulsory)
In circuit design, capacitors C1 and C2 which connect to the ground are added to the input and output terminals
of the crystal oscillator respectively. The specific capacitive values depend on further testing of, and adjustment
to, the overall performance of the whole circuit. It is recommended that users reserve a series resistor of 0Ωon
the XTAL_P clock trace. Note that the accuracy of the selected crystal is ± 10 PPM.
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
GNDGND
GND
GND
20K
C2
22pF
R2 0R
3.3nF
R3
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C1
22pF
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
U0TXD 41
GPIO22 39 GPIO21 42
CAP1
VDDA 46
U0RXD 40
Figure 5: ESP32 Crystal Oscillator
Notice:
Defects in the craftsmanship of the crystal oscillators (for example, high frequency deviation) and unsta-
ble operating temperature may lead to the malfunction of ESP32, resulting in a decrease of the overall
performance.
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2.1.4.2 RTC (Optional)
ESP32 supports an external 32.768 kHz crystal oscillator to act as the RTC sleep clock.
GPIO35
GPIO32
GPIO33
GPIO25
C23 12pF
U4
32kHz
XTAL32_IN 1
XTAL32_OUT
2
C22 12pF
U2
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
Figure 6: ESP32 Crystal Oscillator (RTC)
Notice:
If the RTC source is not required, then Pin12 32K_XP and Pin13 32K_XN can be used as GPIOs.
2.1.5 RF
The output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30+j10) and (35+j10) Ω
respectively. A π-type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network.
CHIP_PU
SENSOR_VP
SENSOR_VN
GND GND
GND
C15
2.0pF
L4 2.7nH
C14
2.7pF
C17
C16
270pF
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
9
ANT1
PCB ANT
1
2
Figure 7: ESP32 RF Matching Schematics
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
2.1.6 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.
• Pins SENSOR_VP or SENSOR_VN will trigger an input glitch lasting for 80 ns once the temperature sensor,
or SARADC1, or SARADC2, or Hall sensor is initialized.
• It is recommended that users avoid using SENSOR_VP or SENSOR_VN as input GPIO when designing the
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
circuit or avoid using them in software.
2.1.7 External Capacitor
The schematics of Pin47 CAP2 and Pin48 CAP1 is shown in Figure 8. C5 (10 nF) that connects to CAP1 should
be of high precision. For the RC circuit between CAP1 and CAP2 pins, please refer to Figure 8. Removing the RC
circuit may slightly affect ESP32 in Deep-sleep mode.
GND
GND
R1 20K
C5
10nF
C6 3.3nF
GND 49
CAP2
47
CAP1 48
VDDA 46
Figure 8: ESP32 External Capacitor
2.1.8 UART
Users need to connect a 499Ωresistor to the U0TXD line in order to suppress the 80 MHz harmonics.
U0TXD
GPIO22
U0RXD
R3 499R
U0TXD
41
GPIO22 39
GPIO21
U0RXD 40
Figure 9: ESP32 UART
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2.2 PCB Layout Design
This chapter introduces the key points of designing ESP32 PCB layout with the example of ESP-WROOM-32D.
The PCB layout design guidelines are applicable to cases when the
• ESP32 module functions as a standalone device, and when the
• ESP32 functions as a slave device.
Figure 10: ESP32 PCB Layout
2.2.1 Standalone ESP32 Module
2.2.1.1 General Principles of PCB Layout
We recommend a four-layer PCB design.
• The first layer is the TOP layer for signal traces and components.
• The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.
• The third layer is the POWER layer. It is acceptable to route signal traces on this layer, provided that there is
a complete GND plane under the RF and crystal oscillator.
• The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.
Below are the suggestions for a two-layer PCB design.
• The first layer is the TOP layer for signal traces and components.
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
• The second layer is the BOTTOM layer, where power traces are routed. Placing any components on this
layer is not recommended. Do not route any power or signal traces under or around the RF and crystal
oscillator, so that there is a complete GND plane, which is connected to the Ground Pad at the bottom of
the chip.
2.2.1.2 Positioning a ESP32 Module on a Base Board
If users adopt on-board design, they should pay attention to the layout of the module on the base board. The inter-
ference of the base board on the module’s antenna performance should be reduced as much as possible.
It is recommended that the PCB antenna area of the module be placed outside the base board while the module
be put as close as possible to the edge of the base board so that the feed point of the antenna is closest to the
board.
Base Board
1 2 3
4
5
Figure 11: ESP32 Module Antenna Position on Base Board
Note:
As is shown in Figure 11, the recommended position of ESP32 module on the base board should be:
• Position 3: Highly recommended;
• Position 4: Recommended;
• Position 1, 2, 5: Not recommended.
If the positions recommended are not suitable, please make sure that the module is not covered by any metal
shell. The antenna area of the module and the area 15 mm outside the antenna should be kept clean, (namely no
copper, routing, components on it) as shown in the Figure 12:
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
15 mm
15 mm
Base Board
15 mm
Clearance
Figure 12: Keepout Zone for ESP32 Module’s Antenna on the Base Board
2.2.1.3 Power Supply
The 3.3V power traces are highlighted in yellow in Figure 13. The width of these power traces should be larger
than 20 mil. Before power traces reach the analog power-supply pins (Pin 1, 3, 4, 43, 46), a 10 µF capacitor is
required, which can work in conjunction with the 0.1 µF capacitor. As Figure 13 shows, C13 (10 µF capacitor)
is placed by the 3.3V stamp hole; C10, L5 and C21 are placed as close as possible to the analog power-supply
pin. If possible, add a 0.1 µF capacitor for every digital power pin. Note that all decoupling capacitors should be
placed close to the power pin, and ground vias should be added adjacent to the ground pin for the decoupling
capacitors to ensure a short return path.
It is good practice to route the power traces on the fourth (bottom) layer. Vias are required for the power traces to
go through the layers and get connected to the pins on the top layer. The diameter of the drill should exceed the
width of the power traces. The diameter of the via pad should be 1.5 times that of the drill.
The center ground pad at the bottom of the chip should be connected to ground plane through at least 9 ground
vias.
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Figure 13: ESP32 Power Supply Design
2.2.1.4 Crystal Oscillator
For the design of the crystal oscillator section, please refer to Figure 14. In addition, the following should be
noted:
• The crystal oscillator should be placed far from the clock pin. The recommended gap is 2.7 mm. It is good
practice to add high-density ground via stitching around the clock trace for containing the high-frequency
clock signal.
• There should be no vias for the clock input and output traces, which means that the traces cannot cross
layers.
• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator and
at the end of the clock trace.
• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The larger the copper area on the top layer is, the better.
• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example, power-switching converter components or unshielded inductors.
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2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
Figure 14: ESP32 Crystal Oscillator Layout
2.2.1.5 RF
The characteristic RF impedance must be 50Ω. The ground plane on the adjacent layer needs to be complete.
Make sure you keep the width of the RF trace consistent, and do not branch the trace. The RF trace should be
as short as possible with dense ground via stitching around it for isolation.
However, there should be no vias for the RF trace. The RF trace should be routed at a 135° angle, or with circular
arcs if trace bends are required.
π-type matching circuitry should be reserved on the RF trace and placed close to the chip.
No high-frequency signal traces should be routed close to the RF trace. The RF antenna should be placed away
from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks (SDIO_CLK), etc.
In addition, the USB port, USB to UART chip, UART signal lines (including traces, vias, test points, header pins, etc.)
must be as far away from the antenna as possible. It is good practice to add ground vias around the UART signal
line. It is recommended that the design of PCB onboard antenna be based on Espressif’s Type-A antenna.
Figure 15: ESP32 RF Layout
Espressif Systems 18 ESP32 Hardware Design Guidelines V2.1

2. SCHEMATIC CHECKLIST AND PCB LAYOUT DESIGN
2.2.1.6 External RC
External resistors and capacitors should be placed close to the chip pins, and there should be no vias around the
traces. Please ensure that 10 nF capacitors are placed close to the pins.
2.2.1.7 UART
The series resistor on the U0TXD line needs to be placed as close as possible to the chip so that the U0TXD traces
on the top layer are as short as possible.
2.2.1.8 Touch Sensor
ESP32 offers up to 10 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or
proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows users to
use touch pads with smaller area to implement the touch detection function. Users can also use the touch panel
array to detect a larger area or more test points.
Figure 16: A Typical Touch Sensor Application
In order to prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system,
the following factors should be taken into account.
Electrode Pattern
The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a hu-
man fingertip is commonly applied. Large size or irregular shape might lead to incorrect responses from nearby
electrodes.
Note:
The examples illustrated in Figure 17 are not of actual scale. It is suggested that users use a human fingertip as reference.
Espressif Systems 19 ESP32 Hardware Design Guidelines V2.1