Espressif Systems ESP32-H2 Series Instruction Manual

PRELIMINARY
ESP32-H2 Series
Hardware Design Guidelines
Introduction
Hardware design guidelines give advice on how to integrate ESP32-H2 into other products.
ESP32-H2 is a series of ultra-low-power SoCs with support for Bluetooth®5 (LE), Bluetooth
Mesh, Thread, Matter and Zigbee.
These guidelines will help to ensure optimal performance of your product with respect to tech-
nical accuracy and conformity to Espressif’s standards.
Pre-release v0.5
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PRELIMINARY
Contents
Contents
1 Overview 5
2 Schematic Checklist 6
2.1 Power Supply 7
2.1.1 Digital Power Supply 7
2.1.2 Analog Power Supply 7
2.2 Power-up Timing and System Reset 8
2.2.1 Power-up Timing 8
2.2.2 System Reset 8
2.2.3 Power-up and Reset Timing 9
2.3 Flash 9
2.4 Clock Source 9
2.4.1 External Clock Source (compulsory) 9
2.4.2 RTC Clock(optional) 11
2.5 RF 11
2.6 UART 12
2.7 Strapping Pins 13
2.8 GPIO 14
2.9 ADC 16
2.10 USB 16
3 PCB Layout Design 17
3.1 General Principles of PCB Layout 17
3.2 Positioning a Module on a Base Board 18
3.3 Power Supply 20
3.4 Crystal 21
3.5 RF 23
3.6 UART 25
3.7 USB 25
3.8 Typical Layout Problems and Solutions 25
3.8.1 Q: The voltage ripple is not large, but the TX performance of RF is rather poor. 26
3.8.2 Q: The voltage ripple is small, but RF TX performance is poor. 26
3.8.3 Q: When ESP32-H2 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 26
3.8.4 Q: TX performance is not bad, but the RX sensitivity is low. 27
4 Hardware Development 28
4.1 ESP32-H2 Modules 28
4.2 ESP32-H2 Development Boards 28
4.3 Download Guidelines 28
5 Related Documentation and Resources 30
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Contents
Glossary 31
Revision History 32
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List of Figures
List of Tables
1 Description of Timing Parameters for Power-up and Reset 9
2 Chip Boot Mode Control 13
3 Description of Timing Parameters for the Strapping Pins 13
4 IO MUX Pin Functions 14
List of Figures
1 ESP32-H2 Schematic 6
2 Schematic for the Digital Power Supply Pins 7
3 Schematic for the Analog Power Supply Pins 8
4 Visualization of Timing Parameters for Power-up and Reset 9
5 Schematic for the Crystal 10
6 Schematic for the RTC Clock 11
7 Schematic for RF Matching 12
8 RF Tuning Diagram 12
9 Visualization of Timing Parameters for the Strapping Pins 14
10 ESP32-H2 PCB Layout 17
11 Placement of ESP32-H2 Modules on Base Board (antenna feed point on the right) 18
12 Placement of ESP32-H2 Modules on Base Board (antenna feed point on the left) 19
13 Keepout Zone for ESP32-H2 Module’s Antenna on the Base Board 20
14 ESP32-H2 Power Traces in a Four-layer PCB Design 20
15 ESP32-H2 Crystal Oscillator Layout (Connected to the Ground) 22
16 ESP32-H2 Crystal Oscillator Layout (Not Connected to the Ground) 23
17 ESP32-H2 RF Layout in a Four-layer PCB Design 23
18 ESP32-H2 PCB Stack up Design 24
19 ESP32-H2 Stub in a Four-layer PCB Design 25
20 ESP32-H2 UART0 Layout 25
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1 Overview
1 Overview
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/sites/default/files/documentation/esp32-h2_hardware_design_guidelines_en.
pdf
ESP32-H2 series is a low-power MCU-based SoC solution that supports Bluetooth®5 (LE), Zigbee 3.0 and
Thread 1.3 (802.15.4). With its state-of-the-art power and RF performance, this SoC is an ideal choice for a wide
variety of application scenarios relating to Internet of Things (IoT), smart home, industrial automation, health care,
and consumer electronics.
ESP32-H2 has a 32-bit RISC-V processor, operating at up to 96 MHz. The chip supports application
development to operate without the need for a host MCU.
ESP32-H2 series provides a highly-integrated way to implement wireless communication technologies using a
complete RF subsystem, including a antenna switch, RF balun, power amplifier, low noise amplifier (LNA), filter,
power management unit, calibration circuits, etc. As a result, PCB size has been greatly reduced.
With its advanced calibration circuitry, ESP32-H2 series can dynamically adjust itself to remove external circuit
imperfections or adapt to changes in external conditions.
For more information about ESP32-H2 series, please refer to ESP32-H2 Series Datasheet.
Note:
Unless otherwise specified, “ESP32-H2” used in this document refers to the series of chips, instead of a specific chip
variant.
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2 Schematic Checklist
2 Schematic Checklist
The integrated circuitry of ESP32-H2 requires only 17 electrical components (resistors, capacitors, and inductors)
and one crystal. The high integration of ESP32-H2 allows for simple peripheral circuit design. This chapter details
ESP32-H2 schematics.
ESP32-H2 schematics are shown in Figure 1.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
When VBAT is powered by external
battery, R2 can be NC.
RF_ANT LNA_IN GPIO27
GPIO0
GPIO2
GPIO3
GPIO1
GPIO4
GPIO5
VBAT
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13
U0RXD
U0TXD
GPIO25
GPIO26
GPIO22
EN
GPIO14
GND
VDD33
GNDGNDGND
GND
GNDGND
GND
GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
VDD33
GND
VDD33
C2
10nF C5
1uF
C7
1uF
C10
0.1uF
C13
0.1uF
C6
10uF
L2 TBD
C1
TBD
R3 499
Y1
32MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C19
0.1uF
ANT1
PCB_ANT
1
2
U1 ESP32-H2
VDD3P3
1
VDD3P3
2
GPIO0
3
GPIO1
4
MTMS
5
MTDO
6
MTCK
7
MTDI
8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30 VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25 24
U0TXD 23
U0RXD 22
GPIO22 21
VDDPST2 20
VDDA_PMU 19
VBAT 18
CHIP_EN 17
C17
0.1uF
C12
TBD
R2 0
C8
0.1uF
C4
TBD
R4 TBD
C11
TBD
Figure 1: ESP32-H2 Schematic
Any basic ESP32-H2 circuit design may be broken down into 10 major sections:
• Power supply
• Power-on sequence and system reset
• Flash
• Clock source
• RF
• UART
• Strapping pins
• GPIO
• ADC
• USB
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The rest of this document details the specifics of circuit design for each of these sections.
2.1 Power Supply
For more information about power pins, please refer to ESP32-H2 Series Datasheet > Section Power Supply.
2.1.1 Digital Power Supply
ESP32-H2 has pin9 VDDPST1 and pin20 VDDPST2 that supply power to Group0 IO and Group1 IO respectively,
in a voltage range of 3.0 V ~3.6 V. It is recommended to add an extra 0.1 µF filter capacitor close to each digital
power supply pin.
The schematic for the digital power supply pins is shown in Figure 2.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
When VBAT is powered by external
battery, R2 can be NC.
RF_ANT LNA_IN GPIO27
GPIO0
GPIO2
GPIO3
GPIO1
GPIO4
GPIO5
VBAT
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13
U0RXD
U0TXD
GPIO25
GPIO26
GPIO22
EN
GPIO14
GND
VDD33
GNDGNDGND
GND
GNDGND
GND
GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
VDD33
GND
VDD33
C2
10nF C5
1uF
C7
1uF
C10
0.1uF
C13
0.1uF
C6
10uF
L2 TBD
C1
TBD
R3 499
Y1
32MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C19
0.1uF
ANT1
PCB_ANT
1
2
U1 ESP32-H2
VDD3P3
1
VDD3P3
2
GPIO0
3
GPIO1
4
MTMS
5
MTDO
6
MTCK
7
MTDI
8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30 VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25 24
U0TXD 23
U0RXD 22
GPIO22 21
VDDPST2 20
VDDA_PMU 19
VBAT 18
CHIP_EN 17
C17
0.1uF
C12
TBD
R2 0
C8
0.1uF
C4
TBD
R4 TBD
C11
TBD
Figure 2: Schematic for the Digital Power Supply Pins
2.1.2 Analog Power Supply
ESP32-H2’s pin1 VDD3P3, pin2 VDD3P3, pin18 VBAT, pin19 VDDA_PMU, pin27 VDD3P3, pin30 VDD3P3 and
pin31 VDD3P3 are the analog power supply pins, working at 3.0 V ~3.6 V.
For pin1 VDD3P3 and pin2 VDD3P3, it should be noted that the sudden increase in current draw, when
ESP32-H2 is transmitting signals, may cause a power rail collapse. Therefore, it is highly recommended to add
another 10 µF capacitor to the power trace, which can work in conjunction with the 1 µF capacitor and the 0.1
µF. Refer to Figure 3and place the appropriate decoupling capacitor near each analog power pin.
If VBAT is powered separately by an external power supply, R2 is not required and the operating voltage range is
3.0 V to 3.6 V.
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
When VBAT is powered by external
battery, R2 can be NC.
RF_ANT LNA_IN GPIO27
GPIO0
GPIO2
GPIO3
GPIO1
GPIO4
GPIO5
VBAT
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13
U0RXD
U0TXD
GPIO25
GPIO26
GPIO22
EN
GPIO14
GND
VDD33
GNDGNDGND
GND
GNDGND
GND
GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
VDD33
GND
VDD33
C2
10nF C5
1uF
C7
1uF
C10
0.1uF
C13
0.1uF
C6
10uF
L2 TBD
C1
TBD
R3 499
Y1
32MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C19
0.1uF
ANT1
PCB_ANT
1
2
U1 ESP32-H2
VDD3P3
1
VDD3P3
2
GPIO0
3
GPIO1
4
MTMS
5
MTDO
6
MTCK
7
MTDI
8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30 VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25 24
U0TXD 23
U0RXD 22
GPIO22 21
VDDPST2 20
VDDA_PMU 19
VBAT 18
CHIP_EN 17
C17
0.1uF
C12
TBD
R2 0
C8
0.1uF
C4
TBD
R4 TBD
C11
TBD
Figure 3: Schematic for the Analog Power Supply Pins
Notice:
• When use the single power supply, the recommended power supply voltage for ESP32-H2 is 3.3 V and the output
current is no less than 350 mA.
• It is suggested to add another 10 µF capacitor at the power entrance. If the power entrance is close to pin1 and
pin2, it can share the same 10 µF capacitor with pin1 and pin2.
• It is suggested to add an ESD protection diode at the power entrance.
2.2 Power-up Timing and System Reset
2.2.1 Power-up Timing
When ESP32-H2 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_EN
is pulled up and the chip is enabled. Therefore, CHIP_EN needs to be powered up after the 3.3 V rails have been
brought up. More details about the power-up timing can be found in Section 2.2.3.
Notice:
To ensure the correct power-up timing, it is advised to add an RC delay circuit at the CHIP_EN pin. The recommended
setting for the RC delay circuit is usually R = 10 kΩand C = 1 µF. However, specific parameters should be adjusted based
on the characteristics of the actual power supply and the power-up and reset timing sequence of the chip.
2.2.2 System Reset
CHIP_EN serves as the reset pin of ESP32-H2. When CHIP_EN is at low level, the reset voltage (VIL_nRST )
should be in the range of (–0.3 ~0.25 × VDD) V. To avoid reboots caused by external interferences, make the
CHIP_EN trace as short as possible. Also, add a pull-up resistor as well as a capacitor to ground whenever
possible. More details can be found in Section 2.2.3.
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Notice:
CHIP_EN pin must not be left floating.
2.2.3 Power-up and Reset Timing
Figure 4shows the power-up and reset timing of ESP32-H2 series of chips. Details about the parameters are
listed in Table 1.
VIL_nRST
t0t1
2.8 V
Power Supply Pins
CHIP_EN
Figure 4: Visualization of Timing Parameters for Power-up and Reset
Table 1: Description of Timing Parameters for Power-up and Reset
Parameter Description Min (µs)
t0
Time between bringing up the power supply pins and activating
CHIP_EN 50
t1Duration of CHIP_EN signal level < VIL_nRST to reset the chip 50
Notice:
In cases where the power supply ramps up slowly (e.g., during battery charging), or the device needs to be frequently
powered on and off, or the power supply is unstable (e.g., in solar photovoltaic systems), adding a single RC circuit might
not meet the requirements for power-up and reset timing, and consequently the chip will not boot correctly. In this case,
it is advised to take other approaches, such as adding an external reset chip or a watchdog timer IC. The threshold of
reset chip or watchdog timer IC is suggested to be around 3.0 V.
2.3 Flash
ESP32-H2 series of chips have in-package 2 MB or 4 MB flash. The pins for flash are not bonded out.
2.4 Clock Source
ESP32-H2 has two clock sources:
• External clock source
• RTC clock source
2.4.1 External Clock Source (compulsory)
Currently, the ESP32-H2 firmware only supports 32 MHz crystal.
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Crystal
The circuit for the crystal is shown in Figure 5. Note that the accuracy of the selected crystal should be within
±10 ppm.
Please add a series component (resistor or inductor, see R4 in Figure 5) on the XTAL_P clock trace. Initially, it is
suggested to use an inductor of 24 nH to reduce the impact of high-frequency crystal harmonics on RF
performance, and the value should be adjusted after an overall test.
The initial values of external capacitors C1 and C4 can be determined according to the formula:
CL=C1×C4
C1 + C4+Cstray
where the value of CL(load capacitance) can be found in the crystal’s datasheet, and the value of Cstray refers to
the PCB’s stray capacitance. The values of C1 and C4 need to be further adjusted after an overall test as
below:
1. Select TX tone mode using the Certification and Test Tool.
2. Observe the 2.4 GHz signals with a radio communication analyzer or a spectrum analyzer and demodulate
it to obtain the actual frequency offset.
3. Adjust the frequency offset to be within ±10 ppm (recommended) by adjusting the external load
capacitance.
• When the center frequency offset is positive, it means that the equivalent load capacitance is small,
and the external load capacitance needs to be increased.
• When the center frequency offset is negative, it means the equivalent load capacitance is large, and
the external load capacitance needs to be reduced.
• External load capacitance at the two sides are usually equal, but in special cases, they may have
slightly different values.
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
The values of C11, L2 and C12 vary with the actual PCB board.
The values of C1 and C4 vary with the selection of the crystal. The value of R4 varies with the actual PCB board. R4 could be a resistor or inductor, the initial value is suggested to be 24 nH.
CHIP_EN:
H Activate chip; L Disable chip. This pin could not be float.
When VBAT is powered by external battery, R2 can be NC.
RF_ANT LNA_IN GPIO27
GPIO0 GPIO2 GPIO3 GPIO1 GPIO4 GPIO5
VBAT
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
U0RXD U0TXD GPIO25 GPIO26 GPIO22 EN
GPIO14
GND
VDD33
GNDGNDGND
GND
GNDGND
GND
GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
VDD33
GND
VDD33
C2
10nF C5
1uF
C7
1uF
C10 0.1uF C13 0.1uF
C6
10uF
L2 TBD
C1
TBD
R3 499
Y1
32MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C19 0.1uF
ANT1
PCB_ANT
1 2
U1 ESP32-H2
VDD3P3
1
VDD3P3
2
GPIO0
3
GPIO1
4
MTMS
5
MTDO
6
MTCK
7
MTDI
8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30
VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25 24
U0TXD 23
U0RXD 22
GPIO22 21
VDDPST2 20
VDDA_PMU 19
VBAT 18
CHIP_EN 17
C17 0.1uF
C12
TBD
R2 0
C8
0.1uF
C4 TBD
R4 TBD
C11
TBD
Figure 5: Schematic for the Crystal
Notice:
• Defects in the manufacturing of crystal (for example, large frequency deviation of more than ±10 ppm, unstable
performance within operating temperature range, etc) may lead to the malfunction of ESP32-H2, resulting in a
decrease of the RF performance.
• It is recommended that the amplitude of the crystal is greater than 500 mV.
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• When Bluetooth connection fails, after ruling out software problems, you may follow the steps mentioned above to
ensure that the frequency offset meets the requirements by adjusting capacitors at the two sides of the crystal.
2.4.2 RTC Clock(optional)
ESP32-H2 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC
sleep clock. Using an RTC clock is aimed at achieving more accurate timekeeping and reducing average power
consumption, and does not have impact on the functionality.
Figure 6shows the schematic for the external 32.768 kHz crystal.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GPIO13
GPIO14
GND
GND
GND
X1
32.768kHz
12
C14 TBD
U1
ESP32-H2
VDD3P3 1 VDD3P3 2
GPIO0 3 GPIO1 4
MTMS 5 MTDO 6
MTCK 7
MTDI 8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30
VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25
24 U0TXD 23 U0RXD 22 GPIO22 21 VDDPST2 20 VDDA_PMU 19 VBAT 18 CHIP_EN 17
R18 TBD
C13 TBD
Figure 6: Schematic for the RTC Clock
Notice:
• Please note the requirements for the 32.768 kHz crystal.
–Equivalent series resistance (ESR) ⩽70 kΩ.
–Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R is used for biasing the crystal circuit (5 MΩ< R ⩽10 MΩ). In general, you do not need to
populate the resistor.
• If the RTC clock is not required, then the pins for the external 32.768 kHz crystal can be used as other GPIOs.
2.5 RF
The RF circuit of the ESP32-H2 series of chips is mainly composed of three parts, the RF traces on the PCB
board, the chip matching circuit, the antenna and the antenna matching circuit.
• For the RF traces on the PCB board, 50 Ωimpedance control is required.
• For the chip matching circuit, it must be placed close to the chip. It is mainly used to adjust the impedance
point and suppress harmonics. The CLC structure is preferred, and a set of LC can be added if space
permits. The CLC matching circuit is shown in Figure 7.
• For the antenna and the antenna matching circuit, to ensure the radiation performance, the antenna’s
characteristic impedance must be around 50 Ω. Adding a CLC matching circuit near the antenna is
recommended to adjust the antenna. However, if the available space is limited and the antenna impedance
point can be guaranteed to be 50 Ωby simulation, then there is no need to add a matching circuit near the
antenna.
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB board.The initial value could be
0 ohm.
RF_ANT LNA_IN GPIO27
GPIO0
GPIO2
GPIO3
GPIO1
GPIO4
GPIO5
VBAT
GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13
U0RXD
U0TXD
GPIO25
GPIO26
GPIO22
EN
GPIO14
GND
VDD33
GNDGNDGND
GND
GNDGND
GND GND
GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
VDD33
GND
GND
GND
VDD33
C2
10nF C5
1uF
C7
1uF
C10
0.1uF
C13
0.1uF
C6
10uF
L2 TBD
C1
TBD
R3 499
Y1
32MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C19
1uF
ANT1
PCB_ANT
1
2
U1 ESP32-H2
VDD3P3
1
VDD3P3
2
GPIO0
3
GPIO1
4
MTMS
5
MTDO
6
MTCK
7
MTDI
8
GPIO8
10
GPIO9
11
GPIO10
12
GPIO11
13
GPIO12
14
XTAL_32K_P
15
XTAL_32K_N
16 GPIO26 25
GPIO27 26
VDD3P3 27
XTAL_N 28
XTAL_P 29
VDD3P3 30 VDD3P3 31
ANT 32
GND 33
VDDPST1
9
GPIO25 24
U0TXD 23
U0RXD 22
GPIO22 21
VDDPST2 20
VDDA_PMU 19
VBAT 18
CHIP_EN 17
C9
0.1uF
C17
0.1uF
C18
0.1uF
C12
TBD
R2 0
C8
0.1uF
L1 0
C3
0.1uF
C4
TBD
R4 0
C11
TBD
Figure 7: Schematic for RF Matching
Figure 8shows the general process of RF tuning. Please be noted the matching parameters are subject to the
RF tuning of PCB board, which depends greatly on the antenna and PCB layout. For ESP32-H2 series of chips,
it is recommended to set the S11 parameter in the figure below to 35+j5 Ω�and the center frequency is 2442
MHz.
If the RF function is not required, the RF pin can be left floating.
If the application or production environment is susceptible to electrostatic discharge, it is recommended to
reserve an ESD protection diode near the antenna side.
Figure 8: RF Tuning Diagram
Notice:
The matching parameters vary with board, so the ones used in our modules could not be applied directly.
2.6 UART
It is recommended to connect a 499 Ωseries resistor to the U0TXD line in order to suppress the 80 MHz
harmonics.
Usually UART0 is used as the serial port for download and log printing, and UART0 pins (U0TXD and U0RXD) are
fixed. For instructions on download over UART0, please refer to Section 4.3.
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Other UART interfaces can be used as serial ports for communication, which could be mapped to any available
GPIO by software configurations. For these interfaces, it is also recommended to add a series resistor to the TX
line to suppress harmonics.
When using the AT firmware, please note that the UART GPIO is already configured (refer to AT Firmware
Download). It is recommended to use the default configuration.
2.7 Strapping Pins
At each startup or reset, a chip requires some initial configuration parameters, such as in which boot mode to
load the chip, etc. These parameters are passed over via the strapping pins. After reset, the strapping pins work
as normal function pins.
All the information about strapping pins is covered in ESP32-H2 Series Datasheet > Section Strapping Pins.
In this document we will mainly cover the strapping pins related to boot mode.
GPIO8 and GPIO9 control the boot mode after the reset is released. See Table 2 Chip Boot Mode Control.
Table 2: Chip Boot Mode Control
Boot Mode GPIO0 GPIO46
Default Configuration — (Floating) 1 (Pull-up)
SPI Boot (default) Any value 1
Download Boot 1 0
Invalid combination 10 0
1This combination triggers unexpected behavior
and should be avoided.
Regarding the timing requirements for the strapping pins, there are such parameters as setup time and hold time.
For more information, see Table 3and Figure 9.
Table 3: Description of Timing Parameters for the Strapping Pins
Parameter Description Min (ms)
t0Setup time before CHIP_EN goes from low to high 0
t1Hold time after CHIP_EN goes high 3
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CHIP_EN
t1 t0
Strapping pin
VIL_nRST
VIH
Figure 9: Visualization of Timing Parameters for the Strapping Pins
Notice:
Please do not add high-value capacitors at GPIO9, otherwise the chip not boot successfully.
2.8 GPIO
The pins of ESP32-H2 series can be configured via IO MUX or GPIO matrix. IO MUX provides the default pin
configurations, whereas the GPIO matrix is used to route signals from peripherals to GPIO pins. For more
information about IO MUX and GPIO matrix, please refer to ESP32-H2 Technical Reference Manual > Chapter IO
MUX and GPIO Matrix.
Some peripheral signals can only be routed to certain GPIO pins, while some can be routed to any available
GPIO pins. For details, please refer to ESP32-H2 Series Datasheet > Section Peripheral Pin Congurations.
When using GPIOs:
• Pay attention to the states of strapping pins during power-up.
• Pay attention to their default configurations after reset (refer to Table 4). It is recommended to add a pull-up
or pull-down resistor to pins in high-impedance state or enable the pull-up and pull-down during software
initialization to avoid extra power consumption.
Note:
The content below is excerpted from ESP32-H2 Series Datasheet > Section Pins.
Table 4: IO MUX Pin Functions
Name No. Function 0 Function 1 Function 2 Reset Notes
GPIO0 3 GPIO0 GPIO0 FSPIQ 0 —
GPIO1 4 GPIO1 GPIO1 FSPICS0 0 R
MTMS 5 MTMS GPIO2 FSPIWP 1 R
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Name No. Function 0 Function 1 Function 2 Reset Notes
MTDO 6 MTDO GPIO3 FSPIHD 1 R
MTCK 7 MTCK GPIO4 FSPICLK 1* R
MTDI 8 MTDI GPIO5 FSPID 1 R
GPIO8 10 GPIO8 GPIO8 — 1 —
GPIO9 11 GPIO9 GPIO9 — 3 —
GPIO10 12 GPIO10 GPIO10 — 0 R
GPIO11 13 GPIO11 GPIO11 — 0 R
GPIO12 14 GPIO12 GPIO12 — 0 —
XTAL_32K_P 15 GPIO13 GPIO13 — 0 R
XTAL_32K_N 16 GPIO14 GPIO14 — 0 R
GPIO22 21 GPIO22 GPIO22 — 0 —
U0RXD 22 U0RXD GPIO23 FSPICS1 3 —
U0TXD 23 U0TXD GPIO24 FSPICS2 4 —
GPIO25 24 GPIO25 GPIO25 FSPICS3 1 —
GPIO26 25 GPIO26 GPIO26 FSPICS4 1 R, USB
GPIO27 26 GPIO27 GPIO27 FSPICS5 3* R, USB
Reset
The default configuration of each pin after reset:
•0- input disabled, in high impedance state (IE = 0)
•1- input enabled, in high impedance state (IE = 1)
•2- input enabled, pull-down resistor enabled (IE = 1, WPD = 1)
•3- input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
•4- output enabled, pull-up registor enabled (OE = 1, WPU = 1)
•1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is
0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)
1, input enabled, in high impedance state (IE = 1)
•3* - input enabled, pull-up resistor enabled (IE = 1, WPU = 0, USB_WPU = 1). See details in Notes
We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power
consumption. You may add pull-up and pull-down resistors in your PCB design, or enable internal pull-up and
pull-down resistors during software initialization.
Notes
•R- These pins have analog functions.
•USB - The pull-up value of a USB pin is controlled by the pin’s pull-up value together with the USB pull-up
value. If any of the two pull-up values is 1, the pin’s pull-up resistor will be enabled. The pull-up resistors of
USB pins are controlled by the USB_SERIAL_JTAG_DP/DM_PULLUP bit, and the pull-up value is
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controlled by the USB_SERIAL_JTAG_PULLUP_VALUE bit. For details, see
ESP32-H2 Technical Reference Manual > Chapter USB Serial/JTAG Controller.
2.9 ADC
It is recommended to add a 0.1 µF filter capacitor between pins and ground when using the ADC function.
2.10 USB
ESP32-H2 integrates a USB serial/JTAG controller that is compatible with USB 2.0 full-speed mode.
GPIO26 and GPIO27 can be used as D- and D+ for USB, and it is recommended to add a series resistor (initial
value can be 0 Ω) and a capacitor to ground (initially optional), and place them near the ESP32-H2 chip.
ESP32-H2 also supports downloading and log printing through USB. For instructions on download over USB,
please refer to Section 4.3.
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3 PCB Layout Design
This chapter introduces the key points of how to design an ESP32-H2 PCB layout using the ESP32-H2-MINI-1
module as an example.
Figure 10: ESP32-H2 PCB Layout
3.1 General Principles of PCB Layout
It is recommended to use a four-layer PCB design:
• Layer 1 (TOP): Signal traces and components.
• Layer 2 (GND): No signal traces here to ensure a complete GND plane.
• Layer 3 (POWER): GND plane should be applied to better isolate the RF and crystal. Route power traces
and a few signal traces on this layer, provided that there is a complete GND plane under the RF and crystal.
• Layer 4 (BOTTOM): Route a few signal traces here. It is not recommended to place any components on
this layer.
A two-layer PCB design can also be used:
• Layer 1 (TOP): Traces and components.
• Layer 2 (BOTTOM): Do not place any components on this layer and keep traces to a minimum. Please
make sure there is a complete GND plane for the chip, RF, and crystal.
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3.2 Positioning a Module on a Base Board
If module-on-board design is adopted, attention should be paid while positioning the module on the base board.
The interference of the base board on the module’s antenna performance should be minimized.
It is suggested to place the module’s on-board PCB antenna outside the base board, and the feed point of the
antenna closest to the board. In the following example figures, positions with mark ✓are strongly recommended,
while positions without a mark are not recommended.
123
4
5
Base board
Feed Point
✓
✓
Figure 11: Placement of ESP32-H2 Modules on Base Board (antenna feed point on the right)
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123
4
5
Base board
Feed Point
✓
✓
Figure 12: Placement of ESP32-H2 Modules on Base Board (antenna feed point on the left)
If PCB antenna could not be placed outside the board, please ensure a clearance of at least 15 mm around the
antenna area (no copper, routing, or components on it), and place the feed point of the antenna closest to the
board. If there is a base board under the antenna area, it is recommended to cut it off to minimize its impact on
the antenna. Figure 13 shows the suggested clearance for modules whose antenna feed point is on the left.
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Max 1
Base board
Max 2 Min15
5.4
Unit: mm
: Clearance Area
Figure 13: Keepout Zone for ESP32-H2 Module’s Antenna on the Base Board
When designing an end product, attention should be paid to the interference caused by the housing of the
antenna and it is recommended to carry out RF verification.
As a conclusion, please be noted it is necessary to test the throughput and communication signal range of the
whole product to ensure the product’s actual RF performance.
3.3 Power Supply
Figure 14: ESP32-H2 Power Traces in a Four-layer PCB Design
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