Espressif Systems ESP32-C6 Series Instruction Manual

ESP32-C6 Series
Hardware Design Guidelines
Introduction
Hardware design guidelines give advice on how to integrate ESP32-C6 into other products.
ESP32-C6 is a series of ultra-low-power SoCs with support for 2.4 GHz Wi-Fi 6 (802.11 ax),
Bluetooth®5 (LE), Zigbee and Thread (802.15.4).
These guidelines will help to ensure optimal performance of your product with respect to tech-
nical accuracy and conformity to Espressif’s standards.
Version 1.0
Espressif Systems
Copyright © 2023
www.espressif.com

Contents
Contents
1 Overview 5
2 Schematic Checklist 6
2.1 Power Supply 8
2.1.1 Digital Power Supply 8
2.1.2 Analog Power Supply 8
2.2 Power-up Timing and System Reset 9
2.2.1 Power-up Timing 9
2.2.2 System Reset 9
2.2.3 Power-up and Reset Timing 10
2.3 Flash 10
2.4 Clock Source 11
2.4.1 External Clock Source (compulsory) 11
2.4.2 RTC (optional) 12
2.5 RF 13
2.6 UART 14
2.7 Strapping Pins 14
2.8 GPIO 15
2.9 ADC 17
2.10 USB 17
2.11 SDIO 17
3 PCB Layout Design 19
3.1 General Principles of PCB Layout 19
3.2 Positioning a Module on a Base Board 20
3.3 Power Supply 22
3.4 Crystal 23
3.5 RF 24
3.6 Flash 26
3.7 UART 26
3.8 USB 27
3.9 SDIO 27
3.10 Typical Layout Problems and Solutions 27
3.10.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 27
3.10.2 Q: The power ripple is small, but RF TX performance is poor. 28
3.10.3 Q: When ESP32-C6 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 28
3.10.4 Q: TX performance is not bad, but the RX sensitivity is low. 28
4 Hardware Development 29
4.1 ESP32-C6 Modules 29
4.2 ESP32-C6 Development Boards 29
4.3 Download Instructions 29
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Contents
5 Related Documentation and Resources 30
Glossary 31
Revision History 32
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List of Figures
List of Tables
1 Description of Timing Parameters for Power-up and Reset 10
3 Boot Mode Control 15
4 Description of Timing Parameters for the Strapping Pins 15
5 ESP32-C6 Pin Overview 16
List of Figures
1 ESP32-C6 QFN40 Schematic 6
2 ESP32-C6 QFN32 Schematic 7
3 Schematic for the Digital Power Supply Pins 8
4 Schematic for the Analog Power Supply Pins 9
5 Visualization of Timing Parameters for Power-up and Reset 10
6 Schematic for the External Flash and RAM (PSRAM) 11
7 Schematic for the Crystal 12
8 Schematic for the External Crystal (RTC) 12
9 Schematic for ESP32-C6’s External Oscillator 13
10 Schematic for RF Matching 13
11 RF Tuning Diagram 14
12 Visualization of Timing Parameters for the Strapping Pins 15
13 ESP32-C6 PCB Layout 19
14 Placement of ESP32-C6 Modules on Base Board (antenna feed point on the right) 20
15 Placement of ESP32-C6 Modules on Base Board (antenna feed point on the left) 20
16 Keep-out Zone for ESP32-C6 Module’s Antenna on the Base Board (antenna feed point on the right) 21
17 ESP32-C6 Power Traces in a Four-layer PCB Design 22
18 ESP32-C6 Analog Power Traces in a Four-layer PCB Design 23
19 ESP32-C6 Crystal Layout 24
20 ESP32-C6 RF Layout in a Four-layer PCB Design 24
21 ESP32-C6 PCB Stack up Design 25
22 ESP32-C6 Stub in a Four-layer PCB Design 26
23 ESP32-C6 Flash Layout 26
24 ESP32-C6 UART0 Layout 27
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1 Overview
1 Overview
Note:
Check the link or the QR code to make sure that you use the latest version of this document:
https://espressif.com/sites/default/files/documentation/esp32-c6_hardware_design_guidelines_en.
pdf
ESP32-C6 series is a low-power MCU-based SoC solution that supports 2.4 GHz Wi-Fi 6 (802.11 ax),
Bluetooth®5 (LE), Zigbee 3.0 and Thread 1.3 (802.15.4). With its state-of-the-art power and RF performance,
this SoC is an ideal choice for a wide variety of application scenarios relating to Internet of Things (IoT), smart
home, industrial automation, health care, and consumer electronics.
ESP32-C6 has a high-performance (HP) 32-bit RISC-V processor and an low-power (LP) 32-bit RISC-V
processor, operating at up to 160 MHz and 20 MHz respectively. The chip supports application development to
operate without the need for a host MCU.
ESP32-C6 series provides a highly-integrated way to implement wireless communication technologies using a
complete RF subsystem, including a antenna switch, RF balun, power amplifier, low noise amplifier (LNA), filter,
power management unit, calibration circuits, etc. As a result, PCB size has been greatly reduced.
With its advanced calibration circuitry, ESP32-C6 series can dynamically adjust itself to remove external circuit
imperfections or adapt to changes in external conditions. As such, the mass production of ESP32-C6 series
does not require expensive and specialized Wi-Fi test equipment.
For more information about ESP32-C6 series, please refer to ESP32-C6 Series Datasheet.
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2 Schematic Checklist
2 Schematic Checklist
The core circuitry of ESP32-C6 requires only 20 electrical components (resistors, capacitors, and inductors), one
crystal and one SPI flash memory chip (optional for the QFN32 package). The high integration of ESP32-C6
allows for simple peripheral circuit design. This chapter details ESP32-C6 schematics.
ESP32-C6 consists of variants in two packages, namely the QFN40 package and the QFN32 package. The main
difference between these two packages is whether the flash is integrated into the chip’s package.
ESP32-C6 schematics are shown in Figure 1and Figure 2respectively.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
NC: No component.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
LNA_INRF_ANT
GPIO18
GPIO19
GPIO22
GPIO23
GPIO20
GPIO21
CHIP_EN
GPIO3
GPIO2
GPIO0
GPIO1
GPIO4
GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 SPICS0
SPIQ
SPIWP
SPIHD
SPICLK
SPID
GPIO15
U0RXD
U0TXD
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
GNDGND
VDD_SPI
GND GND
GND
VDD_SPI
GND
C11
TBD
R17 0
Y1
40MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C12
TBD
C4
TBD
C2
10nF
C7
1uF
R16 0
R4 TBD
C6
10uF
R15 0
U2 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C8
0.1uF
C9
0.1uF
C17
1uF
R14 0
L1 2.0nH
L2 TBD
R8
10K(NC)
R13 0
ANT1
PCB_ANT
1
2
C1
TBD
U1 ESP32-C6
ANT
1
VDDA3P3
2
GND 41
VDDA3P3
3
CHIP_EN
4
VDDPST1
5
XTAL_32K_P
6
XTAL_32K_N
7
GPIO2
8
GPIO3
9
MTMS
10
SPID 26
SPICLK 25
SPIHD 24
VDD_SPI 23
SPIWP 22
SPIQ 21
MTDI
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
GPIO11
17
GPIO12
18
GPIO13
19
SPICS0
20
GPIO15 27
VDDPST2 28
U0TXD 29
U0RXD 30
VDDA2 40
XTAL_P 39
XTAL_N 38
VDDA1 37
SDIO_DATA3 36 SDIO_DATA2 35 SDIO_DATA1 34 SDIO_DATA0 33
SDIO_CLK 32
SDIO_CMD 31
C10
0.1uF
C3
1uF
C15
0.1uF
R10 0
C16
0.1uF
R3 499
Figure 1: ESP32-C6 QFN40 Schematic
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
NC: No component.
CHIP_EN
GPIO0
GPIO1
GPIO2
GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO12
GPIO13
GPIO14
GPIO15
LNA_IN
U0RXD
U0TXD
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
RF_ANT
GND
GNDGND
VDD33
GND
GND
GND GND
VDD33
VDD33
GND
GND
GND
GND
VDD33
GND GNDGND
GND
GND
L2 TBD
C6
10uF
C8
0.1uF
Y1
40MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C9
0.1uF
R4 TBD
R17 0
R3 499
C2
10nF
C1
TBD
C10
0.1uF
L1 2.0nH
U1 ESP32-C6F
VDDA3P3
2
VDDA3P3
3
GPIO3
9
GPIO12
16
MTMS
10
MTDO
13 MTCK 12 MTDI 11
GPIO13 17
VDDPST1
5
GPIO2
8
GPIO8
14
GPIO9
15
XTAL_32K_P
6
XTAL_32K_N
7
CHIP_PU
4U0RXD 22
U0TXD 21
SDIO_CLK 24
SDIO_DATA0 25 SDIO_DATA1 26 SDIO_DATA2 27
XTAL_N 30
XTAL_P 31
VDDA1 29
ANT
1
GND 33
GPIO15 19
VDDPST2 20
SDIO_CMD 23
SDIO_DATA3 28
VDDA2 32
GPIO14 18
C7
1uF(NC)
ANT1
PCB_ANT
1
2
C4
TBD
C11
TBD
C15
0.1uF
C12
TBD
C3
1uF
Figure 2: ESP32-C6 QFN32 Schematic
Note:
Unless otherwise specified, ”ESP32-C6” used in this document refers to the QFN40 variant of ESP32-C6.
Any basic ESP32-C6 circuit design may be broken down into 11 major sections:
• Power supply
• Power-on sequence and system reset
• Flash
• Clock source
• RF
• UART
• Strapping pins
• GPIO
• ADC
• USB
• SDIO
The rest of this chapter details the specifics of circuit design for each of these sections.
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2 Schematic Checklist
2.1 Power Supply
For more information about power pins, please refer to ESP32-C6 Series Datasheet > Section Power Supply.
2.1.1 Digital Power Supply
ESP32-C6 has pin5 VDDPST1 and pin28 VDDPST2 that supply power to LP digital pins/part of analog pins and
HP digital pins respectively, in a voltage range of 3.0 V ~3.6 V. It is recommended to add a 0.1 µF filter capacitor
close to each digital power supply pin.
Pin23 VDD_SPI can serve as the power supply for the external device at 3.3 V (typical value), provided by
VDDPST2 via RSP I (For information about RSP I , please refer to ESP32-C6 Series Datasheet > Section Power
Scheme). Therefore, there will be a voltage drop on VDD_SPI to VDDPST2. It is recommended to add a 0.1 µF
and a 1 µF filter capacitor close to VDD_SPI.
VDD_SPI can be connected to and powered by an external power supply.
When not serving as a power supply pin, VDD_SPI can be used as GPIO27.
Notice:
When using VDD_SPI as the power supply pin for the in-package flash or external 3.3 V flash, the supply voltage should
be 3.0 V or above, so as to meet the requirements of flash’s working voltage.
The schematic for the digital power supply pins is shown in Figure 3.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB board. The initial value could be
24 nH.
NC: No component.
LNA_INRF_ANT
GPIO18
GPIO19
GPIO22
GPIO23
GPIO20
GPIO21
CHIP_EN
GPIO3
GPIO2
GPIO0
GPIO1
GPIO4
GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 SPICS0
SPIQ
SPIWP
SPIHD
SPICLK
SPID
GPIO15
U0RXD
U0TXD
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
GNDGND
VDD_SPI
GND GND
GND
VDD_SPI
GND
C11
TBD
R17 0
Y1
40MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C12
TBD
C4
TBD
C2
10nF
C7
1uF
R4 TBD
R16 0
C6
10uF
R15 0
U2 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C8
0.1uF
C9
0.1uF
C17
1uF
R14 0
L1 2.0nH
L2 TBD
R8
10K(NC)
R13 0
ANT1
PCB_ANT
1
2
C1
TBD
U1 ESP32-C6
ANT
1
VDDA3P3
2
GND 41
VDDA3P3
3
CHIP_EN
4
VDDPST1
5
XTAL_32K_P
6
XTAL_32K_N
7
GPIO2
8
GPIO3
9
MTMS
10
SPID 26
SPICLK 25
SPIHD 24
VDD_SPI 23
SPIWP 22
SPIQ 21
MTDI
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
GPIO11
17
GPIO12
18
GPIO13
19
SPICS0
20
GPIO15 27
VDDPST2 28
U0TXD 29
U0RXD 30
VDDA2 40
XTAL_P 39
XTAL_N 38
VDDA1 37
SDIO_DATA3 36 SDIO_DATA2 35 SDIO_DATA1 34 SDIO_DATA0 33
SDIO_CLK 32
SDIO_CMD 31
C10
0.1uF
C3
1uF
C15
0.1uF
R10 0
C16
0.1uF
R3 499
Figure 3: Schematic for the Digital Power Supply Pins
2.1.2 Analog Power Supply
Pin2 VDDA3P3, pin3 VDDA3P3, pin37 VDDA1, and pin40 VDDA2 are the analog power supply pins, working at
3.0 V ~3.6 V.
Please be noted that the sudden increase in current draw, when ESP32-C6 is transmitting signals, may cause a
power rail collapse. Therefore, it is highly recommended to add a 10 µF capacitor to the power pin2 and pin3
VDDA3P3, which can work in conjunction with the 1 µF capacitor. In addition, a CLC filter circuit needs to be
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2 Schematic Checklist
added near VDDA3P3 pins so as to suppress high-frequency harmonics. The recommended rated current of the
inductor is 500 mA or above. Refer to Figure 4and place the appropriate decoupling capacitor near each analog
power pin.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
NC: No component.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the
actual PCB board. R4 could be a
resistor or inductor, the initial
value is suggested to be 24 nH.
CHIP_EN:
H Activate chip;
L Disable chip.
This pin could not be float.
LNA_INRF_ANT
GPIO18
GPIO19
GPIO22
GPIO23
GPIO20
GPIO21
CHIP_EN
GPIO3
GPIO2
GPIO0
GPIO1
GPIO4
GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 SPICS0
SPIQ
SPIWP
SPIHD
SPICLK
SPID
GPIO15
U0RXD
U0TXD
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
GND GND GND
VDD33
GND GND GND
GNDGND
GND
GND
VDD33
GND
GND
VDD33
VDD33
GND
GNDGND
VDD_SPI
GND GND
GND
VDD_SPI
GND
C11
TBD
R17 0
Y1
40MHz(±10ppm)
XIN
1
GND
2XOUT 3
GND 4
C12
TBD
C4
TBD
C2
10nF
C7
1uF
R16 0
R4 TBD
C6
10uF
R15 0
U2 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
C8
0.1uF
C9
0.1uF
C17
1uF
R14 0
L1 2.0nH
L2 TBD
R8
10K(NC)
R13 0
ANT1
PCB_ANT
1
2
C1
TBD
U1 ESP32-C6
ANT
1
VDDA3P3
2
GND 41
VDDA3P3
3
CHIP_EN
4
VDDPST1
5
XTAL_32K_P
6
XTAL_32K_N
7
GPIO2
8
GPIO3
9
MTMS
10
SPID 26
SPICLK 25
SPIHD 24
VDD_SPI 23
SPIWP 22
SPIQ 21
MTDI
11
MTCK
12
MTDO
13
GPIO8
14
GPIO9
15
GPIO10
16
GPIO11
17
GPIO12
18
GPIO13
19
SPICS0
20
GPIO15 27
VDDPST2 28
U0TXD 29
U0RXD 30
VDDA2 40
XTAL_P 39
XTAL_N 38
VDDA1 37
SDIO_DATA3 36 SDIO_DATA2 35 SDIO_DATA1 34 SDIO_DATA0 33
SDIO_CLK 32
SDIO_CMD 31
C10
0.1uF
C3
1uF
C15
0.1uF
R10 0
C16
0.1uF
R3 499
Figure 4: Schematic for the Analog Power Supply Pins
Notice:
• The recommended power supply voltage for ESP32-C6 is 3.3 V and the output current is no less than 500 mA.
• It is suggested to add another 10 µF capacitor at the power entrance. If the power entrance is close to pin2 and
pin3, two 10 µF capacitors could be merged into one.
• It is suggested to add an ESD protection diode at the power entrance.
2.2 Power-up Timing and System Reset
2.2.1 Power-up Timing
When ESP32-C6 uses a 3.3 V system power supply, the power rails need some time to stabilize before CHIP_PU
is pulled up and the chip is activated. Therefore, CHIP_PU needs to be powered up after the 3.3 V rails have
been brought up. More details about the power-up timing can be found in Section 2.2.3.
Notice:
To ensure the correct power-up timing, it is advised to add an RC delay circuit at the CHIP_PU pin. The recommended
setting for the RC delay circuit is usually R = 10 kΩand C = 1 µF. However, specific parameters should be adjusted based
on the characteristics of the actual power supply and the power-up and reset sequence timing of the chip.
2.2.2 System Reset
CHIP_PU serves as the reset pin of ESP32-C6. The reset voltage (VIL_nRST ) should be in the range of (–0.3 ~
0.25 × VDDPST1) V. To avoid reboots caused by external interferences, make the CHIP_PU trace as short as
possible. Also, add a pull-up resistor as well as a capacitor to the ground whenever possible. More details can
be found in Section 2.2.3.
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Notice:
CHIP_PU pin must not be left floating.
2.2.3 Power-up and Reset Timing
Figure 5shows the power-up and reset timing of ESP32-C6 series of chips. Details about the parameters are
listed in Table 1.
VIL_nRST
tST BL tRST
2.8 V
VDDA3P3,
VDDPST1,
VDDPST2,
VDDA1,
VDDA2
CHIP_PU
Figure 5: Visualization of Timing Parameters for Power-up and Reset
Table 1: Description of Timing Parameters for Power-up and Reset
Parameter Description Min (µs)
tST BL
Time reserved for the power rails of VDDA3P3, VDDPST1, VD-
DPST2, VDDA1 and VDDA2 to stabilize before the CHIP_PU pin
is pulled high to activate the chip
50
tRST
Time reserved for CHIP_PU to stay below VIL_nRST to reset the
chip 50
Notice:
If your device needs to be frequently powered on and off, the power supply ramps up slowly, or the power supply such as
solar photovoltaic is not stable, adding a single RC circuit might not meet the requirements for power-up and reset timing,
and consequently the chip will not boot correctly. In this case, it is advised to take other approaches, such as adding an
external reset chip or a watchdog timer IC. For chips with a 3.3 V flash, the reset threshold is suggested to be around 3.0
V.
2.3 Flash
ESP32-C6 series in QFN40 package can support up to 16 MB external flash, powered by VDD_SPI. It is
recommended to add a zero-ohm series resistor on the SPI lines as shown in Figure 6, to lower the driving
current, reduce interference to RF, adjust timing, and better shield from interference.
ESP32-C6 series of chips in QFN32 package have in-package SPI flash. The pins for flash are not bonded out.
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