Espressif Systems ESP32 Series Instruction Manual

ESP32
Hardware Design Guidelines
Version 2.7
Espressif Systems
Copyright © 2019
www.espressif.com

About This Document
The guidelines outline recommended design practices when developing standalone or add-on systems based on
the ESP32 series of products, including ESP32 SoCs, ESP32 modules and ESP32 development boards.
Revision History
For the revision history of this document, please refer to the last page.
Documentation Change Notification
Espressif provides email notifications to keep customers updated on changes to technical documentation. Please
subscribe at www.espressif.com/en/subscribe.
Certification
Download certificates for Espressif products from www.espressif.com/en/certificates.
Disclaimer and Copyright Notice
Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT IS
PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABIL-
ITY, NON-INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE
ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information in this docu-
ment is disclaimed. No licenses express or implied, by estoppel or otherwise, to any intellectual property rights
are granted herein. The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property of their respective
owners, and are hereby acknowledged.
Copyright © 2019 Espressif Inc. All rights reserved.

Contents
1 Overview 1
2 Schematic Checklist and PCB Layout Design 2
2.1 Schematic Checklist 2
2.1.1 Power Supply 3
2.1.1.1 Digital Power Supply 3
2.1.1.2 Analog Power Supply 4
2.1.2 Power-on Sequence and System Reset 4
2.1.2.1 Power-on Sequence 4
2.1.2.2 Reset 4
2.1.3 Flash 5
2.1.4 Crystal Oscillator 5
2.1.4.1 External Clock Source (Compulsory) 5
2.1.4.2 RTC (Optional) 6
2.1.5 RF 7
2.1.6 ADC 7
2.1.7 External Capacitor 8
2.1.8 UART 8
2.2 PCB Layout Design 8
2.2.1 Standalone ESP32 Module 9
2.2.1.1 General Principles of PCB Layout 9
2.2.1.2 Positioning a ESP32 Module on a Base Board 10
2.2.1.3 Power Supply 11
2.2.1.4 Crystal Oscillator 12
2.2.1.5 RF 13
2.2.1.6 External RC 14
2.2.1.7 UART 14
2.2.1.8 Touch Sensor 15
2.2.2 ESP32 as a Slave Device 16
2.2.3 Typical Layout Problems and Solutions 17
2.2.3.1 Q: The current ripple is not large, but the TX performance of RF is rather poor. 17
2.2.3.2 Q: The power ripple is small, but RF TX performance is poor. 18
2.2.3.3 Q: When ESP32 sends data packages, the power value is much higher or lower than the
target power value, and the EVM is relatively poor. 18
2.2.3.4 Q: TX performance is not bad, but the RX sensitivity is low. 18
3 Hardware Development 19
4 Applications 20
4.1 ESP32 Smart Audio Platform 20
4.1.1 ESP32-LyraT Audio Development Board 20
4.1.2 ESP32-LyraTD-MSC Audio Development Board 21
4.2 ESP32 Touch Sensor Application—ESP32-Sense Kit 22
4.3 ESP-Mesh Application—ESP32-MeshKit 23

Revision History 24

List of Figures
1 ESP32 Schematics (ESP32-D0WD used as an example for all illustrations in this section) 2
2 ESP32 Digital Power Supply Pins 3
3 ESP32 Analog Power Supply Pins 4
4 ESP32 Flash 5
5 ESP32 Crystal Oscillator 6
6 Schematic for ESP32’s External Crystal (RTC) 6
7 Schematic of External Oscillator 7
8 ESP32 RF Matching Schematics 7
9 ESP32 External Capacitor 8
10 ESP32 UART 8
11 ESP32 PCB Layout 9
12 ESP32 Module Antenna Position on Base Board 10
13 Keepout Zone for ESP32 Module’s Antenna on the Base Board 11
14 ESP32 Power Traces in a Four-layer PCB Design 11
15 ESP32 Power Traces in a Two-layer PCB Design 12
16 ESP32 Crystal Oscillator Layout 13
17 ESP32 RF Layout in a Four-layer PCB Design 14
18 ESP32 RF Layout in a Two-layer PCB Design 14
19 ESP32 UART Design 15
20 A Typical Touch Sensor Application 15
21 Electrode Pattern Requirements 16
22 Sensor Track Routing Requirements 16
23 PAD/TV Box Layout 17
24 Top View of ESP32-LyraT 20
25 Bottom View of ESP32-LyraT 21
26 ESP32-LyraTD-MSC 22
27 ESP32-Sense Kit 22
28 ESP32-MeshKit-Light � 23
29 ESP32-MeshKit-Sense Development Board 23

1. Overview
1. Overview
ESP32 is a single 2.4 GHz Wi-Fi and Bluetooth combo chip designed with TSMC ultra-low-power 40 nm technol-
ogy. It is designed to achieve the best power and RF performance, robustness, versatility, and reliability in a wide
variety of applications and different power profiles.
ESP32 is a highly-integrated solution for Wi-Fi + Bluetooth applications in the IoT industry with around 20 external
components. ESP32 integrates the antenna switch, RF balun, power amplifier, low noise receive amplifier, filters,
and power management modules. As such, the entire solution occupies minimal Printed Circuit Board (PCB)
area.
ESP32 uses CMOS for single-chip fully-integrated radio and baseband, and also integrates advanced calibration
circuitries that allow the solution to dynamically adjust itself to remove external circuit imperfections or adjust to
changes in external conditions. As such, the mass production of ESP32 solutions does not require expensive and
specialized Wi-Fi test equipment.
The ESP32 series of chips include ESP32-D0WDQ6, ESP32-D0WD, ESP32-D2WD and ESP32-S0WD. For details
of part number and ordering information, please refer to ESP32 Datasheet.
Espressif Systems 1 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
2. Schematic Checklist and PCB Layout Design
ESP32’s integrated circuitry requires only 20 resistors, capacitors and inductors, one crystal and one SPI flash
memory chip. ESP32 integrates the complete transmit/receive RF functionality including the antenna switches, RF
balun, power amplifier, low noise receive amplifier, filters, power management module, and advanced calibration
circuitries.
ESP32’s high integration allows for simple peripheral circuit design. This document details ESP32 schematics and
PCB layout design.
While the high level of integration makes the PCB design and layout process simple, the performance of the system
strongly depends on system design aspects. To achieve the best overall system performance, please follow the
guidelines specified in this document for circuit design and PCB layout. All the common rules associated with
good PCB design still apply and this document is not an exhaustive list of good design practices.
2.1 Schematic Checklist
ESP32 schematics is as shown in Figure 1.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The capacitance of C1 and C2 varies
with the selection of the crystal.
SENSOR_VP
SENSOR_VN
GPIO32
GPIO33
CHIP_PU
GPIO35
SCK/CLK
SCS/CMD
SENSOR_VP
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
SENSOR_VN
GPIO34
GPIO26 GPIO27 GPIO14 GPIO12 GPIO2 GPIO15 GPIO0
GPIO18
GPIO2
U0TXD
U0RXD
GPIO22
GPIO21
GPIO4
GPIO19
SHD/SD2
SWP/SD3
SCS/CMD
SCK/CLK
SDO/SD0
SDI/SD1
GPIO23
CHIP_PU
GPIO34
GPIO35
GPIO25
GPIO26
GPIO27
GPIO14
GPIO12
GPIO13
GPIO0
GPIO15
GPIO4
GPIO16
GPIO5
GPIO17
GPIO32
GPIO33
GPIO21
U0TXD
U0RXD
GPIO25
GPIO13
GPIO16
SDI/SD1
SDO/SD0
SCK/CLK
SCS/CMD
SWP/SD3
SHD/SD2
GPIO5
GPIO18
GPIO23
GPIO17
GPIO19
GPIO22
GND
VDD33
GND
VDD33
GND
GND
GND
VDD33
GND
GND
VDD_SDIO GND
VDD_SDIO
GND
GND
GND
GNDGND
GND
VDD33
VDD33
GND
GNDGND
GND
GND
GND
GND GND
VDD33
GND
GND
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
L5 2.0nH
R1 20K(5%)
C13
10uF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
J30
CON1
1
J23
CON1
1
C5
10nF/6.3V(10%)
C14
TBD
J26
CON1
1
J31
CON1
1
C6
3.3nF/6.3V(10%)
D1
ESD3.3V88D-LCDN
C9
0.1uF
J4
CON1
1
R3 499R
C11
1uF J22
CON1
1
J14
CON1
1
J35
CON1
1
C15
TBD
J36
CON1
1
J12
CON1
1
ANT1
PCB ANT
1
2
C16
270pF(NC)
J7
CON1
1
J25
CON1
1
J21
CON1
1
J6
CON1
1
J33
CON1
1
J17
CON1
1
J32
CON1
1
C17
270pF(NC)
J10
CON1
1
J1
CON1
1
J15
CON1
1
J3
CON1
1
J24
CON1
1
J37
CON1
1
J27
CON1
1
J2
CON1
1
U2 ESP32-D0WD
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
GPIO26
15
GPIO27
16
MTMS
17
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
GND 49
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39 GPIO21 42
VDD3P3_CPU 37
CAP1 48
VDDA 46
U0RXD 40
C20
1uF
L4 TBD
C1
TBD
C18
1uF
J20
CON1
1
J16
CON1
1
J5
CON1
1
C12
NC
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C21
NC
J29
CON1
1
J8
CON1
1
J13
CON1
1
C2
TBD
J19
CON1
1
J9
CON1
1
C4
0.1uF
C10
0.1uF
C3
100pF
J34
CON1
1
C19
0.1uF
J11
CON1
1
J38
CON1
1
R2
0R
J28
CON1
1
J18
CON1
1
Figure 1: ESP32 Schematics (ESP32-D0WD used as an example for all illustrations in this section)
Any basic ESP32 circuit design may be broken down into eight major sections:
• Power supply
• Power-on sequence and system reset
• Flash
• Crystal oscillator
Espressif Systems 2 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
• RF
• ADC
• External capacitors
• UART
2.1.1 Power Supply
For further details of using the power supply pins, please refer to Section 2.3 Power Scheme in ESP32 Datasheet.
2.1.1.1 Digital Power Supply
Pin19 and pin37 are the power supply pins for RTC and CPU, respectively. The digital power supply operates in
a voltage range of 1.8 V ~3.6 V. We recommend adding extra filter capacitors of 0.1 µF close to the digital power
supply pins.
VDD_SDIO works as the power supply for the related IO, and also for an external device.
• When VDD_SDIO operates at 1.8 V, it can be generated from ESP32’s internal LDO. The maximum current
this LDO can offer is 40 mA, and the output voltage range is 1.65 V ~2.0 V. When the VDD_SDIO outputs
1.8 V, the value of GPIO12 should be set to 1 when the chip boots and it is recommended that users add a
2 kΩground resistor and a 4.7 µF filter capacitor close to VDD_SDIO.
• When VDD_SDIO operates at 3.3 V, it is driven directly by VDD3P3_RTC through a 6 Ωresistor, therefore,
there will be some voltage drop from VDD3P3_RTC. When the VDD_SDIO outputs 3.3 V, the value of GPIO12
is 0 (default) when the chip boots and it is recommended that users add a 1 µF capacitor close to VDD_SDIO.
VDD_SDIO can also be driven by an external power supply.
When using VDD_SDIO as the power supply pin for the external 3.3 V flash/PSRAM, the supply voltage should be
2.7 V or above, so as to meet the requirements of flash/PSRAM’s working voltage.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The capacitance of C1 and C2 varies
with the selection of the crystal.
SENSOR_VP
SENSOR_VN
GPIO32
GPIO33
CHIP_PU
GPIO35
SCK/CLK
SCS/CMD
SENSOR_VP
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
SENSOR_VN
GPIO34
GPIO26 GPIO27 GPIO14 GPIO12 GPIO2 GPIO15 GPIO0
GPIO18
GPIO2
U0TXD
U0RXD
GPIO22
GPIO21
GPIO4
GPIO19
SHD/SD2
SWP/SD3
SCS/CMD
SCK/CLK
SDO/SD0
SDI/SD1
GPIO23
CHIP_PU
GPIO34
GPIO35
GPIO25
GPIO26
GPIO27
GPIO14
GPIO12
GPIO13
GPIO0
GPIO15
GPIO4
GPIO16
GPIO5
GPIO17
GPIO32
GPIO33
GPIO21
U0TXD
U0RXD
GPIO25
GPIO13
GPIO16
SDI/SD1
SDO/SD0
SCK/CLK
SCS/CMD
SWP/SD3
SHD/SD2
GPIO5
GPIO18
GPIO23
GPIO17
GPIO19
GPIO22
GND
VDD33
GND
VDD33
GND
GND
GND
VDD33
GND
GND
VDD_SDIO GND
VDD_SDIO
GND
GND
GND
GNDGND
GND
VDD33
VDD33
GND
GNDGND
GND
GND
GND
GND GND
VDD33
GND
GND
Title
Size Document Number Rev
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Rev
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Rev
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
L5 2.0nH
R1 20K(5%)
C13
10uF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
J30
CON1
1
J23
CON1
1
C5
10nF/6.3V(10%)
C14
TBD
J26
CON1
1
J31
CON1
1
C6
3.3nF/6.3V(10%)
D1
ESD3.3V88D-LCDN
C9
0.1uF
J4
CON1
1
R3 499R
C11
1uF J22
CON1
1
J14
CON1
1
J35
CON1
1
C15
TBD
J36
CON1
1
J12
CON1
1
ANT1
PCB ANT
1
2
C16
270pF(NC)
J7
CON1
1
J25
CON1
1
J21
CON1
1
J6
CON1
1
J33
CON1
1
J17
CON1
1
J32
CON1
1
C17
270pF(NC)
J10
CON1
1
J1
CON1
1
J15
CON1
1
J3
CON1
1
J24
CON1
1
J37
CON1
1
J27
CON1
1
J2
CON1
1
U2 ESP32-D0WD
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
GPIO26
15
GPIO27
16
MTMS
17
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
GND 49
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39 GPIO21 42
VDD3P3_CPU 37
CAP1 48
VDDA 46
U0RXD 40
C20
1uF
L4 TBD
C1
TBD
C18
1uF
J20
CON1
1
J16
CON1
1
J5
CON1
1
C12
NC
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C21
NC
J29
CON1
1
J8
CON1
1
J13
CON1
1
C2
TBD
J19
CON1
1
J9
CON1
1
C4
0.1uF
C10
0.1uF
C3
100pF
J34
CON1
1
C19
0.1uF
J11
CON1
1
J38
CON1
1
R2
0R
J28
CON1
1
J18
CON1
1
Figure 2: ESP32 Digital Power Supply Pins
Espressif Systems 3 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
2.1.1.2 Analog Power Supply
Pin1, pin3, pin4, pin43 and pin46 are the analog power supply pins. It should be noted that the sudden increase
in current draw, when ESP32 is in transmission mode, may cause a power rail collapse. Therefore, it is highly
recommended to add another 10 µF capacitor to the power trace, which can work in conjunction with the 0.1 µF
capacitor. LC filter circuit needs to be added near the power pin so as to suppress high-frequency harmonics.
The inductor’s rated current is preferably 500 mA and above.
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The capacitance of C1 and C2 varies
with the selection of the crystal.
SENSOR_VP
SENSOR_VN
GPIO32
GPIO33
CHIP_PU
GPIO35
SCK/CLK
SCS/CMD
SENSOR_VP
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
SENSOR_VN
GPIO34
GPIO26 GPIO27 GPIO14 GPIO12 GPIO2 GPIO15 GPIO0
GPIO18
GPIO2
U0TXD
U0RXD
GPIO22
GPIO21
GPIO4
GPIO19
SHD/SD2
SWP/SD3
SCS/CMD
SCK/CLK
SDO/SD0
SDI/SD1
GPIO23
CHIP_PU
GPIO34
GPIO35
GPIO25
GPIO26
GPIO27
GPIO14
GPIO12
GPIO13
GPIO0
GPIO15
GPIO4
GPIO16
GPIO5
GPIO17
GPIO32
GPIO33
GPIO21
U0TXD
U0RXD
GPIO25
GPIO13
GPIO16
SDI/SD1
SDO/SD0
SCK/CLK
SCS/CMD
SWP/SD3
SHD/SD2
GPIO5
GPIO18
GPIO23
GPIO17
GPIO19
GPIO22
GND
VDD33
GND
VDD33
GND
GND
GND
VDD33
GND
GND
VDD_SDIO GND
VDD_SDIO
GND
GND
GND
GNDGND
GND
VDD33
VDD33
GND
GNDGND
GND
GND
GND
GND GND
VDD33
GND
GND
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
L5 2.0nH
R1 20K(5%)
C13
10uF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
J30
CON1
1
J23
CON1
1
C5
10nF/6.3V(10%)
C14
TBD
J26
CON1
1
J31
CON1
1
C6
3.3nF/6.3V(10%)
D1
ESD3.3V88D-LCDN
C9
0.1uF
J4
CON1
1
R3 499R
C11
1uF J22
CON1
1
J14
CON1
1
J35
CON1
1
C15
TBD
J36
CON1
1
J12
CON1
1
ANT1
PCB ANT
1
2
C16
270pF(NC)
J7
CON1
1
J25
CON1
1
J21
CON1
1
J6
CON1
1
J33
CON1
1
J17
CON1
1
J32
CON1
1
C17
270pF(NC)
J10
CON1
1
J1
CON1
1
J15
CON1
1
J3
CON1
1
J24
CON1
1
J37
CON1
1
J27
CON1
1
J2
CON1
1
U2 ESP32-D0WD
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
GPIO26
15
GPIO27
16
MTMS
17
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
GND 49
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39 GPIO21 42
VDD3P3_CPU 37
CAP1 48
VDDA 46
U0RXD 40
C20
1uF
L4 TBD
C1
TBD
C18
1uF
J20
CON1
1
J16
CON1
1
J5
CON1
1
C12
NC
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C21
NC
J29
CON1
1
J8
CON1
1
J13
CON1
1
C2
TBD
J19
CON1
1
J9
CON1
1
C4
0.1uF
C10
0.1uF
C3
100pF
J34
CON1
1
C19
0.1uF
J11
CON1
1
J38
CON1
1
R2
0R
J28
CON1
1
J18
CON1
1
Figure 3: ESP32 Analog Power Supply Pins
Notice:
• The recommended voltage of the power supply for ESP32 is 3.3 V, and its recommended output current is 500 mA
or more.
• It is suggested that users add an ESD tube at the power entrance.
2.1.2 Power-on Sequence and System Reset
2.1.2.1 Power-on Sequence
ESP32 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized. This
is achieved by delaying the activation of CHIP_PU (Pin9) after the 3.3 V rails have been brought up. More details
can be found in section Power Scheme in ESP32 Datasheet.
Notice:
If CHIP_PU is driven by a power management chip, then the power management chip controls the ESP32 power
state. When the power management chip turns on/off Wi-Fi through the high/low level on GPIO, a pulse current
may be generated. To avoid level instability on CHIP_PU, an RC delay circuit is required.
2.1.2.2 Reset
CHIP_PU serves as the reset pin of ESP32. The input level (VIL_nRST ) for resetting the chip should be low enough
and remain so for a period of time. More details can be found in section Power Scheme in ESP32 Datasheet.
Espressif Systems 4 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
To avoid reboots caused by external interferences, the CHIP_PU trace should be as short as possible and routed
away from the clock lines. A pull-up resistor and a ground capacitor are highly recommended.
Notice:
CHIP_PU pin must not be left floating.
2.1.3 Flash
ESP32 can support up to four 16 MB external QSPI flash and SRAM chips. The demo flash used currently is an
SPI flash with 4 MB ROM, in an SOP8 (208 mil) package. The VDD_SDIO acts as the power supply pin. Make
sure to select the appropriate flash according to the power voltage on VDD_SDIO.
SCK/CLK
SCS/CMD
SHD/SD2 SWP/SD3
SDI/SD1
SDO/SD0
GPIO16
SDI/SD1
SDO/SD0
SCK/CLK
SCS/CMD
SWP/SD3
SHD/SD2
GPIO5
GPIO18
GPIO23
GPIO17
GPIO19
GND
VDD_SDIO GND
VDD_SDIO
GND
VDD33
VDD33
C18
1uF
ESP32-D0WD
VDD_SDIO 26
GPIO16 25
GPIO17 27
SD_DATA_2 28
SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
SD_DATA_1 33
GPIO5 34
GPIO18 35
GPIO19 38
GPIO23 36
VDD3P3_CPU 37
C4
0.1uF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
Figure 4: ESP32 Flash
2.1.4 Crystal Oscillator
There are two clock sources for the ESP32, that is, an external crystal oscillator clock source and an RTC clock
source.
2.1.4.1 External Clock Source (Compulsory)
Currently, the ESP32 Wi-Fi/BT firmware only supports 40 MHz crystal oscillator. In circuit design, capacitors C1 and
C2 which connect to the ground are added to the input and output terminals of the crystal oscillator respectively.
The specific capacitive values depend on further testing of, and adjustment to, the overall performance of the
whole circuit. It is recommended that users reserve a series resistor of 0 Ωon the XTAL_P clock trace to reduce
the drive strength of the crystal, as well as to minimize the impact of crystal harmonics on RF performance. Note
that the accuracy of the selected crystal is ±10 ppm.
Espressif Systems 5 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
5 5
4 4
3 3
2 2
1 1
D D C C B B A A
The capacitance of C1 and C2 varies with the selection of the crystal.
SENSOR_VP SENSOR_VN
GPIO32 GPIO33
CHIP_PU GPIO35
SCK/CLK SCS/CMD
SENSOR_VP
SHD/SD2 SWP/SD3
SDI/SD1 SDO/SD0
SENSOR_VN GPIO34
GPIO26
GPIO27
GPIO14
GPIO12
GPIO2
GPIO15
GPIO0
GPIO18
GPIO2
U0TXD U0RXD GPIO22 GPIO21
GPIO4
GPIO19
SHD/SD2 SWP/SD3 SCS/CMD SCK/CLK SDO/SD0 SDI/SD1
GPIO23
CHIP_PU
GPIO34 GPIO35 GPIO25 GPIO26 GPIO27 GPIO14 GPIO12
GPIO13
GPIO0
GPIO15
GPIO4 GPIO16 GPIO5 GPIO17
GPIO32 GPIO33
GPIO21 U0TXD U0RXD
GPIO25
GPIO13
GPIO16 SDI/SD1 SDO/SD0 SCK/CLK SCS/CMD SWP/SD3 SHD/SD2 GPIO5 GPIO18 GPIO23 GPIO17 GPIO19 GPIO22
GND
VDD33
GND
VDD33
GND
GND
GND
VDD33
GND GND
VDD_SDIO GND
VDD_SDIO
GND
GND
GND
GNDGND
GND
VDD33
VDD33
GND
GNDGND
GND
GND
GND
GND GND
VDD33
GND
GND
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
Title
Size Document Number Re v
Date: Sheet o f
<Doc>
ESP-WROOM-32-5X5
A2
1 1Tuesday, July 03, 2018
L5 2.0nH
R1 20K(5%)
C13
10uF
U3 FLASH
/CS
1
DO 2
/WP 3
GND
4
DI 5
CLK
6
/HOLD
7
VCC 8
J30 CON1
1
J23 CON1
1
C5
10nF/6.3V(10%)
C14
TBD
J26 CON1
1
J31 CON1
1
C6
3.3nF/6.3V(10%)
D1 ESD3.3V88D-LCDN
C9 0.1uF
J4 CON1
1
R3 499R
C11
1uF J22
CON1
1
J14 CON1
1
J35 CON1
1
C15
TBD
J36 CON1
1
J12 CON1
1
ANT1
PCB ANT
1 2
C16 270pF(NC)
J7 CON1
1
J25 CON1
1
J21 CON1
1
J6 CON1
1
J33 CON1
1
J17 CON1
1
J32 CON1
1
C17 270pF(NC)
J10 CON1
1
J1 CON1
1
J15 CON1
1
J3 CON1
1
J24 CON1
1
J37 CON1
1
J27 CON1
1
J2 CON1
1
U2 ESP32-D0WD
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
GPIO26
15
GPIO27
16
MTMS
17
MTDI
18
VDD3P3_RTC
19
MTCK
20
MTDO
21
GPIO2
22
GPIO0
23
GPIO4
24
VDD_SDIO 26
GPIO16 25 GPIO17 27
SD_DATA_2 28 SD_DATA_3 29
SD_CMD 30
SD_CLK 31
SD_DATA_0 32
GND 49
SD_DATA_1 33
GPIO5 34
GPIO18 35 GPIO19 38
CAP2 47
VDDA 43
XTAL_N 44
XTAL_P 45
GPIO23 36
U0TXD 41
GPIO22 39
GPIO21 42
VDD3P3_CPU 37
CAP1 48
VDDA 46
U0RXD 40
C20 1uF
L4 TBD
C1
TBD
C18
1uF
J20 CON1
1
J16 CON1
1
J5 CON1
1
C12
NC
U1
40MHz+/-10ppm
XIN
1
GND
2XOUT 3
GND 4
C21 NC
J29 CON1
1
J8 CON1
1
J13 CON1
1
C2 TBD
J19 CON1
1
J9 CON1
1
C4
0.1uF
C10 0.1uF
C3
100pF
J34 CON1
1
C19 0.1uF
J11 CON1
1
J38 CON1
1
R2 0R
J28 CON1
1
J18 CON1
1
Figure 5: ESP32 Crystal Oscillator
Notice:
• If an oscillator is used, its output should be connected to XTAL_P on the chip. Please make sure that the oscillator
output is stable and its accuracy is within ± 10 ppm. It is also recommended that the circuit design for the oscillator
is compatible with the use of crystal, in case that if there is a defect in the circuit design, users can still use the
crystal.
• Defects in the craftsmanship of the crystal oscillators (for example, frequency deviation more than ±10 ppm) and
unstable operating temperature may lead to the malfunction of ESP32, resulting in a decrease of the overall per-
formance.
2.1.4.2 RTC (Optional)
ESP32 supports an external 32.768 kHz crystal or an external 32.768 kHz signal (e.g., an oscillator) to act as the
RTC sleep clock.
Figure 6shows the schematic for the external 32.768 kHz crystal.
GPIO35
GPIO33
GPIO25
GPIO32
GND
GND
R4
TBD
C23 TBD
U4
32.768KHz
XTAL32_IN 1
XTAL32_OUT
2
C22 TBD
U2
VDET_1
VDET_2
11
32K_XP
12
32K_XN
13
GPIO25
14
Figure 6: Schematic for ESP32’s External Crystal (RTC)
Espressif Systems 6 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
Notice:
• Please note the requirements for the 32.768 KHz crystal.
–Equivalent series resistance (ESR) ⩽70 KΩ.
–Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R4 is used for biasing the crystal circuit (5 MΩ< R4 ⩽10 MΩ).
• If the RTC source is not required, then pin12 (32K_XP) and pin13 (32K_XN) can be used as GPIOs.
Figure 7shows the schematic of the external signal.
32768 kHz signal
ESP32
32K_XN
32K_XP
C1
Figure 7: Schematic of External Oscillator
The value of C1 should be larger than 200 pF. The signal should meet the following requirements:
32K_XN input Amplitude (Vpp, unit: V)
Sine wave or square wave 0.6 < Vpp < VDD
2.1.5 RF
The output impedance of the RF pins of ESP32 (QFN 6*6) and ESP32 (QFN 5*5) are (30+j10) Ωand (35+j10) Ω,
respectively. A π-type matching network is essential for antenna matching in the circuit design. CLC structure is
recommended for the matching network.
CHIP_PU
GPIO35
SENSOR_VP
SENSOR_VN
GPIO34
GPIO32
GND GNDGND
C14
TBD
L4 TBD
C17
270pF(NC)
C15
TBD
C16
270pF(NC)
VDDA
1
LNA_IN
2
VDD3P3
3
VDD3P3
4
SENSOR_VP
5
SENSOR_CAPP
6
SENSOR_CAPN
7
SENSOR_VN
8
CHIP_PU
9
VDET_1
10
VDET_2
11
12
ANT1
PCB ANT
1
2
Figure 8: ESP32 RF Matching Schematics
Note:
The parameters of the components in the matching network are subject to the actual antenna and PCB layout.
2.1.6 ADC
It is recommended that users add a 0.1 µF filter capacitor to a pad when using the ADC function.
• Pins SENSOR_VP or SENSOR_VN will trigger an input glitch lasting for 80 ns once SARADC1, or SARADC2,
or Hall sensor is initialized.
Espressif Systems 7 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
• Pins SENSOR_VP or SENSOR_VN is recommended for use as ADC.
• If SENSOR_VP and SENSOR_VN are used as GPIOs, while ADC is supported by other pins in the circuit
design, users need to do settings in software to avoid the input glitch.
2.1.7 External Capacitor
Figure 9shows the schematic of components connected to pin47 CAP2 and pin48 CAP1. C5 (10 nF) that connects
to CAP1 should be of 10% tolerance and is required for proper operation of ESP32. RC circuit between CAP1
and CAP2 pins may be omitted under certain conditions. This circuit is used when entering Deep-sleep mode.
During this process, to minimize power consumption, the voltage to power ESP32 internals is dropped from 1.1
V to around 0.7 V. The RC circuit is used to minimize the period of the voltage drop. If removed, this process will
take longer and the power consumption in Deep-sleep will be higher. If particular application of ESP32 is not using
Deep-sleep mode, or power consumption is less critical, then this circuit is not required.
GND
GND
C5
10nF/6.3V(10%)
GND 49
CAP2 47 CAP1 48
VDDA 46
C6
3.3nF/6.3V(10%)
R1 20K(5%)
Figure 9: ESP32 External Capacitor
2.1.8 UART
Users need to connect a 499 Ωresistor to the U0TXD line in order to suppress the 80 MHz harmonics.
U0TXD
U0RXD
GPIO22
R3 499R
U0TXD 41
GPIO22 39 GPIO21
U0RXD 40
Figure 10: ESP32 UART
2.2 PCB Layout Design
This chapter introduces the key points of designing ESP32 PCB layout with the example of ESP32-WROOM-
32D.
Espressif Systems 8 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
The PCB layout design guidelines are applicable to cases when the
• ESP32 module functions as a standalone device, and when the
• ESP32 functions as a slave device.
Figure 11: ESP32 PCB Layout
2.2.1 Standalone ESP32 Module
2.2.1.1 General Principles of PCB Layout
We recommend a four-layer PCB design.
• The first layer is the TOP layer for signal traces and components.
• The second layer is the GND layer without signal traces being routed so as to ensure a complete GND plane.
• The third layer is the POWER layer. It is acceptable to route signal traces on this layer, provided that there is
a complete GND plane under the RF and crystal oscillator.
• The fourth layer is the BOTTOM layer, where power traces are routed. Placing any components on this layer
is not recommended.
Below are the suggestions for a two-layer PCB design.
• The first layer is the TOP layer for traces and components.
• The second layer is the BOTTOM layer. Please do not place any components on this layer and keep traces
to a minimum. Ideally, it should be a complete GND plane.
Espressif Systems 9 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
2.2.1.2 Positioning a ESP32 Module on a Base Board
If users adopt on-board design, they should pay attention to the layout of the module on the base board. The inter-
ference of the base board on the module’s antenna performance should be reduced as much as possible.
It is recommended that the PCB antenna area of the module be placed outside the base board while the module
be put as close as possible to the edge of the base board so that the feed point of the antenna is closest to the
board.
Base Board
1 2 3
45
Figure 12: ESP32 Module Antenna Position on Base Board
Note:
As is shown in Figure 12, the recommended position of ESP32 module on the base board should be:
• Position 3: Highly recommended;
• Position 4: Recommended;
• Position 1, 2, 5: Not recommended.
If the positions recommended are not suitable, please make sure that the module is not covered by any metal
shell. The antenna area of the module and the area 15 mm outside the antenna should be kept clean, (namely no
copper, routing, components on it) as shown in Figure 13:
Espressif Systems 10 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
15 mm
Base Board
15 mm
Clearance
15 mm
Figure 13: Keepout Zone for ESP32 Module’s Antenna on the Base Board
2.2.1.3 Power Supply
•Four-layer PCB design
In a four-layer PCB design, the 3.3 V power traces are routed as shown highlighted in yellow in Figure 14.
The width of these power traces should be greater than 25 mil. Before power traces reach the analog power-
supply pins (pin 1, 3, 4, 43, 46), a 10 µF capacitor is required, which can work in conjunction with the 0.1 µF
capacitor. As Figure 14 shows, C13 (10 µF capacitor) is placed by the 3.3 V stamp hole; C10, L5 and C21
are placed as close as possible to the analog power-supply pin. If possible, add a 0.1 µF capacitor for every
digital power pin. Note that all decoupling capacitors should be placed close to the power pin, and ground
vias should be added adjacent to the ground pin for the decoupling capacitors to ensure a short return path.
Figure 14: ESP32 Power Traces in a Four-layer PCB Design
It is good practice to route the power traces on the fourth (bottom) layer. Vias are required for the power
traces to go through the layers and get connected to the pins on the top layer. The diameter of the drill
should exceed the width of the power traces. The diameter of the via pad should be 1.5 times that of the
drill.
Espressif Systems 11 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
The central thermal pad at the bottom of the chip should be connected to the ground plane through at least
nine ground vias.
•Two-layer PCB design
In a two-layer PCB design, the 3.3 V power traces are routed as shown labelled with VDD33 in Figure 15.
In contrast to the design practices for a four-layer PCB design, the power traces in a two-layer PCB design
should be routed on the top layer, thus requiring a reduced size of a thermal pad in the center of the chip.
Route the power traces between the thermal pad and its surrounding signal pins. Employ vias only when the
power traces have to reach the bottom layer. The purpose of this practice is to maintain a complete ground
plane while reducing the surrounding area of the power traces.
Other good practices for routing power traces in four-layer PCB designs still apply to two-layer PCB designs.
Figure 15: ESP32 Power Traces in a Two-layer PCB Design
2.2.1.4 Crystal Oscillator
For design of the crystal oscillator section, please refer to Figure 16. In addition, the following should be noted:
• The crystal oscillator should be placed far from the clock pin. The recommended gap is 2.7 mm. It is good
practice to add high-density ground via stitching around the clock trace for containing the high-frequency
clock signal.
• There should be no vias for the clock input and output traces, which means the traces cannot cross layers.
• The external regulating capacitor should be placed on the near left or right side of the crystal oscillator and
at the end of the clock trace.
• Do not route high-frequency digital signal traces under the crystal oscillator. It is best not to route any signal
trace under the crystal oscillator. The larger the copper area on the top layer is, the better.
• As the crystal oscillator is a sensitive component, do not place any magnetic components nearby that may
cause interference, for example, power-switching converter components or unshielded inductors.
Espressif Systems 12 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
Figure 16: ESP32 Crystal Oscillator Layout
2.2.1.5 RF
•Four-layer PCB design
In a four-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 17. The characteristic
RF impedance must be 50 Ω. The ground plane on the adjacent layer needs to be complete. Make sure to
keep the width of the RF trace consistent, and do not branch the trace. The RF trace should be as short as
possible with dense ground via stitching around it for isolation.
However, there should be no vias for the RF trace. The RF trace should be routed at a 135° angle, or with
circular arcs if trace bends are required.
π-type matching circuitry should be reserved on the RF trace and placed close to the chip.
No high-frequency signal traces should be routed close to the RF trace. The RF antenna should be placed
away from high-frequency transmitting devices, such as crystal oscillators, DDR, and clocks (SDIO_CLK),
etc.
In addition, the USB port, USB to UART chip, UART signal lines (including traces, vias, test points, header
pins, etc.) must be as far away from the antenna as possible. It is good practice to add ground vias around
the UART signal line. It is recommended that the design of PCB onboard antenna be based on Espressif’s
Type-B antenna.
•Two-layer PCB design
In a two-layer PCB design, the RF trace is routed as shown highlighted in pink in Figure 18. The width of the
RF trace should be greater than that of the RF trace in a four-layer board and is normally over 20 mil. The
actual width depends on the impedance formula where impedance-relevant parameters may vary depending
on the number of PCB layers.
Other good practices for routing RF traces in four-layer PCB designs still apply to two-layer board designs.
Espressif Systems 13 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
Figure 17: ESP32 RF Layout in a Four-layer PCB Design
Figure 18: ESP32 RF Layout in a Two-layer PCB Design
2.2.1.6 External RC
External resistors and capacitors should be placed close to the chip pins, and there should be no vias around the
traces. Please ensure that 10 nF capacitors are placed close to the pins.
2.2.1.7 UART
The series resistor on the U0TXD line needs to be placed as close to the chip as possible. The U0TXD and U0RXD
traces on the top layer should be as short as possible. Employ vias around the traces for isolation.
Figure 19 below shows an example of UART design.
Espressif Systems 14 ESP32 Hardware Design Guidelines V2.7

2. Schematic Checklist and PCB Layout Design
Figure 19: ESP32 UART Design
2.2.1.8 Touch Sensor
ESP32 offers up to 10 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or
proximity. The chip’s internal capacitance detection circuit features low noise and high sensitivity. It allows users to
use touch pads with smaller area to implement the touch detection function. Users can also use the touch panel
array to detect a larger area or more test points. Figure 20 depicts a typical touch sensor application.
Figure 20: A Typical Touch Sensor Application
In order to prevent capacitive coupling and other electrical interference to the sensitivity of the touch sensor system,
the following factors should be taken into account.
Electrode Pattern
The proper size and shape of an electrode improves system sensitivity. Round, oval, or shapes similar to a hu-
man fingertip is commonly applied. Large size or irregular shape might lead to incorrect responses from nearby
electrodes.
Note:
The examples illustrated in Figure 21 are not of actual scale. It is suggested that users use a human fingertip as reference.
Espressif Systems 15 ESP32 Hardware Design Guidelines V2.7