Freescale Semiconductor MPC5634M User manual

MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 1
Preliminary—Subject to Change Without Notice
MPC563XM Microcontroller
Reference Manual
Devices Supported:
MPC5634M
MPC5633M
MPC5632M
MPC563XRM
Rev. 1
25 Jul 2008

MPC563XM Reference Manual, Rev. 1
2Freescale Semiconductor
Preliminary—Subject to Change Without Notice

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Freescale Semiconductor 3
Preliminary—Subject to Change Without Notice
Chapter 1
Introduction
1.1 The MPC563XM Microcontroller Family ......................................................................................23
1.2 MPC563XM Device Summary .......................................................................................................23
1.3 MPC563XM Blocks ........................................................................................................................24
1.3.1 Block Diagram ..................................................................................................................24
1.3.2 Block Summary ................................................................................................................25
1.4 MPC563XM Features .....................................................................................................................26
1.4.1 Feature List .......................................................................................................................26
1.4.2 e200z335 Core ..................................................................................................................35
1.4.3 Crossbar ............................................................................................................................37
1.4.4 eDMA ...............................................................................................................................37
1.4.5 Interrupt Controller ...........................................................................................................38
1.4.6 FMPLL ..............................................................................................................................39
1.4.7 Calibration EBI .................................................................................................................40
1.4.8 SIU ....................................................................................................................................41
1.4.9 ECSM ................................................................................................................................41
1.4.10 Flash ..................................................................................................................................42
1.4.11 SRAM ...............................................................................................................................43
1.4.12 BAM .................................................................................................................................43
1.4.13 eMIOS ...............................................................................................................................43
1.4.14 eTPU .................................................................................................................................44
1.4.15 eQADC .............................................................................................................................46
1.4.16 DSPI ..................................................................................................................................48
1.4.17 eSCI ..................................................................................................................................50
1.4.18 FlexCAN ...........................................................................................................................51
1.4.19 System Timers ...................................................................................................................52
1.4.20 Software Watchdog Timer (SWT) ....................................................................................53
1.4.21 Nexus Port Controller .......................................................................................................53
1.4.22 JTAG .................................................................................................................................55
Chapter 2
Memory Map
2.1 Introduction .....................................................................................................................................57
2.2 Memory Map ...................................................................................................................................57
Chapter 3
Signal Descriptions
3.1 Device Pin Assignments ..................................................................................................................63
3.1.1 144 LQFP ..........................................................................................................................63
3.1.2 Ballmap: 208 MAPBGA ...................................................................................................65
3.2 External Signal Summary ................................................................................................................66
3.3 Detailed Signal Descriptions ...........................................................................................................76
3.3.1 Reset / Configuration ........................................................................................................76
3.3.2 Calibration External Bus Interface (EBI) .........................................................................76

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3.3.3 Nexus Port Controller (NPC) ............................................................................................78
3.3.4 JTAG .................................................................................................................................79
3.3.5 FlexCAN ...........................................................................................................................80
3.3.6 eSCI ..................................................................................................................................80
3.3.7 DSPI ..................................................................................................................................81
3.3.8 eQADC .............................................................................................................................82
3.3.9 eTPU .................................................................................................................................85
3.3.10 eMIOS ...............................................................................................................................88
3.3.11 Clock Synthesizer .............................................................................................................89
3.3.12 Power / Ground .................................................................................................................90
Chapter 4
Resets
4.1 Reset Sources ..................................................................................................................................93
4.2 Reset Vector .....................................................................................................................................94
4.3 Reset Pins ........................................................................................................................................94
4.3.1 RESET ..............................................................................................................................94
4.3.2 RSTOUT ...........................................................................................................................94
4.4 Clock Quality Monitor Gating Signal .............................................................................................95
4.5 Reset Source Descriptions ...............................................................................................................95
4.5.1 Power-on Reset .................................................................................................................98
4.5.2 External Reset ...................................................................................................................98
4.5.3 Loss of Lock .....................................................................................................................98
4.5.4 Loss of Clock ....................................................................................................................99
4.5.5 Watchdog Timer/Debug Reset ..........................................................................................99
4.5.6 Software Watchdog Timer Reset ......................................................................................99
4.5.7 Checkstop Reset ..............................................................................................................100
4.5.8 JTAG Reset .....................................................................................................................100
4.5.9 Software System Reset ...................................................................................................100
4.5.10 Software External Reset ..................................................................................................101
4.6 Reset Registers in the SIU .............................................................................................................101
4.7 Reset Configuration .......................................................................................................................101
4.7.1 Reset Configuration Half Word (RCHW) .......................................................................101
4.7.2 Reset Configuration Timing ............................................................................................103
4.7.3 Reset Weak Pull Up/Down Configuration ......................................................................104
Chapter 5
Operating Modes
5.1 Overview .......................................................................................................................................105
5.2 Modes of Operation .......................................................................................................................105
5.2.1 Normal Mode ..................................................................................................................105
5.2.2 Debug Mode ...................................................................................................................105
5.2.3 Low Power Modes ..........................................................................................................105
5.3 Modes and Clock Architecture ......................................................................................................106
5.3.1 Block Diagrams ..............................................................................................................106

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5.3.2 Clock Architecture ..........................................................................................................110
Chapter 6
e200z335 (Z335) Core
6.1 Introduction ...................................................................................................................................115
6.2 Features .........................................................................................................................................115
6.3 Location of Detailed Documentation ............................................................................................116
Chapter 7
Direct Memory Access (DMA)
7.1 Information Specific to This Device .............................................................................................117
7.1.1 Device-Specific Features ................................................................................................117
7.1.2 Channel Assignments .....................................................................................................117
7.2 Introduction ...................................................................................................................................118
7.2.1 Overview .........................................................................................................................119
7.2.2 Features ...........................................................................................................................120
7.3 Memory Map/Register Definition .................................................................................................125
7.3.1 Register Descriptions ......................................................................................................127
7.4 Functional Description ..................................................................................................................151
7.4.1 DMA Microarchitecture .................................................................................................151
7.4.2 DMA Basic Data Flow ...................................................................................................152
7.4.3 DMA Performance ..........................................................................................................155
7.5 Initialization/Application Information ..........................................................................................158
7.5.1 DMA Initialization ..........................................................................................................158
7.5.2 DMA Programming Errors .............................................................................................159
7.5.3 DMA Arbitration Mode Considerations .........................................................................160
7.5.4 DMA Transfer .................................................................................................................161
7.5.5 TCD Status ......................................................................................................................164
7.5.6 Channel Linking .............................................................................................................165
7.5.7 Dynamic Programming ...................................................................................................166
7.5.8 Hardware Request Release Timing .................................................................................167
Chapter 8
Multi-Layer AHB Crossbar Switch (XBAR)
8.1 Information Specific to This Device .............................................................................................169
8.1.1 Device-Specific Block Diagram .....................................................................................169
8.1.2 Device-Specific Features ................................................................................................169
8.1.3 Device-Specific Register Information ............................................................................170
8.2 Introduction ...................................................................................................................................171
8.2.1 Overview .........................................................................................................................171
8.2.2 Features ...........................................................................................................................173
8.2.3 Limitations ......................................................................................................................173
8.2.4 General Operation ...........................................................................................................173
8.3 XBAR Registers ............................................................................................................................174
8.3.1 Register Summary ...........................................................................................................174

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8.3.2 XBAR Register Descriptions ..........................................................................................177
8.3.3 Coherency .......................................................................................................................185
8.4 Function .........................................................................................................................................185
8.4.1 Arbitration .......................................................................................................................185
8.4.2 Priority Assignment ........................................................................................................187
8.4.3 Master Port Functionality ...............................................................................................188
8.4.4 Slave Port Functionality ..................................................................................................191
8.5 Initialization/Application Information ..........................................................................................198
8.6 Interface .........................................................................................................................................198
8.6.1 Overview .........................................................................................................................199
8.6.2 Master Ports ....................................................................................................................199
8.6.3 Slave Ports ......................................................................................................................200
Chapter 9
Peripheral Bridge (PBRIDGE)
9.1 PBRIDGE Features .......................................................................................................................201
9.2 PBRIDGE Modes of Operation .....................................................................................................201
9.3 PBRIDGE Block Diagram ............................................................................................................201
9.4 PBRIDGE Signal Description .......................................................................................................201
9.5 PBRIDGE Functional Description ................................................................................................202
9.5.1 Read Cycles ....................................................................................................................202
9.5.2 Write Cycles ....................................................................................................................202
9.6 PBRIDGE Registers ......................................................................................................................202
Chapter 10
Flash Memory (C90FL)
10.1 Introduction ...................................................................................................................................203
10.2 Platform Flash (PFlash) Memory Controller ................................................................................203
10.2.1 Controller Overview .......................................................................................................203
10.2.2 Features ...........................................................................................................................203
10.2.3 Modes of Operation ........................................................................................................204
10.2.4 Block Diagram ................................................................................................................204
10.2.5 Signal Description ...........................................................................................................204
10.2.6 Functional Description ....................................................................................................204
10.2.7 Memory Map and Register Definition ............................................................................208
10.2.8 C90FL Register Descriptions ..........................................................................................209
10.3 Flash Memory Block (C90FL) ......................................................................................................214
10.3.1 C90FL Block Overview ..................................................................................................214
10.3.2 C90FL Block Features ....................................................................................................215
10.3.3 C90FL Modes of Operation ............................................................................................216
10.3.4 C90FL Block Diagram ....................................................................................................216
10.3.5 C90FL Flash EEPROM Functional Description ............................................................217
10.3.6 C90FL Memory Map and Register Definition ...............................................................219

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Chapter 11
Flash Memory (LC)
11.1 Introduction ...................................................................................................................................243
11.2 Block Diagram ..............................................................................................................................243
11.3 Overview .......................................................................................................................................243
11.4 Features .........................................................................................................................................244
11.4.1 FBIU features ..................................................................................................................244
11.4.2 Flash memory array features ...........................................................................................244
11.5 Modes of Operation .......................................................................................................................245
11.5.1 User Mode .......................................................................................................................245
11.5.2 Stop Mode .......................................................................................................................245
11.6 Memory Map/Register Description ...............................................................................................245
11.6.1 Flash Memory Map .........................................................................................................245
11.6.2 Register Descriptions ......................................................................................................248
11.7 Functional Description ..................................................................................................................279
11.7.1 Basic Interface Protocol ..................................................................................................279
11.7.2 Access Protections ..........................................................................................................280
11.7.3 Read Cycles - Buffer Miss ..............................................................................................280
11.7.4 Read Cycles - Buffer Hit .................................................................................................280
11.7.5 Write Cycles ....................................................................................................................280
11.7.6 Error Termination ............................................................................................................280
11.7.7 Access Pipelining ............................................................................................................281
11.7.8 Flash Error Response Operation .....................................................................................281
11.7.9 Bank0 Page Read Buffers and Prefetch Operation .........................................................281
11.7.10Read-While-Write Functionality .....................................................................................283
11.7.11Wait-State Emulation ......................................................................................................284
11.7.12Flash Memory Array: User Mode ...................................................................................285
Chapter 12
General-Purpose Static RAM (SRAM)
12.1 Overview .......................................................................................................................................299
12.2 Features .........................................................................................................................................299
12.3 Modes of Operation .......................................................................................................................299
12.3.1 Normal (Functional) Mode .............................................................................................299
12.3.2 Standby Mode .................................................................................................................299
12.4 Block Diagram ..............................................................................................................................299
12.5 External Signal Description ..........................................................................................................300
12.6 Functional Description ..................................................................................................................300
12.6.1 Access Timing .................................................................................................................300
12.7 Module Memory Map ...................................................................................................................301
12.8 Register Descriptions ....................................................................................................................301
Chapter 13
External Bus Interface (EBI)
13.1 Information Specific to This Device .............................................................................................303

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13.1.1 Device-Specific Features ................................................................................................303
13.1.2 Unsupported Features .....................................................................................................303
13.1.3 Device-Specific Register Information ............................................................................303
13.2 Introduction ...................................................................................................................................303
13.2.1 Overview .........................................................................................................................304
13.2.2 Features ...........................................................................................................................305
13.2.3 Modes of Operation ........................................................................................................305
13.3 External Signal Description ..........................................................................................................308
13.3.1 Overview .........................................................................................................................308
13.3.2 Detailed Signal Descriptions ..........................................................................................308
13.3.3 Signal Function/Direction by Mode ...............................................................................313
13.3.4 Signal Pad Configuration by Mode ................................................................................313
13.3.5 Signal Output Buffer Enable Logic by Mode .................................................................314
13.4 Memory Map/Register Definition .................................................................................................315
13.4.1 Register Descriptions ......................................................................................................316
13.5 Functional Description ..................................................................................................................324
13.5.1 External Bus Interface Features ......................................................................................324
13.5.2 External Bus Operations .................................................................................................330
13.6 Initialization/Application Information ..........................................................................................397
13.6.1 Booting from External Memory .....................................................................................397
13.6.2 Running with SDR (Single Data Rate) Burst Memories ................................................397
13.6.3 Running with Asynchronous Memories .........................................................................398
13.6.4 Connecting an MCU to Multiple Memories ...................................................................400
13.6.5 Address Decoding Example for External Master Accesses ............................................401
13.6.6 EBI Operation with Reduced Pinout MCUs ...................................................................402
13.6.7 Address/Data Multiplexing Connection Examples .........................................................404
13.6.8 Summary of Differences from MPC5xx .........................................................................408
Chapter 14
Interrupt Controller (INTC)
14.1 Information Specific to This Device .............................................................................................411
14.1.1 Device-Specific Features ................................................................................................411
14.1.2 Device-Specific Register Information ............................................................................411
14.2 Introduction ...................................................................................................................................411
14.2.1 Module Overview ...........................................................................................................411
14.2.2 Block Diagram ................................................................................................................412
14.2.3 Features ...........................................................................................................................413
14.3 Modes of Operation .......................................................................................................................414
14.3.1 Normal Mode ..................................................................................................................414
14.3.2 Debug Mode ...................................................................................................................415
14.3.3 Stop Mode .......................................................................................................................415
14.3.4 Factory Test Mode ..........................................................................................................415
14.4 External Signal Description ..........................................................................................................416
14.5 Memory Map/Register Definition .................................................................................................416
14.5.1 Memory Map ..................................................................................................................416

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14.5.2 Register Information .......................................................................................................416
14.5.3 INTC Block Configuration Register (INTC_BCR) ........................................................417
14.5.4 INTC Current Priority Register for Processor 0 (INTC_CPR_PRC0) ...........................418
14.5.5 INTC Current Priority Register for Processor 1 (INTC_CPR_PRC1) ...........................419
14.5.6 INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR_PRC0) ..........420
14.5.7 INTC Interrupt Acknowledge Register for processor 1 (INTC_IACKR_PRC1) ...........421
14.5.8 INTC End of Interrupt Register for Processor 0 (INTC_EOIR_PRC0) .........................421
14.5.9 INTC End of Interrupt Register for processor 1 (INTC_EOIR_PRC1) .........................422
14.5.10INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3 - INTC_SSCIR4_7) .422
14.5.11INTC Priority Select Registers (INTC_PSR0_3 - INTC_PSR508_511) ........................424
14.6 Functional Description ..................................................................................................................425
14.6.1 Interrupt Request Sources ...............................................................................................425
14.6.2 Priority Management ......................................................................................................426
14.6.3 Handshaking with Processor ...........................................................................................428
14.6.4 Reserved Spaces in Memory Map ..................................................................................431
14.7 Initialization/Application Information ..........................................................................................432
14.7.1 Initialization Flow ...........................................................................................................432
14.7.2 Interrupt Exception Handler ...........................................................................................432
14.7.3 Code Compression’s Impact on Vector Table .................................................................434
14.7.4 ISR, RTOS, and Task Hierarchy .....................................................................................434
14.7.5 Order of Execution ..........................................................................................................434
14.7.6 Priority Ceiling Protocol .................................................................................................435
14.7.7 Selecting Priorities According to Request Rates and Deadlines ....................................436
14.7.8 Software Setable Interrupt Requests ...............................................................................437
14.7.9 Lowering Priority Within an ISR ....................................................................................438
14.7.10Negating an Interrupt Request Outside of its ISR ..........................................................438
14.7.11Examining LIFO contents ...............................................................................................439
Chapter 15
Interrupts
15.1 Introduction ...................................................................................................................................441
15.2 Interrupt Vectors ............................................................................................................................441
15.2.1 External Input .................................................................................................................441
15.2.2 Critical Input ...................................................................................................................443
15.3 Interrupt Summary ........................................................................................................................443
Chapter 16
System Integration Unit (SIU)
16.1 Overview .......................................................................................................................................465
16.2 Features .........................................................................................................................................465
16.3 Modes of Operation .......................................................................................................................466
16.3.1 Normal Mode ..................................................................................................................466
16.3.2 Debug Mode ...................................................................................................................466
16.4 Block Diagram ..............................................................................................................................466
16.5 Signal Description .........................................................................................................................467

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16.6 Detailed Signal Descriptions .........................................................................................................468
16.6.1 RESET — Reset Input ....................................................................................................468
16.6.2 RSTOUT — Reset Output ..............................................................................................468
16.6.3 GPIO[0:213] — General Purpose I/O Pins .....................................................................468
16.6.4 BOOTCFG1 (BOOTCFG1_IRQ[3]_ETRIG[1]_GPIO[212]) — Boot Configuration Pin ..
469
16.6.5 WKPCFG (WKPCFG_NMI_GPIO[213]) — I/O Pin Weak Pull Up Reset Configuration
Pin 469
16.6.6 IRQ[0:15] — External Interrupt Request Input Pins ......................................................469
16.7 Functional Description ..................................................................................................................469
16.7.1 System Configuration .....................................................................................................469
16.7.2 Reset Control ..................................................................................................................470
16.7.3 External Interrupt ............................................................................................................470
16.7.4 GPIO Operation ..............................................................................................................471
16.7.5 Internal Multiplexing ......................................................................................................471
16.8 Memory Map .................................................................................................................................473
16.9 Register Descriptions ....................................................................................................................475
16.9.1 MCU ID Register 2 (SIU_MIDR2) ................................................................................475
16.9.2 MCU ID Register (SIU_MIDR) .....................................................................................477
16.9.3 Reset Status Register (SIU_RSR) ...................................................................................478
16.9.4 System Reset Control Register (SIU_SRCR) .................................................................480
16.9.5 External Interrupt Status Register (SIU_EISR) ..............................................................481
16.9.6 DMA/Interrupt Request Enable Register (SIU_DIRER) ................................................482
16.9.7 DMA/Interrupt Request Select Register (SIU_DIRSR) .................................................483
16.9.8 Overrun Status Register (SIU_OSR) ..............................................................................484
16.9.9 Overrun Request Enable Register (SIU_ORER) ............................................................484
16.9.10IRQ Rising-Edge Event Enable Register (SIU_IREER) ................................................485
16.9.11External IRQ Falling-Edge Event Enable Register (SIU_IFEER) .................................485
16.9.12External IRQ Digital Filter Register (SIU_IDFR) ..........................................................486
16.9.13Pad Configuration Registers (SIU_PCR) .......................................................................487
16.9.14GPIO Pin Data Output Registers (SIU_GPDO83_86 - SIU_GPDO230_232) ...............533
16.9.15GPO Data Output Registers (SIU_GPDO350 - SIU_GPDO413) ..................................534
16.9.16GPIO Pin Data Input Registers (SIU_GPDI83_86 - SIU_GPDI_232) ..........................535
16.9.17eQADC Trigger Input Select Register (SIU_ETISR) .....................................................536
16.9.18External IRQ Input Select Register (SIU_EIISR) ..........................................................538
16.9.19DSPI Input Select Register (SIU_DISR) ........................................................................542
16.9.20MUX Select Register 3 (SIU_ISEL3) ............................................................................545
16.9.21Chip Configuration Register (SIU_CCR) .......................................................................546
16.9.22External Clock Control Register (SIU_ECCR) ..............................................................547
16.9.23Compare A High Register ...............................................................................................548
16.9.24Compare A Low Register ...............................................................................................548
16.9.25Compare B High Register ...............................................................................................549
16.9.26Compare B Low Register ...............................................................................................549
16.9.27System Clock Register (SIU_SYSDIV) .........................................................................550
16.9.28Halt Register (SIU_HLT) ................................................................................................551