Freescale Semiconductor MPC5604B User manual

LAAS-CNRS
Quick Start to MPC5604B
Embedded Development
Sahin Serdar
21/06/2013

Table of Contents
Introduction .........................................................................................................................................................................1
1. About this document..........................................................................................................................................1
2. About of embedded programming ...............................................................................................................2
3. Associated documents.......................................................................................................................................3
Chapter 1 .......................................................................................................4
1. ME: Mode Entry Modules .................................................................................................................................4
1.1. Introduction .................................................................................................................................................4
1.2. Enabling modes ..........................................................................................................................................5
1.3. Configuring modes ....................................................................................................................................5
1.4. Configuring peripherals ..........................................................................................................................6
1.5. Device mode selection .............................................................................................................................7
2. CGM: Clock Generation Module .....................................................................................................................8
2.1. Clock Architecture .....................................................................................................................................8
2.2. Clock Out........................................................................................................................................................9
2.3. Sysclk ...........................................................................................................................................................10
2.4. FMPLL..........................................................................................................................................................11
3. A device initialisation procedure...............................................................................................................13
4. SWT: Software Watchdog Timer................................................................................................................14
Chapter 2 SIUL: System Integration Unit Line ............................................................................................15
1. Introduction........................................................................................................................................................15
2. Pad configuration .............................................................................................................................................15
3. GPIO: General Purpose Input/Output......................................................................................................17
4. External interrupts ..........................................................................................................................................19
Chapter 3 INTC: Interrupt Controller .............................................................................................................21
1. Introduction........................................................................................................................................................21
2. INTC configuration (Software mode) ......................................................................................................23
2.1. Enabling interrupt requests ...............................................................................................................23
2.2. Configuring hardware ISRs.................................................................................................................23
2.3. Configuring software ISRs...................................................................................................................24
2.4. Enabling nested interruptions...........................................................................................................24
3. Hardware mode INTC.....................................................................................................................................24
Chapter 4 Timer Modules ....................................................................................................................................26
1. Introduction........................................................................................................................................................26
2. STM: System Timer Module .........................................................................................................................27

3. PIT: Periodic Interrupt Timer .....................................................................................................................27
4. RTC/API: Real Time Clock/ Autonomous Periodic Interrupt ........................................................29
5. Timer Examples ................................................................................................................................................31
Chapter 5 eMIOS: Enhanced Modular I/O Subsystem .............................................................................32
1. Module Configuration.....................................................................................................................................33
2. Channel Configuration....................................................................................................................................34
1.1. Introduction ..............................................................................................................................................34
1.2. GPIO: General Purpose Input/Output ............................................................................................36
1.3. SAIC: Single Action Input Capture....................................................................................................37
1.4. SAOC: Single Action Output Compare.............................................................................................37
1.5. IPWM: Input Pulse Width Measurement.......................................................................................38
1.6. IPM: Input Period Measurement ......................................................................................................38
1.7. DAOC: Double Action Output Compare..........................................................................................39
1.8. MC: Modulus Counter............................................................................................................................40
1.9. MCB: Modulus Counter Buffered......................................................................................................41
1.10. OPWFMB: Output Pulse Width and Frequency Modulation Buffered .........................41
1.11. OPWMCB: Center Aligned Output Pulse Width Buffered ..................................................43
1.12. OPWMB: Output Pulse Width Modulation Buffered............................................................44
1.13. OPWMT: Output Pulse Width Modulation with Trigger....................................................45
3. PWM Channel Initialisation..........................................................................................................................46
4. PWM Example....................................................................................................................................................46
Chapter 6 ADC: Analog-to-Digital Converter ...............................................................................................48
1. Presentation of the ADC module ................................................................................................................48
1.1. Introduction ..............................................................................................................................................48
1.2. Conversion.................................................................................................................................................49
1.3. ADC clock and conversion timing.....................................................................................................50
1.4. Pre-sampling.............................................................................................................................................51
1.5. Analog watchdog.....................................................................................................................................51
1.6. Low power consumption modes ......................................................................................................51
2. ADC Configuration............................................................................................................................................52
2.1. Pad Configuration ...................................................................................................................................52
2.2. General Registers ....................................................................................................................................52
2.3. Conversion Registers.............................................................................................................................53
2.4. Interrupt Registers.................................................................................................................................54
2.5. Watchdog Registers ...............................................................................................................................54

2.6. Channel Registers ...................................................................................................................................55
3. ADC Example with PIT and eMIOS ............................................................................................................55
Chapter 7 CTU: Cross Triggering Unit ............................................................................................................58
1. Introduction........................................................................................................................................................58
2. Configuring CTU................................................................................................................................................59
3. Configuring ADC................................................................................................................................................60
4. Implementing a feedback loop with ADC-CTU-eMIOS......................................................................60
Chapter 8 WKPU: Wakeup Unit.........................................................................................................................62
1. Low power consumption modes................................................................................................................62
1.1. STOP .............................................................................................................................................................62
1.2. STANDBY....................................................................................................................................................62
2. Introduction........................................................................................................................................................63
3. Configuration of wakeup events.................................................................................................................65
Chapter 9 DSPI: Deserial Serial Peripheral Interface...............................................................................66
1. Introduction........................................................................................................................................................66
1.1. SPI Protocol Description......................................................................................................................66
1.2. Module Presentation .............................................................................................................................68
2. Configuration......................................................................................................................................................69
2.1. Signal Configuration ..............................................................................................................................69
2.2. Module Configuration Register .........................................................................................................69
2.3. Transfer Configuration Register.......................................................................................................70
2.3.1. Data attributes.....................................................................................................................................71
2.3.2. Baud rate ...............................................................................................................................................72
2.3.3. CS to SCK delay....................................................................................................................................73
2.3.4. After SCK delay....................................................................................................................................73
2.3.5. After transfer delay ...........................................................................................................................73
2.4. Status and Interrupt Registers ..........................................................................................................73
2.5. Transmit/Receive Registers...............................................................................................................74
3. Developing a general purpose SPI Driver...............................................................................................75
4. Driving smart-MOS switches MC33984 using SPI Driver................................................................77
4.1. Introduction to MC33984....................................................................................................................77
4.2. Driver’s components .............................................................................................................................77
4.2.1. Definitions.............................................................................................................................................79
4.2.2. Initialization .........................................................................................................................................79
4.2.3. Operations.............................................................................................................................................80

4.2.4. User interface.......................................................................................................................................80
4.2.5. Testing ....................................................................................................................................................80
Chapter 10 UART: Universal Asynchronous Receiver Transmitter......................................................82
1. Introduction to UART......................................................................................................................................82
2. Module Presentation.......................................................................................................................................82
3. Configuration......................................................................................................................................................83
3.1. Signal Configuration ..............................................................................................................................83
3.2. LINFlex Module Configuration ..........................................................................................................83
3.3. UART Mode Configuration ..................................................................................................................84
3.4. Baud Rate Configuration......................................................................................................................84
3.5. Status Registers and Interrupt Configuration.............................................................................85
3.6. Data Transmit/Receive ........................................................................................................................86
4. Developing a general purpose UART Driver .........................................................................................87
5. Using the UART Driver for a terminal interface...................................................................................88
5.1. System initialisation ..............................................................................................................................88
5.2. SIUL configuration..................................................................................................................................88
5.3. ADC configuration...................................................................................................................................89
5.4. eMIOS configuration..............................................................................................................................90
5.5. Main procedure and use of the driver............................................................................................90
5.6. Results .........................................................................................................................................................92
Chapter 11 I²C: Inter-Integrated Circuit Bus Controller............................................................................94
1. Presentation of I²C protocol.........................................................................................................................94
1.1. Description ................................................................................................................................................94
1.2. Baud rate ....................................................................................................................................................95
1.3. Pull-up resistor calculation.................................................................................................................96
2. Using the I²C module.......................................................................................................................................96
2.1. Module Presentation .............................................................................................................................96
2.2. Module Registers.....................................................................................................................................97
2.3. Communication........................................................................................................................................99
2.4. Developing a general purpose I²C Driver .................................................................................. 101
Chapter 12 CAN: Controller Area Network..................................................................................................102
6. CAN protocol ...................................................................................................................................................102
1.1. Introduction ........................................................................................................................................... 102
1.2. Frame Description............................................................................................................................... 103
1.3. Physical Layer .......................................................................................................................................104

1.4. Error detection......................................................................................................................................105
1.5. Bit-rate and sampling......................................................................................................................... 106
7. FlexCAN Module Configuration ...............................................................................................................107
7.1. Module Description.............................................................................................................................107
7.2. Message Buffer mode and RX FIFO mode.................................................................................. 108
7.2.1. Message Buffers............................................................................................................................... 108
7.2.2. RX FIFO Engine ................................................................................................................................110
7.3. Configuration Registers.....................................................................................................................111
7.4. Status and Interrupt Registers ....................................................................................................... 113
8. FlexCAN usage explained with an example ........................................................................................ 115
8.1. Initialisation...........................................................................................................................................116
8.2. Transmission ......................................................................................................................................... 116
8.3. Reception.................................................................................................................................................117
8.4. Interrupt Handling .............................................................................................................................. 117
9. CAN Transceiver(MCZ33905S5EK) Configuration ......................................................................... 118
Appendix 1 Using Code Warrior IDE ...............................................................................................................120
Appendix 2 Pad Configurations .........................................................................................................................127
Appendix 3 Peripheral input pin selection ................................................................................................... 135
Appendix 4 Interrupt Vector Table.................................................................................................................. 137
Appendix 5 I²C Baud Rate Prescaler Values................................................................................................. 142

1
Introduction
1.
About this document
This document is meant to be a simple guide for developing embedded software on Freescale’s
MPC5604B microcontroller, based on Qorrivva architecture. This microcontroller is destined to
be used in automotive applications, mostly related to body control and it comes with many
peripherals.
This guide will be focused on the configuration and use of those peripherals by summarizing the
official reference manual, but it also gives commented code examples and tips for overcoming
common difficulties. Our tests were carried out on the starter kit evaluation board of MPC5604B,
which embodies a CAN transceiver, a potentiometer, four LEDs and buttons; practical for
examples.
The following figure shows different peripherals contained in the microcontroller. The green
ones are explained in detail in this document, minimal information is given on blue ones.

2.
About embedded programming
Most embedded software is built on a multi-layer architecture, where lower layers provide
drivers for a simpler way of using different hardware peripherals. Then those drivers can be
used for implementing drivers for more complex devices or for high-level application related
functions.
The figure below illustrates a software architecture example where an MC33984 high side
switch chip is used for driving some loads, supervising their power and detecting errors while
providing a serial communication interface to the user.
This document is focused on lower software layer interacting with the MCU’s peripherals
directly. In embedded C software there are some restrictions compared to regular C software:
The program must never reach the end of main function. It usually ends up having a
main loop with a state machine or an empty infinite loop.
All the local variables have to be defined at the beginning of a function.
Main function has often the same structure: first it initialises the system clock and mode and
then it initialises and configures each peripheral it uses. On this MCU it also has to disable the
watchdog before doing anything else.
Most of the programming is done by writing and reading peripheral registers so use of masks is
pretty common for accessing specific fields (AND ‘&’ mask for clearing, OR ‘|’ for setting, XOR ‘^’
for toggling).
Due to limited amount of code and data memory, compiler optimisations are quite handy, but
the result might turn into an undefined behaviour if variables that are altered by external
environment are optimised. To avoid this, the keyword ‘volatile’ can be used with these kind of
variables.
DSPI
LINFlex
SIUL
INTC
eMIOS
SPI
DRIVER
UART
DRIVER
PWM
INTERFACE
PAD
CONFIG
INTERRUPT
HANDLER
LOAD
DRIVE
MC33984 SMART MOS CONTROLLER
FAULT
HANDLER
USER
INTERFACE
POWER
SUPERVISION
MAIN APPLICATION
APPLICATION
LAYER
APP. SERVICE
LAYER
APP. DRIVER
&
MCU DRIVER
LAYER
MCU HW LAYER
(Registers etc.)
x |= mask; /* Bits specified by the mask are set, others unchanged. */
x &= (~mask); /* Bits specified by the mask are cleared, others unchanged. */
x ^= mask; /* Bits specified by the mask are toggled, others unchanged. */

3.
Associated documents
This document is not as detailed as the MPC5604B’s reference manual and it may not give all the
required information for implementing some specific behaviour with a peripheral. In this case
following documents might be useful:
MPC5604B/C Reference Manual Rev. 8: The official Freescale document which explains
the use of each peripheral.
AN2865: MPC5500&MPC5600 Simple Cookbook: A Freescale application note which
gives example codes with many peripherals in different uses. It also gives the design
procedure of the software.
TRK-MPC5604B Schematic Rev. B: This document is the schematic of MPC5604B starter
kit board. This should be used to check whether a pin is used by some component on the
board. For instance when using the UART pins on the port B, you should check if the
jumpers connecting those pins to the LIN Transceiver are removed. Otherwise you
would receive framing errors.
MPC5604B/C Datasheet Rev. 7: Contains useful information about electrical and timing
characteristics of the device. It also contains important information related to the
peripherals like SPI timing.
MPC5604B/C Errata: Contains a list of known problems with the MCU and possible
workarounds.
This document itself also contains some detailed examples, codes or driver examples:
-A device initialisation procedure
-Timer examples
-PWM Example
-ADC Example with PIT and eMIOS
-Implementing a feedback loop with ADC-CTU-eMIOS
-Developing a general purpose SPI Driver
-Driving smart-MOS switches MC33984 using SPI Driver
-Developing a general purpose UART Driver
-Using the UART Driver for a terminal interface
-FlexCAN usage explained with an example

4
Chapter 1
Initialisation of the controller
1.
ME: Mode Entry Modules
1.1.
Introduction
This module controls the device modes, their settings and the transitions between them. On
Figure 1, you can find different modes that are availcontroller. They have to be
initialised properly, after reset, in order to get the right configuration for the system.
Figure 1 : MC_ME Mode Diagram (Freescale Lecture)
In this paragraph we will quickly explain RESET, DRUN, SAFE, TEST, RUN 0...3 modes, which are
needed for embedded applications. See Wakeup Events chapter for more information about
STANDBY and STOP modes.
System Modes
oRESET: This state is active after a system reset or a non-recoverable failure.
The device leaves this state once the reset sequence that initialises the chip
and power is completed. The system clock is set to the internal 16MHz RC
oscillator.
oDRUN: This is the entry mode of the software which can control the flash
memories, configure clocks, user modes before going into a user mode. This
is the first thing to be done in “main” procedure (Default RUN).
oSAFE: The device goes into this state once a recoverable hardware failure has
occurred. After handling the failure the system goes in to the DRUN mode,
reinitialising the software.
oTEST: This mode allows software to do on-chip test routines with peripheral
modules, RAM etc.
User Modes
oRUN0…3: This is where the software runs; these four RUN modes can be
configured with different clock and power settings.

1.2.
Enabling modes
The first thing to be done once the device enters in DRUN is to enable the modes that are going
to be used by the software. This is done using the Mode Enable Register (MER). This register
allows all modes to be enabled/disabled except for RESET, DRUN, SAFE, and RUN0 which are
always enabled.
Figure 2 : Mode Enable Register (MER) (Reference Manual Rev8 – Fig. 8-4)
For instance, enabling all the normal user modes can be done with:
1.3.
Configuring modes
We then need to configure the modes we will need in the software using configuration registers
(‘ME.<mode>.R’). In regular embedded software with no power saving specifications, we will
only need configuring RUN0…3.
Figure 3 : Mode Configuration Register for RUN 0…3 (Reference Manual Rev8 – Fig. 8-13)
Quick explanation of modifiable fields of this register:
•DFLAON : Data flash power-down control, leave it at 11 (normal mode)
•CDFLAON : Code flash power-down control, leave it at 11 (normal mode)
•FMPLLON: Frequency Modulated PLL control, 0 if not needed, 1 if used
•FXOSCON: Fast External Crystal Oscillator control, 0 if not needed, 1 if used
•FIRCON: Fast Internal RC Oscillator control, always needed in case of failure
•SYSCLK: System clock switch control, specify the clock used by system (see next chapter
for details on oscillators and their configuration)
ME.MER.R = 0x000000FD; /* Enable all RUNx modes along with default modes */

6
Example for configuring RUN0:

1.4.
Configuring peripherals
Having configured different modes, we possess 8 different registers that allow us to configure a
peripheral to only run on a set of specific mode. These registers are called Run Peripheral
Configuration Registers (RUNPC[0] to RUNPC[7]).
Figure 4 : Run Peripheral Configuration Registers (Reference Manual Rev8 – Fig. 8-21)
You may notice that STANDBY, HALT and STOP cannot be selected using this register, you’ll
need to use Low Power Peripheral Configuration registers (LPPC[0] to LPPC[7]).
Figure 5 : Low Power Peripheral Configuration Registers (Reference Manual Rev8 – Fig. 8-22)
Once all the possible modes have been selected using these 8+8 registers, each one of the 144
peripherals can be affected to one of the 8 RUNPC register and one of the 8 LPPC registers using
Peripheral Control Registers (PCTL[0] to PCTL[143]). The selected peripheral will only run in
the modes selected by these registers.
Figure 6 : Peripheral Control Registers (Reference Manual Rev8 – Fig. 8-23)
DBG_F allows to froze the peripheral in debug mode or not (which can be useful for observing
peripherals internal state), LP_CFG is used to select a low power mode from LPPC registers
ME.RUN[0].R = 0x001F0074; /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL0 */

(0...7) for low power operation and RUN_CFG allows to select a normal run mode from RUNPC
registers. Note that by default, all peripherals run on RUNPC[0] register.
Example for configuring SIUL peripheral (System Integration Unit Line: GPIO and external
interrupt manager) to run only in RUN0 mode, using RUNPC1:
Here’s a table of peripherals with id numbers up to 143:
Figure 7 : Register gating address offset for peripherals (Reference Manual Rev8 – Fig. 6-1)
1.5.
Device mode selection
After enabling modes we want to use, configuring them and the peripherals, we can change the
current mode of the device using the Mode Control Register.
Figure 8 : Mode Control Register (Reference Manual Rev8 – Fig. 8-3)
In order to perform a mode selection, you need to specify the mode in the field TARGET_MODE
and use the Key 0xA50F first, and then repeat the same thing with the inverted key 0x5AF0. This
will trigger a mode transition.
ME.RUNPC[1].R = 0x00000010; /* Peri.Cfg. 1 settings: only run in RUN0 mode */
ME.PCTL[68].R = 0x01; /* MPC56xxB/S: select ME.RUNPC[1] */

To ensure that the operation was successful, you need to use the read only Global Status Register
to check the current mode.
Figure 9 : Global Status Register (Reference Manual Rev8 – Fig. 8-2)
Here’s an example code for a transition towards RUN0 mode:
2.
CGM: Clock Generation Module
2.1.
Clock Architecture
In this section we will discuss different ways to setup the system clock and peripheral clocks in
this microcontroller. The clocking structure is represented on the figure below.
Figure 10 : The Clock Architecture (MC_CGM) (Freescale Lecture)
There are three sets of peripherals in this architecture that can have independent clocks as
noted in the figure above, all peripherals not mentioned there are in the core platform.
ME.MCTL.R = 0x40005AF0; /* Enter RUN0 Mode & Key */
ME.MCTL.R = 0x4000A50F; /* Enter RUN0 Mode & Inverted Key */
while (ME.GS.B.S_MTRANS == 1) {} /* Wait for mode transition to complete */
while (ME.GS.B.S_CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */
div 1 to 16
div 1 to 16
div 1 to 16

We can see that there are five possible clock sources in this architecture:
FXOSC: Fast External Crystal Oscillator, between 4-16MHz (8 MHz on TRK-
MPC5604B),
FIRC: Fast Internal RC Oscillator, 16MHz,
SXOSC: Slow External Crystal Oscillator, 32kHz,
SIRC: Slow Internal RC Oscillator, 128kHz,
FMPLL: Frequency Modulated Phase Locked Loop allows delivering a high speed clock
up to 64MHz using FXOSC.
Slow clocks are mostly used for the real time clock module and we will focus more on the fast
ones that are used for system clock generation.
System clock can be selected among FXOSC, FIRC or their division by 1 to 32, or by FMPLL. This
clock drives the core of the microcontroller, it can be gated to different peripheral sets, and can
be divided for power saving. We can also generate an output clock from pin PA [0] called CLOCK
OUT using these fast oscillators.
2.2.
Clock Out
In this section we will review the registers used to generate an output clock. It can be controlled
using two registers.
Figure 11 : Output Clock Enable Register (Reference Manual Rev8 – Fig. 7-2)
Figure 12 : Output Clock Division Select Register (Reference Manual Rev8 – Fig. 7-2)
Use of the enable register is obvious; write 1 to enable the output clock. For the other one,
SELDIV is the amount of division (clock divided by 2) and SELCTL is the selection of the
source clock among FXOSC (0000), FIRC (0001) and FMPLL (0010).
Here’s an example of using the Output Clock with FMPLL after dividing it by 8:
CGM.OCDS_SC.R = 0x32000000; /* Select FMPLL and divide by 2*/
CGM.OC_EN.B.EN = 1; /* Write 1 to enable bit */
/* Here insert GPIO code that selects CLOCKOUT functionality for the pin
PA[0]: SIU.PCR[0].R = 0x0800;, see chapter on SIUL and pad configurations.*/

2.3.
Sysclk
Each of the four clock source has a single control register for its gating towards next blocks. We
will focus only on FXOSC’s control register.
Figure 13 : Fast External Crystal Oscillator Control Register (Reference Manual Rev8 – Fig. 6-2)
Bypass allows using original crystal signal as clock without going through the oscillator, end of
Count Value is used to check the stability of the clock once the software powers it up. Once a
counter reaches the value EOCV [7:0]×512, if M_OSC is set and interrupt is generated, which has
to be cleared by setting I_OSC to 1, and the clock is ready to be used. The clock is divided by
DIVCLOK+1.
Other clock sources control register are similar with some different features: RC oscillators can
be trimmed by the software to increase precision (FIRC can be up to ± 1% precise) and the
SXOSC has a stability checking field (see chapter 6.3 to 6.6 in reference manual Rev8).
And finally, there are two registers for system clock management, one for reading the selected
source (by ME) and the other one is for managing peripheral clock gating.
Figure 14 : System Clock Select Status Register (Reference Manual Rev8 – Fig. 7-4)
Figure 15 : System Clock Divider Configuration Registers (Reference Manual Rev8 – Fig. 7-5)
DE fields of this register are to enable a divider and the value of division is DIV+1(up to 16).

Here’s an example of using a 1MHz by dividing FXOSC by 8, and supplying a 1MHz clock for
peripheral set 1, 100 kHz for peripheral set 2, 250 kHz for peripheral set 3.
You can notice that divider configuration register is made of three 8 bit register instead of one
32bit. See MPC5604B_M27V.h to see how registers are laid out for different modules.
2.4.
FMPLL
Use of FMPLL allows generating high speed clock by using FXOSC. Its block diagram is on the
figure below.
Figure 16 : FMPLL Block Diagram (Reference Manual Rev8 – Fig. 6-6)
When the PLL is locked we have
 = PHI  , so PHI = FXOSC  . .This module has the
following constraints:
FXOSC [4MHz,16MHz]
VCO [256MHz,512MHz]
NDIV [32,96]
IDF [1,15]
ODF {2,4,8,16}
PHI 64MHz
After carefully choosing values for NDIV, IDF and ODF (using a spread sheet for instance), you
can use the control register of FMPLL module to implement it.
Figure 17 : FMPLL Control Register (Reference Manual Rev8 – Fig. 6-7)
CGM.FXOSC_CTL.R = 0x00800700; /* keep reset settings but divide by 8 */
...
/* Here insert code that configures a user mode’s system clock with divided
xtal fast oscillator, you can check it with CGM.SC_SS.R read only register */
CGM.SC_DC[0].R = 0x00; /* no division for peripheral set 1 */
CGM.SC_DC[1].R = 0x89; /* divide by 10 for peripheral set 2 */
CGM.SC_DC[2].R = 0x83; /* divide by 4 for peripheral set 3 */
/* Here insert code that makes the mode transition towards the user mode with
this clock setup */


.
.


Fields of this register are defined as; IDF[3:0]=IDF-1; and IDF [3:0] =1111 means clock
inhibition, ODF[1:0]=log2(ODF)-1, NDIV[6:0]=NDIV. These values must only be changed while
the PLL is not the system clock source. The other fields on this register are defined as:
EN_PLL_SW: Progressive clock switching, improves the PLL’s transition but the clock will
only reach PHI after a few cycles (192/PHI secondsng 64MHz).
UNLOCK_ONCE is set once the FMPLL loses lock. It will only be cleared on system reset.
I_LOCK is set each time a lock or unlock event occurs. It’s cleared by writing ‘1’.
S_LOCK: lock(‘1’)/unlock(‘0’) status of FMPLL.
PLL_FAIL_MASK: used to mask the pll_fail output (write ‘1’ to mask).
PLL_FAIL_FLAG: is set to ‘1’ once a loss of lock occurs while PLL is on. Cleared by writing
‘1’.
Here’s an example of using an 8 MHz crystal oscillator to generate a 45MHz system clock. Having
NDIV=90, IDF=2, ODF=8 allows us to get this output frequency while VCO frequency remains at
8x45=360MHz. All values are within constraints.
At this point, we only looked at the PLL aspect of the FMPLL module; this module can also
modulate the clock using frequency modulation with a triangular wave. This will help reduce the
effects of electromagnetic interference
generated by the high frequency
harmonics caused around the VCO
(from hundreds of MHz to up to a few
GHz) in the PLL. The electromagnetic
radiations on a specific frequency can
interfere with a surrounding
communication bands and cause errors.
By modulating the clock, its spectrum
will get wider and the energy at a
specific frequency will be less
important. Meanwhile the modulation
depth’s size can be critical in some
applications (like CAN) where FM can
cause errors. FM can be configured
using modulation register.
Frequency modulation can be configured with specifications on (modulation depth)
and  , modulation frequency. Modulation frequency should not be higher than 100kHz and
depth should not be higher than ±4%.
Figure 18 : FMPLL with its different spread modes (Reference
Manual Rev8 – Fig. 6-10)
CGM.FMPLL_CR.B.IDF = 1; //IDF[3:0]=IDF-1=2-1=1
CGM.FMPLL_CR.B.ODF = 2; //ODF[1:0]=log2(8)-1=3-1=2
CGM.FMPLL_CR.B.NDIV = 0x5A; //0x5A=90
CGM.FMPLL_CR.B.EN_PLL_SW = 1; //progressive transition
//these 4 lines are equivalent to CGM.FMPLL_CR.R = 0x065A0100
/* Here insert code that configures a user mode’s system clock with FMPLL,
you can check it with CGM.SC_SS.R read only register */

Figure 19 : FMPLL Modulation Register (Reference Manual Rev8 – Fig. 6-8)
Different fields of this register are defined as:
STRB_BYPASS: Strobe bypass; when this bit is set to ‘0’, it allows to change other fields
while FM is not enabled, but if it is set to ‘1’, other fields has to be static while FMPLL is
powered on,
SPRD_SEL: spread selection, if it is ‘0’, the FM is centre spread, if it is ‘1’, the FM is down
spread (see Figure 18),
MOD_PERIOD[12:0]: binary value of 
, where  =.
 and  is the
modulation frequency,
INC_STEP[14:0]: binary value of =󰇡××
××󰇢,
FM_EN: enable FM by writing ‘1’.
MOD_PERIOD and INC_STEP have to be calculated using selected values of  and in order
to respect the following limitation: _×_(2 1).
Recommended modulation depths are ±0.25% to±4% for center spread and 0.5% to8% for
down spread.
3.
A device initialisation procedure
We’ve seen different steps to follow for initialising the microcontroller, we can now write a
generic initialisation function that could be used for a lot of embedded applications.
The structure of the code will remain the same for most of the embedded applications:
Enable modes that may be used.
Make the clock configuration.
Mode configuration.
Peripheral configuration.
Transition towards a user mode.
CGM.FMPLL_MR.B.MOD_PERIOD = 20; /* fmod=50kHz */
CGM.FMPLL_MR.B.INC_STEP = 29; /* md = 0.1% */
CGM.FMPLL_MR.B.FM_EN = 1; /* enable FM */

Here’s an example for setting a 64MHz system clock and making SIUL (GPIO) run on this mode.
We could also write “ME.RUNPC[0].R = 0x00000010;” instead of RUNPC[1] to make all
peripherals run on RUN0, without needing PCTL lines, as all peripherals select RUNPC[0].
Use of FM for PLL is not recommended if there might be time sensitive applications. For example
it might induce transmission errors on CAN protocol if modulation depth and frequency are not
correctly selected1.
4.
SWT: Software Watchdog Timer
This timer is used to prevent system lock-up when the software is trapped in a loop or a bus
transaction failed. It is a 32-bit count-down timer, clocked by the 128kHz SIRC. A 32-bit time-out
value (minimum 0x100) value is specified (by default it’s 1280, so 10ms) and the software has
to enter some key sequence before timeout, otherwise a system reset is generated (it can be
modified to generate an interrupt first, and then a reset on a second timeout). By default this
module is frozen in the debug mode.
Using its configuration registers, this module is highly customisable for better fault detection, for
more details; see the chapter 30 of the reference manual rev.8, especially the paragraph 6. On
this document we will only give the code for disabling the watchdog in case it causes a problem.
1http://www.ti.com/lit/an/spna090/spna090.pdf : A Texas Instruments document that explains how to
choose the right values for FM parameters without affecting the CAN.
void disableWatchdog(void) {
SWT.SR.R = 0x0000c520; /* Write keys to clear soft lock bit */
SWT.SR.R = 0x0000d928;
SWT.CR.R = 0x8000010A; /* Clear watchdog enable (WEN) */
}
void initModesAndClock(void) {
ME.MER.R = 0x0000001D; /* Enable DRUN, RUN0, SAFE, RESET modes */
CGM.FMPLL_CR.R = 0x02400100; /* 8 MHz xtal: Set PLL0 to 64 MHz */
ME.RUN[0].R = 0x001F0074; /* RUN0 config: clock selection(FMPLL) */
ME.RUNPC[1].R = 0x00000010;
ME.PCTL[68].R = 0x01; /* SIUL use the configuration of RunPC[1]
add other peripherals as needed.*/
/* Mode Transition to enter RUN0 mode: */
ME.MCTL.R = 0x40005AF0; /* Enter RUN0 Mode & Key */
ME.MCTL.R = 0x4000A50F; /* Enter RUN0 Mode & Inverted Key */
while (ME.GS.B.S_MTRANS) {} /* Wait for mode transition to complete */
while(ME.GS.B.S CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */