Freescale Semiconductor QE128 User manual

QE128 Quick Reference User Guide
Devices Supported:
MCF51QE128
MC9S08QE128
Document Number: QE128QRUG
Rev. 1.0
10/2007

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QE128QRUG
Rev. 1.0
10/2007

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor -1
Chapter 1
QE Peripheral Module Quick Reference User Guide
Chapter 2
QE MCUs 8-bit and 32-bit Comparison
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.2 Cores Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.2.1 V1 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
2.2.2 QE S08 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
2.2.3 ColdFire V1 or 9S08QE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
2.3 Features Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
2.3.1 On-Chip Memory Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
2.3.2 Power-Saving Modes and Power-Saving Features Comparison . . . . . . . . . . 1-18
2.3.3 Package Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
2.3.4 Clock Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
2.3.5 System Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
2.3.6 Input/Output Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
2.3.7 Development Support Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
2.3.8 Peripherals Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Chapter 3
How to Load the QRUG Examples?
3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
3.2 Steps to programming the MCU using Multilink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
3.3 Steps to programming the MCU Using In-Circuit BDM. . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 4
Using the Keyboard Interrupt (KBI) for the QE Microcontrollers
4.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
4.2 KBI project for EVB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
4.2.1 Code example and explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
4.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
4.3 KBI project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
4.3.1 Code example and explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
4.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 5
Using the Internal Clock Source (ICS) for the QE Microcontrollers
5.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
5.2 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
5.3 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor-2
Chapter 6
Using the Inter-Integrated Circuit (IIC) for the QE Microcontrollers
6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
6.2 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
6.2.1 IIC Master Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
6.2.2 IIC Slave Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
6.3 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Chapter 7
Using the Analog Comparator (ACMP) for the QE Microcontrollers
7.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
7.2 ACMP project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
7.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
7.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
7.3 ACMP project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
7.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
7.3.2 Hardware Inplementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 8
Using the Analog to Digital Converter (ADC) for the QE Microcontrollers
8.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
8.2 ADC project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
8.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
8.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
8.3 ADC project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
8.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
8.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 9
Using the Real Time Counter (RTC) for the QE Microcontrollers
9.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
9.2 RTC project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
9.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
9.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
9.3 RTC project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
9.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
9.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Chapter 10
Using the Serial Communications Interface (SCI) for the QE Microcontrollers
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
10.2 SCI project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor -3
10.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
10.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
10.3 SCI project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
10.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
10.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Chapter 11
Using the Serial Peripheral Interface (SPI) for the QE Microcontrollers
11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
11.2 SPI project for EVB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
11.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
11.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
11.3 SPI project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
11.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
11.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Chapter 12
Generating PWM Signals Using Timer/Pulse-Width Modulator (TPM) Module
for the QE Microcontrollers
12.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
12.2 PWM project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
12.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
12.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
12.3 PWM project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
12.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
12.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 13
Using the Output Compare function with the Timer/Pulse-Width Modulator
(TPM) module for the QE Microcontrollers
13.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
13.2 TPM Project for EVB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
13.2.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
13.2.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
13.3 TPM project for Demo board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
13.3.1 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
13.3.2 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Chapter 14
Using the Rapid General Purpose I/O (RGPIO) for the MCF51QE128 Micro-
controllers
14.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor-4
14.2 Code Example and Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
14.3 Simulation steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
14.4 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor 1-1
Chapter 1
QE Peripheral Module Quick Reference User Guide
A Compilation of Demonstration Firmware for QE Modules
This document is a brief description of the QE128 microcontroller unit (MCU) in an 8-bit version and
32-bit version. There is also useful information about core differences.
This document is a compilation of code examples and quick reference materials that have been created to
help users speed the development of their applications. Each section in this document contains an example
that works with an evaluation board (EVB) and Demo board with both 8-bit and 32-bit cores versions.
These examples were developed using CodeWarriorTM 6.0 version. Consult the device reference manual
for specific part information.
NOTE
• The provided examples were made to be used with the MC9S08QE128
and MCF51QE128 in an 80-pin and 64-bit package, but could be easily
migrated to a different QE device, pay attention to the used pins.
• All the example projects were developed in two different boards:
EVBQE128 STARTER KIT and DEMO board, no extra hardware is
needed except for the ACMP module, SPI, and IIC.
Revision History
Date Revision
Level Description Page Number(s)
25-Jun-07 0 Initial public release. N/A
19-Oct-07 1.0 Changes in template, function names and other minor corrections. N/A

QE Peripheral Module Quick Reference User Guide
QE128 Quick Reference User Guide, Rev. 1.0
1-2 Freescale Semiconductor

QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor 2-1
Chapter 2
QE MCUs 8-bit and 32-bit Comparison
2.1 Overview
This is a brief explanation of MCU architectures. It has helpful informationabout cores, addressing modes
and exception processing. The intention of this section is to provide an overview of the S08 and V1 Core.
Further information can be found in reference manuals at www.freescale.com.
2.2 Cores Comparison
2.2.1 V1 core
The MCF51QE128, MCF51QE96, MCF51QE64 are members of the low-cost, low-power, high
performance ColdFire®V1 core (version 1) family of 32-bit MCUs. Figure 2-1 shows the ColdFire V1
core platform block diagram.
The ColdFire V1 core features are:
• Implements Instruction Set Revision C (ISA_C).
• Supports up to 30 peripheral interrupts and seven software interrupts.
• Built upon lowest-cost ColdFire V2 core microarchitecture.
• Two independent decoupled 2-stage pipelines.
• Debug architecture remapped into S08's single-pin BDM interface.

QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-2 Freescale Semiconductor
Figure 2-1. ColdFire V1 Core Platform Block Diagram
IA Generation
Instruction
Fetch Cycle
FIFO
Instruction
Buffer
Decode & Select,
Operand Fetch
Address
Generation,
Execute
IFP
OEP
IAG
IC
IB
DSOC
AGEX
BDC/Debug
Flash Array SRAM Array
Local
Controller
RGPIO
Controller
RGPIO
Pins
BKGD
Bus
Platform
V1 ColdFire
core
On-Platform Bus
Flash
Controller
RAM
Controller
Peripheral
Bridge
Write Data
Read Data
Address,
Attributes
Peripheral Bus
Off-Platform Off-Platform

QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
Freescale Semiconductor 2-3
The ColdFire V1 core has two programming models, the user and supervisor. First, is the user
programming model which is the same as the M68000 family microprocessors and consists of the
following registers:
• 16 general-purpose 32-bit registers (D0-D7, A0-A7)
• 32-bit program counter (PC)
• 8-bit condition code register (CCR)
Figure 2-2. User Programming Model Registers
Data registers (D0-D7) -- These registers are used for bit, byte, word or longword operations. It can also
be used as index registers for effective address (<ea>) calculations.
Address registers (A0-A6) -- These registers can be used as software stack pointers, index registers or
based address registers. They can also be used as data operation
storage,word and longword operations.
Figure 2-4. Address Registers (A0–A6)
A7 -- Is a user stack pointer and is treated specifically by CPU.
Program counter (PC) -- This register contains the address of the currently executing instruction. The
PCincrements itsvalue orcan beloaded withanew onewhen an instruction
is executing or when an exception occurs.
313029282726252423222120191817161514131211109876543210
RData
W
Figure 2-3. Data Registers (D0–D7)
313029282726252423222120191817161514131211109876543210
RAddress
W
D
0
Data Registers
D1
D2
D
3
D4
D
5
D6
D
7
3
1
0
A
0
Address Registers
A1
A2
A
3
A4
A
5
A6
A
7
3
1
0
S
P
P
C
CC
R

QE MCUs 8-bit and 32-bit Comparison
QE128 Quick Reference User Guide, Rev. 1.0
2-4 Freescale Semiconductor
Figure 2-5. Program Counter Register (PC)
Condition code register (CCR) -- This register reflects the result of most instruction flags. It is used to
evaluate the instructions of the conditional branches.
Second, is the supervisor programming model. This is intended to be used only by system control software
to implement restricted operating system functions: I/O control, and memory management. In the
supervisor programming model all registers and features of the ColdFire processors can be accessed and
modified. This consists of registers available in user mode and the following control registers:
• 16-bit status register (SR).
• 32-bit supervisor stack pointer (SSP).
• 32-bit vector base register (VBR).
• 32-bit CPU configuration register (CPUCR).
Status register (SR) — This is a 16-bit register. It stores the processor status and includes the condition
code register (CCR). When it is used in user mode only the lower 8-bit can
be accessed. When used in supervisor mode the registers can be accessed.
If a supervisor instruction is executed in user mode it generates a privilege
violation exception. Figure 2-8 shows the SR behavior in a state machine.
313029282726252423222120191817161514131211109876543210
RAddress
W
76543210
R000XNZVC
W
Figure 2-6. Condition Code Register (CCR)
Table 2-1. CCR Field Descriptions
Field Description
7–5 Reserved, must be cleared.
4
X
Extend condition code bit. Set to the C-bit value for arithmetic operations; otherwise not affected or set to a specified
result.
3
N
Negative condition code bit. Set if most significant bit of the result is set; otherwise cleared.
2
Z
Zero condition code bit. Set if result equals zero; otherwise cleared.
1
V
Overflow condition code bit. Set if an arithmetic overflow occurs implying the result cannot be represented in operand
size; otherwise cleared.
0
C
Carry condition code bit. Set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a
subtraction; otherwise cleared.

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Figure 2-8. Processor Status State Machine
Supervisor stack pointer (SSP) -- This ColdFire architecture supports two independent stack pointers,
A7 registers. Each operating mode has its own stack pointer, SSP and user
stackpointer (USP). Thehardware implementation ofthese tworegistersdo
not identify one as SSP and the other as USP. Instead, the hardware uses one
32-bit register as the active A7 and the other as, OTHER_A7.
System Byte Condition Code Register (CCR)
1514131211109876543210
RT0S M 0I000X N ZVC
W
Figure 2-7. Status Register (SR)
Table 2-2. SR Field Descriptions
Field Description
15
T
Trace enable. When set, the processor performs a trace exception after every instruction.
14 Reserved, must be cleared.
13
S
Supervisor/user state.
0Usermode
1 Supervisor mode
12
M
Master/interrupt state. Bit is cleared by an interrupt exception and software can set it during execution of the RTE or
move to SR instructions.
11 Reserved, must be cleared.
10–8
I
Interrupt level mask. Defines current interrupt level. Interrupt requests are inhibited for all priority levels less than or
equal to current level, except edge-sensitive level 7 requests, which cannot be masked.
7–0
CCR
Refer to MCF51QE128 Reference Manual.
SR[S] = 1 SR[S] = 0
Reset
Supervisor
Mode User Mode
Exception
Rte, move-to-sr with
sr_operand[13] = 1
Rte, move-to-sr with
sr_operand[13] = 0

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Figure 2-9. Stack Pointer Registers (A7 and OTHER_A7)
Vector base register (VBR) -- This register defines the base address of the exception vector table in the
memory. It has two different possible values: 0x(00)00_0000 exception
vector table based on the flash, and 0x(00)80_0000 exception vector table
based on the RAM. At reset the VBR is cleared. The VBR is located at the
base of the exception table at the address 0x(00)00_0000 in the flash.
Figure 2-10. Vector Base Register (VBR)
CPU configuration register (CPUCR) -- With this register you can configure some cores into supervisor
mode. Certain hardware features can be enabled or disabled based on the
state of the CPUCR.
Figure 2-11. CPU Configuration Register
2.2.1.1 Addressing Modes
The ColdFire V1 core counts with 12 different addressing modes. The addressing modes and syntax are
shown in Table 2-3:
313029282726252423222120191817161514131211109876543210
RAddress
W
313029282726252423222120191817161514131211109876543210
R00000000 Base
Address
00000000000000000 0 00
W
31 30 29 28 27 26252423222120191817161514131211109876543210
R
ARD IRD IAE IME BWD
0
FSD
0000000000000000000000 0 00
W
Table 2-3. Addressing Modes and Syntax
Addressing modes Syntax
Register Direct. op.sz1Ry,Rx
Address Register Indirect. op.sz (Ax),Rx
Address Register Indirect with Post-increment. op.sz (Ax)+,Rx
Address Register Indirect Pre-decrement. op.sz -(Ay),Rx
Address Register Indirect with Displacement. op.sz d16(Ay),Rx
Address Register Indirect with Scaled Index and Displacement. op.sz d8(Ay,Xi*SF),Rx
Program Counter Indirect with Displacement. op.sz d16(PC),Rx
Program Counter Indirect with Scaled Index and Displacement. op.sz d8(PC,Xi*SF),Rx)

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This is a syntax for a V1 core example:
2.2.1.2 Exception Processing
Exception processing is defined as processor-detected conditions that force an instruction stream
discontinuity because of a program or system error: a system call, a debug, or an I/O interrupt. The
ColdFire V1 core uses a reduced version of the interrupt controller from other ColdFire processors. This
hardware implementation is available only for a 32-bit MCU.
Absolute Short Addressing. op.sz xxx.w,Rx
Absolute Long Addressing. op.sz xxx.{l},Rx
Immediate Byte, Word. op.{b,w}2#imm,Rx
Immediate Long. op.l#imm3,Rx
1op.sz - operand size(size is 1 for byte, 2 for word, 4 for long).
2op.{b,w} - operand {byte,word}.
3op.l - operand long.
Source Destination
#0x55 Rx
Table 2-3. Addressing Modes and Syntax
Addressing modes Syntax

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The processor performs the following operations to process an exception:
Figure 2-12. Processor Operations Process
Interrupts are treated as lowest-priority exception type. CPU samples for halts and interrupts once per
instruction. The first instruction in ISR does not sample. Interrupts are guaranteed to be recoverable
exceptions.
ColdFire architecture reserves 64 entries for processor exceptions and the remaining 192 entries for I/O
interrupts. The ColdFire V1 core architecture only uses a relatively small number of the I/O interrupt
vector. Table 2-4 shows the ColdFire V1 core processor with the exception of the vector table.
313029282726252423222120191817161514131211109876543210
Format FS[3:2] Vector FS[1:0] Status Register
Program Counter
Figure 2-13. Exception Stack Frame Form
Saves a copy of the SR.
Forces:
SR[S]=1
SR[T]=0
If an interrupt forces
the interrupt
SR[M]=0
then sets
SR[I]=to the level of
Calculates the vector for
all internal exceptions.
For interrupts, the CPU
uses the vector number
supplied by the interrupt
controller or performs an
interrupt acknowledge
(IACK) cycle to retrieve
the I/O vector number.
Init
Saves the content at the
time of the exception by
storing a 64-bit
exception stack frame
(including the saved SR)
on the top of the
supervisor stack.
The processor fetches a
32-bit vector address
from the exception
vector table @ (VBR +
vector_number x 4). The
address defines the first
instruction of the
exception handler or
interrupts service routine
(ISR). Control is then
passed to the exception
handler at this address.
1
End
1

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Table 2-4. Vector Table
Vector
Number(s)
Vector
Offset(Hex)
Stacked
Program
Counter
Assignment
0 0x000 - Initial supervisor stack pointer
1 0x004 - Initial program counter
2-63 0x008-0x0FC - Reserved for internal CPU Exceptions
64 0x100 Next IRQ_pin
65 0x104 Next Low_voltage
66 0x108 Next TPM1_ch0
67 0x10C Next TPM1_ch1
68 0x110 Next TPM1_ch2
69 0x114 Next TPM1_ovfl
70 0x118 Next TPM2_ch0
71 0x11C Next TPM2_ch1
72 0x120 Next TPM2_ch2
73 0x124 Next TPM2_ovfl
74 0x128 Next SPI2
75 0x12C Next SPI1
76 0x130 Next SCI1_err
77 0x134 Next SCI1_rx
78 0x138 Next SCI1_tx
79 0x13C Next IICx
80 0x140 Next KBIx
81 0x144 Next ADC
82 0x148 Next ACMPx
83 0x14C Next SCI2_err
84 0x150 Next SCI2_rx
85 0x154 Next SCI2_tx
86 0x158 Next RTC
87 0x15C Next TPM3_ch0
88 0x160 Next TPM3_ch1
89 0x164 Next TPM3_ch2
90 0x168 Next TPM3_ch3
91 0x16C Next TPM3_ch4
92 0x170 Next TPM3_ch5
93 0x174 Next TPM3_ovfl
94-95 0x178-0x17C - Reserved; unused for V1
96 0x180 Next Level 7 Software Interrupt
97 0x184 Next Level 6 Software Interrupt
98 0x188 Next Level 5 Software Interrupt
99 0x18C Next Level 4 Software Interrupt
100 0x190 Next Level 3 Software Interrupt
101 0x194 Next Level 2 Software Interrupt
102 0x198 Next Level 1 Software Interrupt
103-255 0x19C-0x3FC - Reserved; unused for V1

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2.2.2 QE S08 core
This section provides summary information about the registers, addressing modes and core features. The
generated source and object-code is compatible with the M68HC08 CPU.
The S08 MCU supports only the user programming model. Figure 2-14 shows five CPU registers. These
registers are not part of the memory map.
Figure 2-14. CPU Registers
Accumulator -- The accumulator is a general-purpose 8-bit register. One operand input to the arithmetic
logic unit (ALU) is connected to the accumulator and the ALU results are
often stored in the accumulator after arithmetic and logical operations.
Index Register (H:X) -- This is a two separate 8-bit register, which often works together as a 16-bit
address pointer where H holds the upper byte of an address and X the lower
byte. All the indexing addressing mode instructions use the 16-bit register.
Stack pointer (SP) -- This 16-bit address pointer register points to the next available location on the
automatic last-in-first-out (LIFO). The stack is used to automatically store
the return address from subroutine calls or return from interrupts. It stores
the context in the interrupt service routine (ISR) and it stores the local
variables and parameters in function calls.
Program counter (PC) -- This register contains the next instruction or operand to be retrieved. This
register automatically increments to the next memory location during a
normal program execution.
Condition code register (CCR) -- This 8-bit condition code register contains the interrupt mask (I) and
five flags that indicate the results of the instruction just executed. Bits 5 and
6 are permanently set to 1.

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Figure 2-15. Condition Code Register
2.2.2.1 Addressing Modes
Addressing modes define the way the CPU accesses operand and data. The S08 core supports seven
different addressing modes:
n -- Any label or expression that evaluates to a single integer in the range 0-7
opr8i -- Any label or expression that evaluates to an 8-bit immediate value
opr16i -- Any label or expression that evaluates to a 16-bit immediate value
opr8a -- Any label or expression that evaluates to an 8-bit value
opr16a -- Any label or expression that evaluates to a 16-bit value
oprx8 -- Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing
oprx16 -- Any label or expression that evaluates to a 16-bit value
page -- Any label or expression that evaluates to a valid bank number for PPAGE register. Any value
between 0 and 7 is valid.
rel -- Any label or expression that refers to an address that is within -128 to +127 locations from the next
address after the last byte of object code for the current instruction.
A -- Accumulator
V - Two's complement Overflow Flag N - Negative flag
H - Half Carry Flag Z - Zero Flag
I - Interrupt Mask Bit C - Carry/Borrow flag
Table 2-5. Addressing Modes and Examples
Addressing Modes Example
Inherent --Operands in internal registers. ASLA – Arithmetic Shift Left A.
Relative -- 8-bit offset to branch destination. BEQ rel – Branch if equal
Immediate -- Operand in next object code byte. ADC #opr8i – Add with carry
Direct -- Operand in memory at 0x0000-0x00FF. ADC opr8a – Add with carry
Extended -- Operand within 64 Kbyte address space. ADC opr16a – Add with carry
Indexed relative to H:X. ADC oprx8,X – Add with carry
Indexed relative to SP. ADC oprx8,SP – Add with carry

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2.2.2.2 Interrupt Sequence
The S08 core interrupt sequence first completes the current instruction then attends the requested interrupt.
The CPU responds to an interrupt with the same sequence operation as in a software interrupt (SWI), and
it differs from the address used for the vector retrieved.
Figure 2-16. The CPU Interrupt Sequence
2.2.3 ColdFire V1 or 9S08QE
The ColdFire V1 and S08 cores have significant differences, even though the 32 bit ColdFire V1 core
presents improvements in performance. These differences are highlighted in the following section.
The ColdFire V1 architecture features, staged pipelining allows the core to process multiple instructions
at the same time.
Store PCL in SP
Store X in SP
Store PCH in SP
Store A in SP
Store PCL in SP
Store CCR in SP
Sets the | bit in the CCR
Fetches the high-order
half of the interrupt
vector
Fetches the low-order
half of the interrupt
vector
Delays for one free bus
cycle
Init 1
Fetches three bytes of
program information
starting at the address
indicated by the interrupt
vector
Fills the instruction
queue, preparing for
execution of the first
instruction in the
interrupt service routine
1
2
2
End