Freescale Semiconductor MPC8309KIT User manual

Freescale Semiconductor
Hardware KIT User Guide
© Freescale Semiconductor, Inc., 2011. All rights reserved.
1 Introduction
The MPC8309KIT is a two-board system: one is a processor
board called SOM that features the PowerQUICC processor,
MPC8309, and memory interfaces and the other a carrier
card that consists of external world interfaces terminated on
connector/header.
This is a low-cost, high-performance system solution that
consists of a printed circuit board (PCB) assembly plus a
software board support package (BSP) distributed in a CD
image. This BSP enables the fastest possible time-to-market
for development or integration of applications including
low-end base station, branch access gateway, test and
measurement equipment, DSLAM, and other infrastructure
equipments.
This document describes the hardware features of the board
including specifications, block diagram, connectors,
interfaces, and hardware straps. It also describes the board
settings and physical connections needed to boot the
MPC8309KIT. Finally, it talks about the software shipped
with this platform.
Document Number: MPC8309-KITUG
Rev. 0, 06/2011
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Required Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. MPC8309KIT Hardware . . . . . . . . . . . . . . . . . . . . . . . 2
4. Board-Level Functions . . . . . . . . . . . . . . . . . . . . . . . . 7
5. SOM Board Connectors . . . . . . . . . . . . . . . . . . . . . . 27
6. Carrier Board Connectors . . . . . . . . . . . . . . . . . . . . . 30
7. MPC8309KIT Board Configuration . . . . . . . . . . . . . 35
8. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10. MPC8309KIT Software . . . . . . . . . . . . . . . . . . . . . . 49
11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PowerQUICC MPC8309KIT
User’s Guide

PowerQUICC MPC8309KIT User’s Guide, Rev. 0
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Required Reading
When you finish reading this document, you should:
• Be familiar with the board layout
• Understand the default board configuration and your board configuration option
• Know how to get started and boot the board
• Know about the software and further documentation that supports the board
2 Required Reading
Use this manual in conjunction with following documents:
•MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual
(MPC8309RM)
•MPC8309 PowerQUICC II Pro Processor Hardware Specifications (MPC8309EC)
•Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582)
NOTE
This equipment has been tested and found to comply with the limits for a
Class A digital device, pursuant to part 15 of the FCC rules. These limits are
designed to provide reasonable protection against harmful interference
when the equipment is operated in a commercial environment. This
equipment generates, uses, and can radiate radio frequency energy and, if
not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment
in a residential area is likely to cause harmful interference in which case the
user is required to correct the interference at his own expense.
3 MPC8309KIT Hardware
This section covers the features, block diagram, specifications, and mechanical data of MPC8309KIT
(SOM + Carrier) board.
3.1 Features
• CPU: Freescale MPC8309 e300 core running at 333/266 MHz; CPU Coherent system bus (CSB)
running at 133 MHz
• Memory subsystem:
— 256 MByte unbuffered DDR2 SDRAM discrete devices
— 8 MByte NOR Flash single chip memory
— 512 MByte NAND Flash memory
— 256 Kbit serial EEPROM
•Interfaces:
— 10/100 Base-T Ethernet ports:

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MPC8309KIT Hardware
– FEC1 MII/RMII: one 10/100 Base-T RJ-45 interface using Micrel™ KSZ8001 10/100
Base-T PHY on SOM card
– FEC2 MII/RMII: one 10/100 Base-T interfaced with 5-Port Switch (PSB6972) on carrier
card
– FEC3 MII/RMII: one 10/100 Base-T RJ-45 interface using Micrel™ KSZ8001 10/100
Base-T PHY on carrier card
— USB 2.0 Port:
– USB ULPI signals are interfaced with USB3300 PHY device on carrier card.
— eSDHC Port:
– One microSD Card Connector
— Dual UART Ports:
– UART1 supports up to 115200bps (RS232) terminated on 3-Pin Header on SOM and DB9
connector on carrier card
– UART2 port converted in to RS-485 and terminated on a DB9 connector on carrier card
—I
2C
–I
2C1: Connected to Microchip™ 24LC256 Serial EEPROM
–I
2C2: Connected to I/O expander PCA9534 on carrier card
— Flex CAN module
– CAN: Interfaced with one CAN transceiver (MCZ33902F) on carrier card
• SOM Board Connectors:
— 3 pin power jack connector
— 3 pin UART header for console
— JTAG/COP for debugging
— 120 pin and 140 pin board-to-board connector
— 6 pin BDM header for KA2 programming
— RJ45 for Ethernet connectivity
— MicroSD card connector
— 6 pin header for boot device (NAND/NOR) selection
• Carrier board connectors:
— Mini PCIe(x1) card edge connector (not used in MPC8309KIT)
— PCI card edge connector
— Mini PCI card edge connector
— Dual stack DB9 female connector for RS-232 console and RS-485
— 2x2 RJ45 connector for Ethernet switch
— Unshielded RJ45 connector for T1/E1
— MiniAB USB connector
— Microcontroller UART header
— Microcontroller BDM header.

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MPC8309KIT Hardware
— Shielded RJ45 connector for FEC-3
— 4-Pin CAN header
— RJ-11 connector for SLIC/PSTN phone interface
— 60 pin local bus connector on carrier for future expansion
— 120 pin and 140 pin board-to-board connector
— 16 Pin SPI and IEEE 1588 Header on carrier for future expansion and measurement
— 16 pin GPIO header
• Form Factor:
— SOM: 90 mm x 70 mm
— Carrier: 170 mm x 170 mm
• 6-Layer PCB (4-layer signals, 2-layer power and ground) routing
• Certification
— FCC Class-A
—CE
• Lead free (RoHS)

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MPC8309KIT Hardware
This figure shows MPC8309SOM block diagram.
Figure 1. MPC8309 SOM Block Diagram

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MPC8309KIT Hardware
This figure shows MPC830X carrier block diagram.
Figure 2. MPC830X Carrier Block Diagram
3.2 MPC8309KIT Specifications
This table lists the specifications of MPC8309KIT.
Table 3-1. Specifications of MPC8309KIT
Characteristics Specifications
Power Requirement SOM stand-alone
MPC8309 KIT 5 VDC @ 1A 12 VDC @ 5A
Communication Processor MPC8309 running @ 333 MHz
Addressing: Total address range
Flash memory (local bus)
DDR2 SDRAM
4 GByte (32 address lines)
8 MByte with one chip-select
256 MByte DDR2 SDRAM
Operating temperature MPC8309SOM
MPC830X_Carrier –40 °C to 85 °C
0 °C to 70 °C
Storage Temperature –40 °C to 125 °C

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Board-Level Functions
3.3 Mechanical Data
This figure shows MPC8309KIT dimensions (in mm). The MPC830X carrier board measures
170 x 170 mm and MPC8309SOM board measures 90 x 70 mm.
Figure 3. MPC8309KIT Dimension
4 Board-Level Functions
The board-level functions include reset, external interrupts, clock distribution, DDR SDRAM controller,
local bus controller, I2C, SPI, SD memory card interface, FEC-1/2/3 interface, CAN interface, RS-232,
RS-485, KA2 microcontroller, PCI, MiniPCI, COP/JTAG interface, and USB interface.
Relative Humidity —
PCB dimensions SOM Board (LxWxT)
Carrier Board (LxWxT) 90 mm x 70 mm x 1.63 mm 170 mm x 170 mm x 1.63 mm
Table 3-1. Specifications of MPC8309KIT (continued)
Characteristics Specifications

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Board-Level Functions
4.1 Reset and Reset Configurations
An MPC8309KIT module generates single reset to the MPC8309 and other peripherals on the board. The
reset unit provides power-on reset, hard reset, and soft reset signals in compliance with the MPC8309
hardware specification. Figure 4 shows the reset scheme on board.
• PORESET# (power-on reset) is generated by TI Power Management IC TPS65023. When MR#
(Manual Reset) is deasserted and 3.3 V is ready, the TPS65023 internal timeout guarantees a
minimum reset active time of 100 ms before PORESET# is deasserted. Push button reset interfaces
the MR signal with debounce capability to produce a manual master PORESET#.
• MPC8309 POR# input is also generated by MC9RS08KA2 microcontroller device by monitoring
I2C–I/O expander GPIO status based loading of Reset configuration word from boot device on
SOM board.
• HRESET# (hard reset) is generated either by the MPC8309 or the COP/JTAG port.
• COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller. The
HRESET# line is available at the COP/JTAG port connector. The COP/JTAG controller can
directly generate the hard-reset signal by asserting this line low. As shown in Figure 4, it allows the
COP to independently assert HRESET# or TRST# while ensuring that the MPC8309 can drive
HRESET# as well.
• Carrier_RST# is used to provide POR signal to the devices on carrier card. This signal is generated
by ANDing carrier_POR# and HRESET# signal generated by MPC8309.
This figure shows reset circuitry of MPC8309KIT.
Figure 4. Reset Circuitry of MPC8309KIT

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Board-Level Functions
4.2 External Interrupts
This figure shows external interrupt circuitry of MPC8309KIT.
Figure 5. Interrupt Circuitry of MPC8309KIT
• All external interrupt signals are pulled up by 4.7 K resistors.
• Either PHY (KSZ8001) interrupt (FEC1_IRQ#) or FRMR_IRQ# is connected to IRQ0# of
MPC8309. The selection between FEC1_IRQ# and FRMR_IRQ# can be done through resistor
mount/No mount. Default IRQ0 is connected to FRMR_IRQ#.
• Option provided to connect SLIC and Framer device interrupt (FRMR_IRQ#) to be ANDed and
given to IRQ1# of MPC8309. By default, only SLIC Interrupt is connected to IRQ1.
• Interrupt from PCI and miniPCI card is given to IRQ2 of MPC8309.
• MCU interrupt (MCU_IRQ#) and thermal interrupt (THERM_IRQ#) are ANDed and given to
IRQ3 of MPC8309.

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Board-Level Functions
4.3 Clock Distribution
This figure shows clock distribution on SOM board.
Figure 6. Clock Distribution on MPC8309KIT
The table shows the clock distribution on MPC8309KIT (SOM + Carrier) board.
Table 4-2. MPC8309SOM and Carrier Clock Distribution
Clock
Frequency Module Generated by Description
33.33 MHz MPC8309
CLKIN 33.33 MHz OSC The MPC8309 uses CLKIN to generate the internal system PLL. The CSB clock is generated by the internal PLL and is fed to the e300 core PLL for
generating the e300 core clock.
133 MHz DDR2 SDRAM MPC8309 The DDR memory controller is configured to use the 2:1 mode CSB to DDR
for the DDR interface (DDR266). The local bus clock uses 1:1 local to CSB
clock, which is configured by hard reset configuration or SPMR register.
32.76 KHz Real Time
Clock 32.76 KHz OSC Clock for RTC
25 MHz MPC QE and
FEC1 PHY
Clock
25 MHZ OSC
and 1:4 Clock
buffer
The 25 MHz oscillator provides the clock for MPC8309 QUICC Engine and
FEC1 PHY KSZ8001.