Freescale Semiconductor MPC8309KIT User manual

Freescale Semiconductor
Hardware KIT User Guide
© Freescale Semiconductor, Inc., 2011. All rights reserved.
1 Introduction
The MPC8309KIT is a two-board system: one is a processor
board called SOM that features the PowerQUICC processor,
MPC8309, and memory interfaces and the other a carrier
card that consists of external world interfaces terminated on
connector/header.
This is a low-cost, high-performance system solution that
consists of a printed circuit board (PCB) assembly plus a
software board support package (BSP) distributed in a CD
image. This BSP enables the fastest possible time-to-market
for development or integration of applications including
low-end base station, branch access gateway, test and
measurement equipment, DSLAM, and other infrastructure
equipments.
This document describes the hardware features of the board
including specifications, block diagram, connectors,
interfaces, and hardware straps. It also describes the board
settings and physical connections needed to boot the
MPC8309KIT. Finally, it talks about the software shipped
with this platform.
Document Number: MPC8309-KITUG
Rev. 0, 06/2011
Contents
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Required Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. MPC8309KIT Hardware . . . . . . . . . . . . . . . . . . . . . . . 2
4. Board-Level Functions . . . . . . . . . . . . . . . . . . . . . . . . 7
5. SOM Board Connectors . . . . . . . . . . . . . . . . . . . . . . 27
6. Carrier Board Connectors . . . . . . . . . . . . . . . . . . . . . 30
7. MPC8309KIT Board Configuration . . . . . . . . . . . . . 35
8. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10. MPC8309KIT Software . . . . . . . . . . . . . . . . . . . . . . 49
11. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
PowerQUICC MPC8309KIT
User’s Guide

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Required Reading
When you finish reading this document, you should:
• Be familiar with the board layout
• Understand the default board configuration and your board configuration option
• Know how to get started and boot the board
• Know about the software and further documentation that supports the board
2 Required Reading
Use this manual in conjunction with following documents:
•MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Reference Manual
(MPC8309RM)
•MPC8309 PowerQUICC II Pro Processor Hardware Specifications (MPC8309EC)
•Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582)
NOTE
This equipment has been tested and found to comply with the limits for a
Class A digital device, pursuant to part 15 of the FCC rules. These limits are
designed to provide reasonable protection against harmful interference
when the equipment is operated in a commercial environment. This
equipment generates, uses, and can radiate radio frequency energy and, if
not installed and used in accordance with the instruction manual, may cause
harmful interference to radio communications. Operation of this equipment
in a residential area is likely to cause harmful interference in which case the
user is required to correct the interference at his own expense.
3 MPC8309KIT Hardware
This section covers the features, block diagram, specifications, and mechanical data of MPC8309KIT
(SOM + Carrier) board.
3.1 Features
• CPU: Freescale MPC8309 e300 core running at 333/266 MHz; CPU Coherent system bus (CSB)
running at 133 MHz
• Memory subsystem:
— 256 MByte unbuffered DDR2 SDRAM discrete devices
— 8 MByte NOR Flash single chip memory
— 512 MByte NAND Flash memory
— 256 Kbit serial EEPROM
•Interfaces:
— 10/100 Base-T Ethernet ports:

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MPC8309KIT Hardware
– FEC1 MII/RMII: one 10/100 Base-T RJ-45 interface using Micrel™ KSZ8001 10/100
Base-T PHY on SOM card
– FEC2 MII/RMII: one 10/100 Base-T interfaced with 5-Port Switch (PSB6972) on carrier
card
– FEC3 MII/RMII: one 10/100 Base-T RJ-45 interface using Micrel™ KSZ8001 10/100
Base-T PHY on carrier card
— USB 2.0 Port:
– USB ULPI signals are interfaced with USB3300 PHY device on carrier card.
— eSDHC Port:
– One microSD Card Connector
— Dual UART Ports:
– UART1 supports up to 115200bps (RS232) terminated on 3-Pin Header on SOM and DB9
connector on carrier card
– UART2 port converted in to RS-485 and terminated on a DB9 connector on carrier card
—I
2C
–I
2C1: Connected to Microchip™ 24LC256 Serial EEPROM
–I
2C2: Connected to I/O expander PCA9534 on carrier card
— Flex CAN module
– CAN: Interfaced with one CAN transceiver (MCZ33902F) on carrier card
• SOM Board Connectors:
— 3 pin power jack connector
— 3 pin UART header for console
— JTAG/COP for debugging
— 120 pin and 140 pin board-to-board connector
— 6 pin BDM header for KA2 programming
— RJ45 for Ethernet connectivity
— MicroSD card connector
— 6 pin header for boot device (NAND/NOR) selection
• Carrier board connectors:
— Mini PCIe(x1) card edge connector (not used in MPC8309KIT)
— PCI card edge connector
— Mini PCI card edge connector
— Dual stack DB9 female connector for RS-232 console and RS-485
— 2x2 RJ45 connector for Ethernet switch
— Unshielded RJ45 connector for T1/E1
— MiniAB USB connector
— Microcontroller UART header
— Microcontroller BDM header.

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MPC8309KIT Hardware
— Shielded RJ45 connector for FEC-3
— 4-Pin CAN header
— RJ-11 connector for SLIC/PSTN phone interface
— 60 pin local bus connector on carrier for future expansion
— 120 pin and 140 pin board-to-board connector
— 16 Pin SPI and IEEE 1588 Header on carrier for future expansion and measurement
— 16 pin GPIO header
• Form Factor:
— SOM: 90 mm x 70 mm
— Carrier: 170 mm x 170 mm
• 6-Layer PCB (4-layer signals, 2-layer power and ground) routing
• Certification
— FCC Class-A
—CE
• Lead free (RoHS)

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MPC8309KIT Hardware
This figure shows MPC8309SOM block diagram.
Figure 1. MPC8309 SOM Block Diagram

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MPC8309KIT Hardware
This figure shows MPC830X carrier block diagram.
Figure 2. MPC830X Carrier Block Diagram
3.2 MPC8309KIT Specifications
This table lists the specifications of MPC8309KIT.
Table 3-1. Specifications of MPC8309KIT
Characteristics Specifications
Power Requirement SOM stand-alone
MPC8309 KIT 5 VDC @ 1A 12 VDC @ 5A
Communication Processor MPC8309 running @ 333 MHz
Addressing: Total address range
Flash memory (local bus)
DDR2 SDRAM
4 GByte (32 address lines)
8 MByte with one chip-select
256 MByte DDR2 SDRAM
Operating temperature MPC8309SOM
MPC830X_Carrier –40 °C to 85 °C
0 °C to 70 °C
Storage Temperature –40 °C to 125 °C

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Board-Level Functions
3.3 Mechanical Data
This figure shows MPC8309KIT dimensions (in mm). The MPC830X carrier board measures
170 x 170 mm and MPC8309SOM board measures 90 x 70 mm.
Figure 3. MPC8309KIT Dimension
4 Board-Level Functions
The board-level functions include reset, external interrupts, clock distribution, DDR SDRAM controller,
local bus controller, I2C, SPI, SD memory card interface, FEC-1/2/3 interface, CAN interface, RS-232,
RS-485, KA2 microcontroller, PCI, MiniPCI, COP/JTAG interface, and USB interface.
Relative Humidity —
PCB dimensions SOM Board (LxWxT)
Carrier Board (LxWxT) 90 mm x 70 mm x 1.63 mm 170 mm x 170 mm x 1.63 mm
Table 3-1. Specifications of MPC8309KIT (continued)
Characteristics Specifications

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Board-Level Functions
4.1 Reset and Reset Configurations
An MPC8309KIT module generates single reset to the MPC8309 and other peripherals on the board. The
reset unit provides power-on reset, hard reset, and soft reset signals in compliance with the MPC8309
hardware specification. Figure 4 shows the reset scheme on board.
• PORESET# (power-on reset) is generated by TI Power Management IC TPS65023. When MR#
(Manual Reset) is deasserted and 3.3 V is ready, the TPS65023 internal timeout guarantees a
minimum reset active time of 100 ms before PORESET# is deasserted. Push button reset interfaces
the MR signal with debounce capability to produce a manual master PORESET#.
• MPC8309 POR# input is also generated by MC9RS08KA2 microcontroller device by monitoring
I2C–I/O expander GPIO status based loading of Reset configuration word from boot device on
SOM board.
• HRESET# (hard reset) is generated either by the MPC8309 or the COP/JTAG port.
• COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller. The
HRESET# line is available at the COP/JTAG port connector. The COP/JTAG controller can
directly generate the hard-reset signal by asserting this line low. As shown in Figure 4, it allows the
COP to independently assert HRESET# or TRST# while ensuring that the MPC8309 can drive
HRESET# as well.
• Carrier_RST# is used to provide POR signal to the devices on carrier card. This signal is generated
by ANDing carrier_POR# and HRESET# signal generated by MPC8309.
This figure shows reset circuitry of MPC8309KIT.
Figure 4. Reset Circuitry of MPC8309KIT

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Board-Level Functions
4.2 External Interrupts
This figure shows external interrupt circuitry of MPC8309KIT.
Figure 5. Interrupt Circuitry of MPC8309KIT
• All external interrupt signals are pulled up by 4.7 K resistors.
• Either PHY (KSZ8001) interrupt (FEC1_IRQ#) or FRMR_IRQ# is connected to IRQ0# of
MPC8309. The selection between FEC1_IRQ# and FRMR_IRQ# can be done through resistor
mount/No mount. Default IRQ0 is connected to FRMR_IRQ#.
• Option provided to connect SLIC and Framer device interrupt (FRMR_IRQ#) to be ANDed and
given to IRQ1# of MPC8309. By default, only SLIC Interrupt is connected to IRQ1.
• Interrupt from PCI and miniPCI card is given to IRQ2 of MPC8309.
• MCU interrupt (MCU_IRQ#) and thermal interrupt (THERM_IRQ#) are ANDed and given to
IRQ3 of MPC8309.

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Board-Level Functions
4.3 Clock Distribution
This figure shows clock distribution on SOM board.
Figure 6. Clock Distribution on MPC8309KIT
The table shows the clock distribution on MPC8309KIT (SOM + Carrier) board.
Table 4-2. MPC8309SOM and Carrier Clock Distribution
Clock
Frequency Module Generated by Description
33.33 MHz MPC8309
CLKIN 33.33 MHz OSC The MPC8309 uses CLKIN to generate the internal system PLL. The CSB clock is generated by the internal PLL and is fed to the e300 core PLL for
generating the e300 core clock.
133 MHz DDR2 SDRAM MPC8309 The DDR memory controller is configured to use the 2:1 mode CSB to DDR
for the DDR interface (DDR266). The local bus clock uses 1:1 local to CSB
clock, which is configured by hard reset configuration or SPMR register.
32.76 KHz Real Time
Clock 32.76 KHz OSC Clock for RTC
25 MHz MPC QE and
FEC1 PHY
Clock
25 MHZ OSC
and 1:4 Clock
buffer
The 25 MHz oscillator provides the clock for MPC8309 QUICC Engine and
FEC1 PHY KSZ8001.

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Board-Level Functions
4.4 DDR2 SDRAM Controller
TheMPC8309processor uses DDR2SDRAMasthe system memory.TheDDR2interfaceusesthe SSTL2
driver/receiver and 1.8 V power. A Vref 1.8V/2 is needed for all SSTL2 receivers in the DDR2 interface.
Since DDR2 SDRAM chip operates at 1.8V and uses SSTL2 interface, it directly interfaces with the
MPC8309 without any level translation. The 1.8 V interface is provided by an on-board voltage regulator.
VREF, which is half the interface voltage (0.9V), is provided by a voltage divider of the 1.8 V for voltage
tracking. SOM board is configured to run DDR2 memory @ Max 133 MHz, that is, DATA RATE of
266 MHz.
This figure shows DDR2 SDRAM connection.
Figure 7. DDR2 SDRAM Connection
2.048/1.544
MHz T1/E1 Clock 2.048/1.544 MHz OSC and 1:4
Clock buffer
The 2.048/1.544 MHz oscillator provided clock for T1/E1 framer on carrier
card and MPC8309TDM section.
24 MHz ULPI external
USB PHY 24 Mhz Crystal Clock for ULPI USB PHY USB3300
25 MHz 5PortEthernet
Switch and
FEC3 PHY
25 MHz OSC. The 25 MHz oscillator provides the clock for the 5 Port Ethernet switch.
32.768 KHz Microcontroller 32.768 KHz
Crystal MC9S08QG8CDT microcontroller on carrier
50 MHz IEEE1588
Clock (TMR
Clock)
50 MHz
Oscillator
/50 MHz VCXO
50 MHz is used by IEEE 1588 module. It is VCXO controlled by SPI DAC.
Table 4-2. MPC8309SOM and Carrier Clock Distribution (continued)
Clock
Frequency Module Generated by Description

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Board-Level Functions
4.5 Local Bus Controller
The MPC8309 local bus controller (LBC) has multiplexed address and data lines LAD[0:15] and
non-multiplexed address lines LA[16:25]. Thus, address latch and data buffer need to be used to interface
standard memory devices for non-multiplexed address and data bus.
The following modules are connected to the local bus of MPC8309:
• 8 MByte NOR Flash memory
• 512 MByte NAND Flash memory
• T1/E1 Framer local bus interface
• Local bus signals are terminated in a 60-pin connector on carrier card for future expansion
4.5.1 NOR Flash Memory Interface
This section describes NOR Flash memory interface to MPC8309 local bus. Through the general-purpose
chip-select machine (GPCM), the MPC8309 SOM provides an 8 MByte of Flash memory using
chip-select and local bus control signals. Local bus address and data are multiplexed so that address latch
and a data buffer are used between MPC8309 and NOR Flash interface.
This figure shows NOR Flash interface block diagram.
Figure 8. NOR Flash Interface Block Diagram
NOTE
NOR_CS# can be either CS0# or CS1# by J3 Header Jumper settings;
default is CS0#.
4.5.2 NAND Flash Memory Interface
This section describes NAND Flash memory interface to MPC8309. The MPC8309 has native support for
NAND Flash memory through its NAND Flash control machine (FCM). eLBC interface of MPC8309
provides glueless interface to NAND Flash memory. MPC8309 supports 16-bits wide eLBC interface.
NAND Flash interface of SOM Card is 8-bit wide.

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Board-Level Functions
This figure shows NAND Flash interface block diagram.
Figure 9. NAND Flash Interface Block Diagram
NOTE
NAND_CS# can be either CS0# or CS1# by J3 Header Jumper settings;
default is CS1#.
4.5.3 DS2155 Parallel Port Interface
T1/E1 transceiver (DS2155) is having an 8-bit parallel port interface for configuration purpose. DS2155
parallel port is interfaced with MPC8309 local bus controller in GPCM mode as shown in Figure 10.
DS2155 is interfaced on CS2# of MPC8309.
This figure shows DS2155 framer parallel interface connection.
Figure 10. DS2155 Framer Parallel Interface Connection
4.6 I2C Interfaces
The MPC8309 has two I2C interfaces: I2C1 and I2C2. All I2C lines are pulled up with 4.7-K resister.
4.6.1 I2C1 Interface
The following components are interfaced on the I2C1 as per MPC8309KIT specifications:
• Serial EEPROM 24LC256-I/SM at address 0x50
•4-BitI
2C I/O expander PCA9536 at address 0x41
• MCU MC9S08QG8CDT on carrier card through board-to-board connector

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Board-Level Functions
• DAC AD5301BRMZ at address 0x48 on carrier card through board-to-board connector
• Temperature sensor device LM75 is connected at 0x90 address
This figure shows I2C1 Interface block diagram.
Figure 11. I2C1 Interface Block Diagram
The I2C EEPROM is used to store the configuration registers values and booting purpose during boot
sequencer mode. Boot sequencer mode is selected at power-on reset by the BOOTSEQ field of the
high-order reset configuration word. If boot sequencer mode is selected, the I2C module communicates
with one or more EEPROMs through the I2C interface.
I2C1 is also connected to the MC9S08QG8CDT on carrier card through board-to-board connector.
MC9S08QG8CDT microcontroller unit is used for the fan control.
PCA9536 4-bit I/O expander on I2C1 line is used to provide on-board general purpose I/O for mux/demux
control and boot status GPIO.
DAC AD5301BRMZ (used for IEEE 1588 interface) is connected to I2C1 at address 0x48 on carrier card
through board-to-board connector.
4.6.2 I2C2 Interfaces
I2C2 lines are connected to the following devices:
• I/O Expander—1 PCA9534DW at address 0x20
• I/O Expander—2 PCA9534DW at address 0x21

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Board-Level Functions
This figure shows I2C2 interface block diagram.
Figure 12. I2C2 Interface Block Diagram
I2C2 is used to connect 8-bit I/O expander PCA9534DW on carrier card. PCA9534DW is an 8-bit I2C to
parallel port expander. PCA9534DW provides general-purpose remote I/O expansion for most
microcontroller families via the I2C interface [serial clock (SCL), serial data (SDA)]. There are two I/O
expanders on carrier card providing a total of 16 bit GPIO.
The table shows I2C I/O expander–based GPIO signal assignment on carrier and SOM cards.
Table 4-3. I2C I/O Expander Based GPIO Signal Assignment on Carrier and SOM Cards
I/O Port Signal Name Description
SOM BOARD GPIO
I/O Expander (PCA9536) U24 GPIO
IO0 CAN/SD_MUX_CTL CAN and SDIO signals mux/demux selections
IO1 NC No connect
IO2 BOOT_STAUS_GPIO GPIO for checking processor boot status
IO3 CARRIER_PRESENT Detect stand-alone/carrier card availability
Carrier Board GPIO
I/O Expander-1 (U21 -PCA9534) GPIO
P0 MPC_SLIC_SPI_CS# SLIC SPI Chip select

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Board-Level Functions
4.7 SPI Interface
SPI interface is connected to the following devices on MPC8309KIT:
• Boot SPI EEPROM Flash on SOM card
• Si3210 SLIC on carrier card
P1 MPC_EEPROM_SPI_CS# SPI EEPROM Chip select (unused)
P2 SPI_MUX_CNTL SPI EEPROM and MPC8309 SPI MUX selection (unused)
P3 FEC3_IEEE1588_MUX_CNTL FEC3 and IEEE 1588 mux/demux control
P4 PCIe_WAKE# PCIe card wake signal
P5 MPC_GPIO_CAN_EN CAN transceiver control
P6 MPC_GPIO_CAN_STY# CAN transceiver control
P7 MPC_GPIO_CAN_ERR# CAN transceiver control
I/O Expander-2 (U39 - PCA9534) GPIO
P0 SW_UPDATE_RST# Switch software update signal (unused)
P1 I2C_EXPND_GPIO1 Terminated on LED D9
P2 I2C_EXPND_GPIO2 Terminated on LED D10
P3 I2C_EXPND_GPIO3 Terminated on LED D11
P4 I2C_EXPND_GPIO4 Terminated on LED D12
P5 I2C_EXPND_GPIO5 Terminated on LED D8
P6 USB_SLIC SEL USB and SLIC mux/demux selections
P7 I2C_EXPND_GPIO7 Terminated on Header J17
Table 4-3. I2C I/O Expander Based GPIO Signal Assignment on Carrier and SOM Cards (continued)
I/O Port Signal Name Description
SOM BOARD GPIO
I/O Expander (PCA9536) U24 GPIO

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Board-Level Functions
This figure shows SPI interface block in MPC8309KIT.
Figure 13. SPI Interface Block in MPC8309KIT
The SPI EEPROM is used to store the configuration registers values for booting purpose. During normal
operation, the SPI EEPROM is not used.
Si3210 PROSLIC is being configured through SPI interface of MPC8309. Chip select of SLIC SPI
interface is generated through PCA954DW I/O expander on carrier card as shown in Figure 13.
4.8 Micro SD Card Interface
MPC8309 has on-chip SDIO controller (eSDHC controller), which provides glueless interface to
removable memory storage interfaces such as SDIO and MMC. The micro SD card can transfer data up to
maximum of 33.25 MHz clock speed. The card insertion detect and the write protect signals of connector
are mechanical switched signals. These signals are connected to MPC8309 GPIO/WP.
This figure shows micro SD card interface block diagram.
Figure 14. Micro SD Card Interface Block Diagram

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Board-Level Functions
NOTE
Power-down the board/system while inserting and removing SD card.
4.9 USB Interface
MPC8309 supports USB 2.0 host/device/OTG interface through external USB ULPI PHY. As shown in
Figure 15, USB signals from the MPC8309 SOM go to the carrier card through the board-to-board
connector.
This figure shows USB connection on MPC8309KIT.
Figure 15. USB Interface Block Diagram
NOTE
USB interface is multiplexed with TDM2 interface. Thislimitation is due to
pin muxing of 8309SoC. So either USB or TDM2 (SLIC) interface can be
used at a time. For configuration of either USB or TDM2 (SLIC) interface,
refer LTIB documentation
4.10 FEC 10/100 Base-T Interface
MPC8309 have three fast Ethernet controller named as FEC1, FEC2, and FEC3. Following are the details
of FEC1, FEC2, and FEC3 port:
• FEC1 port is interfaced on SOM board working in MII mode
• FEC2 port is interfaced to 5-port Ethernet switch on carrier board through board-to-board
connector
• FEC3 port is interfaced to 10/100 Mbps PHY (MII mode) on carrier board through board-to-board
connector

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Board-Level Functions
4.10.1 FEC1 Interface
The FEC-1 port is used to provide network connectivity and allow data transfer over Ethernet on
MPC8309SOM board. The external PHY KSZ8001 is connected to MPC8309 FEC1 port through MII
interface. FEC1 controls the flow of data packets from the system to external PHY. The MDIO
(management data input/output) module controls PHY configuration and status monitoring as shown in
Figure 16. The PHY address connects FEC1 at 0x11.
Figure 16. FEC1 Interface Block Diagram
4.10.2 FEC2 Interface
FEC-2 port of MPC8309 is connected with 5-Port Ethernet switch (PSB6972) through MII interface. One
MII port of switch is connected to FEC2 of MPC8309 on carrier card. The FEC2 signals from the
8309 SoC goes on carrier through carrier–SOM board-to-board connector and interfaced with 5-Port
switch as shown in Figure 17. The MII port of Ethernet switch is configured to operate in “Reverse MII”
mode for MAC-to-MAC connection.
Figure 17. FEC2 Interface Block Diagram

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Board-Level Functions
The MDIO modules is used for switch configuration and status monitoring. The downlink of switch is 4x
10/100 port terminated in 2x2 RJ-45 connector on carrier card through magnetic as shown in above figure.
NOTE
Switch registers are accessed through SMI interface of switch and
MDC/MDIO interface of MPC8309. Because of register addressing scheme
of Ethernet switch over SMI interface, PHY address ranges from 0x00 to
0x0F blocking MDC/MDIO interface.
Hence any external PHY used with this switch need to be addressed from 0x10 to 0x1F.
4.10.3 FEC3 Interface
FEC3 port of MPC8309 is connected to an external PHY KSZ8001 on carrier card over MII interface and
terminated to an RJ-45 connector as shown in Figure 18. This provides additional network port
connectivity on carrier card. FEC3 MII port of MPC8309 is multiplexed with IEEE 1588 signals, so a
12-bit mux/demux IC is used on carrier card for interface selection. By default, MII interface is selected.
MII signals travel through board-to-board connector on carriercarrier card.
Figure 18. FEC3 Interface Block Diagram
The MDIO module controls PHY configuration and status monitoring.
NOTE
Improper insertion of SOM card can result in Ethernet connectivity issue on
FEC2 and FEC3.
4.11 DUART Interface
DUART provides support for RS232 and RS485 connectivity. UART1 is used for RS232 signaling and
UART2 for RS485 signaling.
MAX3221—RS232 transceiver—is used to provide RS232 connectivity on UART1 port. UART2 port is
used to provide RS485 connectivity through SN65HVD33D—a RS485 driver/receiver.