GOWIN DK_START_GW2AR-LV18EQ144PC8I7 User manual

DK_START_GW2AR-LV18EQ144PC8I7_V1.
1
User Guide
DBUG405-1.0E, 09/06/2021

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
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assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
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preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
09/06/2021
1.0E
Initial version published.

Contents
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback .......................................................................................................2
2Development Board Description..................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................ 4
2.3 PCB Components ............................................................................................................... 5
2.4 System Architecture............................................................................................................5
2.5 Features.............................................................................................................................. 6
2.6 Development Board Specification ......................................................................................7
3Development Board Circuit ..........................................................................9
3.1 FPGA Module .....................................................................................................................9
3.2 Download............................................................................................................................9
3.2.1 Overview..........................................................................................................................9
3.2.2 USB Download Circuit ...................................................................................................10
3.2.3 Download Flow ..............................................................................................................10
3.2.4 Pinout.............................................................................................................................10
3.3 Power Supply.................................................................................................................... 11
3.3.1 Overview........................................................................................................................ 11
3.3.2 Power System Distribution ............................................................................................ 11
3.3.3 FPGA Power Pinout.......................................................................................................12
3.4 Clock, Reset .....................................................................................................................12

Contents
DBUG405-1.0E
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3.4.1 Overview........................................................................................................................12
3.4.2 Clock, Reset ..................................................................................................................13
3.4.3 Pinout.............................................................................................................................13
3.5 LED ...................................................................................................................................13
3.5.1 Overview........................................................................................................................13
3.5.2 LED Circuit.....................................................................................................................13
3.5.3 Pinout.............................................................................................................................14
3.6 Switches ...........................................................................................................................14
3.6.1 Overview........................................................................................................................14
3.6.2 Switch Circuit .................................................................................................................14
3.6.3 Pinout.............................................................................................................................14
3.7 Key.................................................................................................................................... 15
3.7.1 Overview........................................................................................................................15
3.7.2 Key Circuit .....................................................................................................................15
3.7.3 Pinout.............................................................................................................................15
3.8 GPIO .................................................................................................................................15
3.8.1 Overview........................................................................................................................15
3.8.2 GPIO Circuit...................................................................................................................16
3.8.3 Pinout.............................................................................................................................17
3.9 LVDS.................................................................................................................................19
3.9.1 Overview........................................................................................................................19
3.9.2 LVDS Circuit .................................................................................................................. 19
3.9.3 Pinout.............................................................................................................................20
3.10 Ethernet ..........................................................................................................................21
3.10.1 Overview...................................................................................................................... 21
3.10.2 Ethernet Circuit ............................................................................................................ 21
3.10.3 Pinout...........................................................................................................................22
4Considerations ............................................................................................24
5Gowin Software ...........................................................................................25

List of Figures
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List of Figures
Figure 2-1 DK_START_GW2AR-LV18EQ144PC8I7_V1.1 Development Board...............................3
Figure 2-2 A Development Board Kit ................................................................................................. 4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Architecture..........................................................................................................5
Figure 3-1 Connection Diagram for FPGA USB Downloading .......................................................... 10
Figure 3-2 Power System Distribution ............................................................................................... 11
Figure 3-3 Clock, Reset .....................................................................................................................13
Figure 3-4 LED Circuit .......................................................................................................................13
Figure 3-5 Switch Circuit.................................................................................................................... 14
Figure 3-6 Key Circuit ........................................................................................................................15
Figure 3-7 GPIO Circuit .....................................................................................................................16
Figure 3-8 LVDS Circuit ..................................................................................................................... 19
Figure 3-9 Ethernet Download Connection........................................................................................21

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminologies .......................................................................................2
Table 2-1 Development Board Specification...................................................................................... 7
Table 3-1 FPGA Download and Pinout .............................................................................................. 10
Table 3-2 FPGA Power Pinout ...........................................................................................................12
Table 3-3 FPGA Clock and Reset Pinout........................................................................................... 13
Table 3-4 LED Pinout ......................................................................................................................... 14
Table 3-5 Clock Circuit Pinout............................................................................................................ 14
Table 3-6 Key Pinout.......................................................................................................................... 15
Table 3-7 J5 GPIO Pinout .................................................................................................................. 17
Table 3-8 J14 GPIO Pinout ................................................................................................................ 17
Table 3-9 J2 GPIO Pinout .................................................................................................................. 18
Table 3-10 J15 GPIO Pinout .............................................................................................................. 18
Table 3-11 J3 FPGA Pinout ................................................................................................................ 20
Table 3-12 J4 FPGA Pinout................................................................................................................20
Table 3-13 Ethernet1 Pinout ..............................................................................................................22
Table 3-14 Ethernet2 Pinout ..............................................................................................................22

1 About This Guide
1.1 Purpose
DBUG405-1.0E
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1About This Guide
1.1 Purpose
The DK_START_GW2AR-LV18EQ144PC8I7_V1.1 user manual
consists of the following four parts:
A brief introduction to the features and hardware resources of the
development board;
An introduction to the hardware circuits functions, circuit, and pinout;
Considerations for the use of the development board;
Introduction to the use of the software.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS226, GW2AR series of FPGA Products Data Sheet
UG229, GW2AR series of FPGA Products Package and Pinout
UG113, GW2AR-18 Pinout
UG290, Gowin FPGA Products Programming and Configuration User
Guide
SUG100, Gowin Software User Guide
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown
in Table 1-1 below.

1 About This Guide
1.4 Support and Feedback
DBUG405-1.0E
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Table 1-1 Abbreviations and Terminologies
Abbreviations and Terminology
Full Name
FPGA
Field Programmable Gate Array
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
CFU
Configurable Function Unit
CLS
Configurable Logic Section
CRU
Configurable Routing Unit
LUT4
4-input Look-up Table
LUT5
5-input Look-up Table
LUT6
6-input Look-up Table
LUT7
7-input Look-up Table
LUT8
8-input Look-up Table
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input/Output Block
SSRAM
Shadow Static Random Access Memory
BSRAM
Block Static Random Access Memory
GPIO
Gowin Programmable I/O
PLL
Phase-locked Loop
DLL
Delay-locked Loop
EQ144
EQFP144
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Description
2.1 Overview
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2Development Board Description
2.1 Overview
Figure 2-1 DK_START_GW2AR-LV18EQ144PC8I7_V1.1 Development Board
DK_START_GW2AR-LV18EQ144PC8I7_V1.1 development board
adopts the GW2AR-18 device. 64Mbit PSRAM is embedded in this device.
The GW2AR series of FPGA products are the first generation products of
the Arora® family. They offer one form of SIP chip. The main difference
between the GW2A series and the GW2AR series is that the GW2AR
series integrates abundant memories. The GW2AR series also provides
high-performance DSP resources, a high-speed LVDS interface, and
abundant BSRAM resources. These embedded resources in combination
with a streamlined FPGA architecture with 55nm process make the
GW2AR series of FPGA products suitable for high-speed and low-cost
applications.
The development board offers abundant external interfaces, including
LVDS interfaces, GPIO interfaces, slide switches, key switches, LED, reset,
clock resources, etc.