GOWIN GW1NS Series User manual

GW1NS series of FPGA Products
Package & Pinout User Guide
UG823-1.8E, 10/18/2022

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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
09/10/2018
1.0E
Initial version published (Preliminary).
11/22/2018
1.1E
Pins distribution view for different packages added.
01/10/2019
1.2E
Quantity of GW1NS-2/GW1NS-2C Pins updated;
Introduction to the I/O BANK updated.
04/03/2019
1.3E
CS36 package outline updated.
10/12/2019
1.4E
GW1NS-4 / GW1NS-4C added.
11/12/2019
1.5E
CS49 package info. added and CS49 POD added.
03/30/2020
1.6E
GW1NS-2/GW1NS-2C CS36U package info. added.
04/16/2020
1.6.1E
GW1NS-2C CS36U package info. removed;
The pins distribution view and pin number of
GW1NS-4/GW1NS-4C QN48 updated.
07/28/2020
1.7E
GW1NS-4/4C MG64 package info. Added.
11/25/2020
1.7.1E
CS49 package outline updated.
06/30/2021
1.7.2E
Section 2.4.1 and 3.1 updated.
10/18/2022
1.8E
The unit in the package outline unified to millimeter.
GW1NS-2 and GW1NS-2C removed.
Pin definitions updated.

Contents
UG823-1.8E
i
Contents
Contents ...............................................................................................................i
List of Figures.....................................................................................................ii
List of Tables......................................................................................................iii
1 About This Guide .............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................1
1.4 Support and Feedback ....................................................................................................... 1
2 Overview ...........................................................................................................2
2.1 PB-Free Package ...............................................................................................................2
2.2 Package and Max. User I/O Information ............................................................................ 2
2.3 Power Pins..........................................................................................................................3
2.4 Pin Quantity ........................................................................................................................3
2.4.1 Quantity of GW1NS-4/GW1NS-4C Pins.......................................................................... 3
2.5 Pin Definitions.....................................................................................................................4
2.6 Introduction to the I/O BANK ..............................................................................................6
3 View of Pin Distribution...................................................................................8
3.1 View of GW1NS-4/GW1NS-4C Pins Distribution ...............................................................8
3.1.1 View of CS49 Pins Distribution........................................................................................8
3.1.2 View of QN48 Pins Distribution .......................................................................................9
3.1.3 View of MG64 Pins Distribution .....................................................................................10
4 Package Diagrams ......................................................................................... 11
4.1 CS49 Package Outline (2.9mm x 2.9mm)........................................................................ 11
4.2 QN48 Package Outline (6mm x 6mm)..............................................................................12
4.3 MG64 Package Outline (4.2mm x 4.2mm) .......................................................................13

List of Figures
UG823-1.8E
ii
List of Figures
Figure 2-1 GW1NS I/O Bank Distribution .......................................................................................... 6
Figure 3-1 View of GW1NS-4/GW1NS-4C CS49 Pins Distribution (Top View) .................................8
Figure 3-2 View of GW1NS-4/GW1NS-4C QN48 Pins Distribution (Top View).................................9
Figure 3-3 View of GW1NS-4/GW1NS-4C MG64 Pins Distribution (Top View) ................................ 10
Figure 4-1 Package Outline CS49 ..................................................................................................... 11
Figure 4-2 Package Outline QN48 (GW1NS-4 / GW1NS-4C)........................................................... 12
Figure 4-3 MG64 Package Outline ....................................................................................................13

List of Tables
UG823-1.8E
iii
List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................1
Table 2-1 Package and Max. User I/O Information............................................................................2
Table 2-2 GW1NS Power Pins........................................................................................................... 3
Table 2-3 Quantity of GW1NS-4/GW1NS-4C Pins ............................................................................ 3
Table 2-4 Definition of the Pins in the GW1NS series of FPGA Products .........................................4
Table 3-1 Other pins in GW1NS-4/GW1NS-4C CS49 ....................................................................... 8
Table 3-2 Other pins in GW1NS-4/GW1NS-4C QN48.......................................................................9
Table 3-3 Other pins in GW1NS-4/GW1NS-4C MG64 ...................................................................... 10

1 About This Guide
1.1 Purpose
UG823-1.8E
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NS series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guides are available on GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS821, GW1NS series of FPGA Products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration User
Guide
3. UG823, GW1NS series of FPGA Products Package and Pinout
4. UG824, GW1NS-4&4C Pinout
1.3 Abbreviations and Terminology
The abbreviations and terminologies used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Meaning
CS49
WLCSP49
FPGA
Field Programmable Gate Array
MG64
MBGA64
QN48
QFN48
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG823-1.8E
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2Overview
The GW1NS series of FPGA products are the first-generation products
in the LittleBee family and include SoC FPtGA devices and non-SoC FPGA
devices. SoC FPFA is embedded with an ARM Cortex-M3 hard core
processor, while no ARM Cortex-M3 hard core processor is included in the
non-SoC FPGA devices. When the ARM Cortex-M3 hard-core processor is
employed as the core, the needs of the Min. memory can be met. FPGA
logic resources and other embedded resources can flexibly facilitate the
peripheral control functions, which provide excellent calculation functions
and exceptional system response interrupts. They also offer high
performance, low power consumption, a small number of pins, flexible
usage, instant start-up, affordability, nonvolatile, high security, and
abundant package types, among other benefits. The GW1NS series of
SoC FPFA products achieve seamless connection between programmable
logic devices and embedded processors. They are compatible with multiple
peripheral device standards and can, therefore, reduce costs of operation
and be widely deployed in industrial control, communication, Internet of
Things, servo drive, consumption fields, etc.
2.1 PB-Free Package
The GW1NS series of FPGA products are PB free in line with the EU
ROHS environmental directives. The substances used in the GW1NS
series of FPGA products are in full compliance with the IPC-1752
standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package and Max. User I/O Information
Package
Pitch(mm)
Size(mm)
GW1NS-4/GW1NS-4C
QN48
0.4
6 x 6
38(4)
CS49
0.4
2.9 x 2.9
42(8)
MG64
0.5
4.2 x 4.2
55(8)
Note!
In this manual, abbreviations are employed to refer to the package types. See 1.3
Abbreviations and Terminology.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in

2 Overview
2.3 Power Pins
UG823-1.8E
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this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO,
and TMS) can be used as GPIO simultaneously, and the Max. user I/O plus one.
2.3 Power Pins
Table 2-2 GW1NS Power Pins
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
VCCPLL
VCCP
–
–
2.4 Pin Quantity
2.4.1 Quantity of GW1NS-4/GW1NS-4C Pins
Table 2-3 Quantity of GW1NS-4/GW1NS-4C Pins
Pin Type
GW1NS-4/GW1NS-4C
CS49
QN48
MG64
I/O Single end/Differential
pair /LVDS[1]
BANK0
8/3/0
8/3/0
10/3/0
BANK1
18/9/0
10/5/0
28/14/0
BANK2
16/8/8
9/4/4
18/9/8
BANK3
0/0/0
11/5/0
0/0/0
Max. User I/O [2]
42
38
55
Differential Pair
20
17
26
True LVDS output
8
4
8
VCC
1
2
1
VCCX
1
1
1
VCCO0
0
1
1
VCCO1
1
1
1
VCCO2
1
1
1
VCCO3
0
2
1
VCCO0/VCCO3[3]
1
0
0
VSS
2
1
2
MODE0
0
0
0
MODE1
0
1
0
MODE2
0
0
0
JTAGSEL_N
0
1
1
NC
0
0
0
Note!
[1] Single end/ Differential I/O quantity include CLK pins, and download pins;
[2] The max. user I/O excludes dedicated MODE pins. The JTAGSEL_N and JTAG
pins cannot be used as I/O simultaneously. The data in this table is when the loaded
four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O.
[3] Pin multiplexing.

2 Overview
2.5 Pin Definitions
UG823-1.8E
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2.5 Pin Definitions
The location of the pins in the GW1NS series of FPGA products varies
according to the different packages.
Table 2-4 provides a detailed overview of user I/O, multi-function pins,
dedicated pins, and other pins.
Table 2-4 Definition of the Pins in the GW1NS series of FPGA Products
Pin Name
I/O
Description
User I/O Pins
IO[End][Row/Column
Number][A/B]
I/O
[End] indicates the pin location, including L(left) R(right)
B(bottom), and T(top).
[Row/Column Number] indicates the pin Row/Column
number. If [End] is T(top) or B(bottom), the pin indicates
the column number of the corresponding CFU. If [End]
is L(left) or R(right), the pin indicates the Row number of
the corresponding CFU.
[A/B] indicates differential signal pair information.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the other functions in
addition to being general purpose user I/O. When these
functions are not in use, these pins can be used as user
I/O.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when low pulse
D0
I/O
Data port D0 in CPU mode
D1
I/O
Data port D1 in CPU mode
D2
I/O
Data port D2 in CPU mode
D3
I/O
Data port D3 in CPU mode
D4
I/O
Data port D4 in CPU mode
D5
I/O
Data port D5 in CPU mode
D6
I/O
Data port D6 in CPU mode
D7
I/O
Data port D7 in CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU mode.0:
Write;1: Read.
DOUT
O
Data output in SERIAL mode
DIN
I, internal weak
pull-up
Data input in SERIAL mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK
I
Serial clock input in JTAG mode
TDO
O
Serial data output in JTAG mode
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Reconfigure JTAG download function signal
RECONFIG_N
I, internal weak
Global reset GowinCONFIG logic signal, active low.

2 Overview
2.5 Pin Definitions
UG823-1.8E
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Pin Name
I/O
Description
pull-up
FASTRD_N
I
Access SPI FLASH to select signal. Low, Fast Read
mode; High, Read mode.
READY[1]
I/O
High, the device can be programmed and configured
currently;
Low, the device cannot be programmed and configured
currently.
DONE[1]
O
High, the programming configuration has been
completed successfully;
Low, the programming configuration has not been
completed or failed.
I
When the DONE signal is low, delay the chip to activate.
Activate the chip until the DONE signal is high.
MI
O
MI in MSPI mode
MO
I
MO in MSPI mode
MCS_N
O
Enable signal MCS_N in MSPI mode, active-low.
MCLK
O
Clock output MCLK in MSPI mode, with default
frequency of 2.5MHz.
SCLK
I
Clock input in SSPI, SERIAL, and CPU modes.
SO
O
SO in SSPI mode
SI
I/O
SI in SSPI mode
SSPI_CS_N
I/O
Enable signal SSPI_CS_N in SSPI mode, active-low,
and internal weak pull-up
CLKHOLD_N
I, internal weak
pull-up
High, the operation is efficient in SSPI mode or CPU
mode;
Low, the operation is inefficient in SSPI mode or CPU
mode.
GCLKT_[x]
I
Global clock input pin, T(True), [x]: global clock No.
GCLKC_[x]
I
Differential input pin of GCLKT_[x], C(Comp), [x]: global
clock No.[2]
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True).
LPLL_C_fb/RPLL_C_fb
I
L/R PLL feedback input pin, C(Comp).
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True).
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp).
CH[7:0]
I
Eight-channel analog input
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
Other Pins
NC
NA
Reserved.
VSS
NA
Ground pins

2 Overview
2.6 Introduction to the I/O BANK
UG823-1.8E
6(13)
Pin Name
I/O
Description
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of I/O BANK#.
VCCX
NA
Power supply pins of auxiliary voltage.
VCCP
NA
FLASH Power supply pin (1.8V)
VCCPLL
NA
Power supply pins of PLL
Note！
[1] The default state of READY/DONE is open-drain output, internal weak pull-up.
DONE outputs 0 during configuration.
[2] When the input is single-ended, the GLKC_[x] pin is not a global clock pin.
2.6 Introduction to the I/O BANK
There are four I/O Banks in the GW1NS series of FPGA products, as
shown in Figure 2-1.
Figure 2-1 GW1NS I/O Bank Distribution
GW1NS
I/O BANK0
I/O BANK2
I/O BANK1
I/O BANK3
This manual provides an overview of the distribution view of the pins in
the GW1NS series of FPGA products. The four I/O Banks of the GW1NS
series of FPGA products are marked with four different colors.
User I/O, power, and ground are also marked with different symbols
and colors. The various symbols and colors used for the various pins are
defined as follows:
" " denotes I/Os in BANK0.
" " denotes I/Os in BANK1.
" " denotes I/Os in BANK2.
" " denotes I/Os in BANK3.
" " denotes VCC, VCCX, and VCCO.

2 Overview
2.6 Introduction to the I/O BANK
UG823-1.8E
7(13)
" " denotes VCC. The filling color does not change.
" " denotes VSS. The filling color does not change.
" " denotes NC.

3 View of Pin Distribution
3.1 View of GW1NS-4/GW1NS-4C Pins Distribution
UG823-1.8E
8(13)
3View of Pin Distribution
3.1 View of GW1NS-4/GW1NS-4C Pins Distribution
3.1.1 View of CS49 Pins Distribution
Figure 3-1 View of GW1NS-4/GW1NS-4C CS49 Pins Distribution (Top View)
Table 3-1 Other pins in GW1NS-4/GW1NS-4C CS49
VCC
D5
VCCO1
C3
VCCO2
E3
VCCX
D3
VCCO0/VCCO3
C5
VSS
D4,C4

3 View of Pin Distribution
3.1 View of GW1NS-4/GW1NS-4C Pins Distribution
UG823-1.8E
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3.1.2 View of QN48 Pins Distribution
Figure 3-2 View of GW1NS-4/GW1NS-4C QN48 Pins Distribution (Top View)
Table 3-2 Other pins in GW1NS-4/GW1NS-4C QN48
VCC
11,37
VCCO0
5
VCCO1
38
VCCO2
36
VCCO3
12,24
VCCX
25
VSS
26

3 View of Pin Distribution
3.1 View of GW1NS-4/GW1NS-4C Pins Distribution
UG823-1.8E
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3.1.3 View of MG64 Pins Distribution
Figure 3-3 View of GW1NS-4/GW1NS-4C MG64 Pins Distribution (Top View)
Table 3-3 Other pins in GW1NS-4/GW1NS-4C MG64
VCC
D5
VCCO0
C3
VCCO1
C6
VCCO2
F6
VCCO3
F3
VCCX
E4
VSS
D4,E5

4 Package Diagrams
4.1 CS49 Package Outline (2.9mm x 2.9mm)
UG823-1.8E
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4Package Diagrams
4.1 CS49 Package Outline (2.9mm x 2.9mm)
Figure 4-1 Package Outline CS49
SYMBOL ITEM DATA(mm)
D0*E0 PACKAGE SIZE X*Y 2.9766*2.9618±0.025
BALLDIAMETER 0.26±0.03
a/b BALL PITCH X/Y 0.4/0.4
N BALLCOUNT 49
H PACKAGE HEIGHT 0.54±0.05
H1 BALL HEIGHT 0.2±0.025
H2 SI THICKNESS+PI 0.315±0.015
H3 BACK COATING 0.025±0.01
0.33099925
0.23082475
0.3229755
0.2536485
G
F
E
D
C
B
A
7 6 5 4 3 2 1
G W 1 N S - L V 4
C S 4 9 C 6 / I 5
Y
X
Y W W
X X X X X X X X
TOP VIEW
PIN 1(A1 )
D0
A1
a
b
SIDEVIEW
H1 H2 H3
H
7654321
G
F
E
D
C
B
A
E0
BOTTOM VIEW

4 Package Diagrams
4.2 QN48 Package Outline (6mm x 6mm)
UG823-1.8E
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4.2 QN48 Package Outline (6mm x 6mm)
Figure 4-2 Package Outline QN48 (GW1NS-4 / GW1NS-4C)
PAD ZONE
EXPOSED THERMAL
BOTTOM VIEW
4.20
4.20
4.10 4.30
4.10 4.30
4.40BSC
c
0.200.15 0.25
__ 0.05
0.02
0 .85
6.00 6.10
e0.40BSC
0.75 0.85
E
A
D
0.230.18 0.20
b
MAXNOMMIN
MILLIMETER
SYMBOL
5.90
6.10
6.00
5.90
L0.450.35 0.40
0.30 0.40
h0.35
4.40BSC
D2
Ne
Nd
E2
A1

4 Package Diagrams
4.3 MG64 Package Outline (4.2mm x 4.2mm)
UG823-1.8E
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4.3 MG64 Package Outline (4.2mm x 4.2mm)
Figure 4-3 MG64 Package Outline
A
1
2
34
B
C
D
5
6
78
E
F
G
H
A
123 4
B
C
D
567 8
E
F
G
H
A
1
2
B
C