GOWIN GW1N Series Owner's manual

Gowin FPGA Products
Programming and Configuraion Guide
UG290-1.04E, 8/8/2018

Copyright©2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
No part of this document may be reproduced or transmitted in any form or by any denotes,
electronic, mechanical, photocopying, recording or otherwise, without the prior written
consent of GOWINSEMI.
Disclaimer
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countries. All other words and logos identified as trademarks or service marks are the
property of their respective holders, as described at www.gowinsemi.com.cn. GOWINSEMI
assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
from usage of the materials or intellectual property except as outlined in the GOWINSEMI
Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
4/17/2017
1.00E
Initial version published.
5/31/2017
1.01E
Update configuration mode and value of different
supported device;
Update RECONFIG N notes during programming built-in
Flash.
10/13/2017
1.02E
Description of reusing pins updated.
3/16/2018
1.03E
Add GW1NS programming and configuration description.
8/8/2018
1.04E
Operation procedures for multiple configurations updated;
When MODE[0]=1, JTAG pins reuse description updated;
The programming features of B version devices updated;
Configuration notes and the timing for different
configuration modes added.

Contents
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Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.3 Related Documents............................................................................................................ 1
1.4 Abbreviations and Terminology...........................................................................................2
1.5 Support and Feedback ....................................................................................................... 2
2 Glossary...........................................................................................................3
3 Configuration Mode and Power-on Requirements .......................................5
3.1 GW1N(R/S) series of FPGA Products................................................................................5
3.1.1 Configuration Modes .......................................................................................................6
3.1.2 Power Supply Voltage ..................................................................................................... 6
3.2 GW2A(R) series of FPGA Products....................................................................................7
3.2.1 Configuration Modes ....................................................................................................... 7
3.2.2 Power Supply Voltage ..................................................................................................... 8
4 Configuration Pin.............................................................................................9
4.1 Configuration Pin List and Reuse Options ......................................................................... 9
4.1.1 Configuration Pin List and Reuse Options ...................................................................... 9
4.1.2 Pin Multiplexing..............................................................................................................10
4.2 Pin Function and Application ............................................................................................12
5 Configuration Mode.......................................................................................18
5.1 Configuration Notes..........................................................................................................19
5.2 JTAG Configuration ..........................................................................................................23
5.3 AUTO BOOT Configuration (supported by GW1N(R/S) only)..........................................26
5.4 SSPI..................................................................................................................................27
5.5 MSPI.................................................................................................................................29
5.6 AUTO BOOT Configuration (supported by GW1N(R/S) only)..........................................36
5.7 CPU Mode........................................................................................................................38
5.8 SERIAL.............................................................................................................................39
6 Bitstream File Configuration ........................................................................41
6.1 Configuration Options.......................................................................................................42

Contents
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6.2 Data Encryption (supported by GW2A(R) series only)..................................................... 42
6.3 Configuration File Size......................................................................................................45
7 Safety Precautions ........................................................................................46
8 Boundary Scan ..............................................................................................48
9 SPI Flash Selection........................................................................................50

List of Figures
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List of Figures
Figure 4-1 Configuring Pin Reuse......................................................................................................12
Figure 4-2 MCLK Frequency Setting .................................................................................................17
Figure 5-1 Recommended Pin Connection........................................................................................ 20
Figure 5-2 Power Recycle Timing......................................................................................................21
Figure 5-3 Trigger Timing................................................................................................................... 22
Figure 5-4 Connection Diagram for the JTAG Configuration Mode...................................................24
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode .....................................25
Figure5-6 JTAG Configuration timing................................................................................................. 25
Figure 5-7 SSPI Configuration Mode Connection Diagram...............................................................27
Figure 5-8 SSPI Programming via External Flash Connection Diagram........................................... 28
Figure 5-9 JTAG Configuration Timing...............................................................................................28
Figure 5-10 MSPI Configuration Mode Connection Diagram ............................................................31
Figure 5-11 Connection Diagram of JTAG Programming External Flash..........................................31
Figure 5-12 Input the Start Address for the Next BitStream .............................................................. 33
Figure 5-13 Set the ProgrammingAddress for the External Flash....................................................34
Figure 5-14 Connection Diagram for Configuring Multi-Chip FPGA via Single Flash .......................35
Figure5-15 MSPI Download Timing...................................................................................................35
Figure 5-16 Dual Boot Flow Chart .....................................................................................................37
Figure 5-17 Connection Diagram for the CPU Mode......................................................................... 38
Figure 5-18 Connection Diagram for the SERIAL Mode....................................................................39
Figure 6-1 Configuration Options....................................................................................................... 42
Figure 6-2 Encryption Key Setting Method........................................................................................ 43
Figure 6-3 Setting the Decryption Key............................................................................................... 44
Figure 6-4Bitstream Format Conversion Tool....................................................................................45
Figure 8-1 Boundary Scan Operation Schematic Diagram ............................................................... 49

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology..........................................................................................2
Table 2-1 Glossary.............................................................................................................................3
Table 3-1 Configuration Modes..........................................................................................................6
Table3-2 Recommended Power Supply Voltage ...............................................................................7
Table 3-3 Configuration Modes..........................................................................................................7
Table3-4 Recommended Power Supply Voltage ...............................................................................8
Table 4-1 Configuration Pin List.........................................................................................................10
Table 4-2 Pin Reuse Options ............................................................................................................. 11
Table 4-3 Pin Function ....................................................................................................................... 12
Table 5-1Corresponding MODE Value............................................................................................... 21
Table 5-2 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 22
Table 5-3 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 22
Table 5-4 Pin Description in JTAG Configuration Mode..................................................................... 23
Table 5-5 JTAG Configuration Timing Parameters ............................................................................25
Table 5-6 SSPI Mode Pins.................................................................................................................27
Table 5-7 SSPI Configuration Timing Parameters............................................................................. 29
Table 5-8 Pin Description in JTAG Configuration Mode..................................................................... 30
Table 5-9 MSPI Configuration Timing Parameters.............................................................................35
Table 5-10 CPU Mode Pins................................................................................................................38
Table 5-11 Pin Definition in SERIAL Configuration Mode.................................................................. 39
Table 6-1 Gowin FPGA Products Configuration File Size.................................................................. 45
Table 9-1 SPI Flash Operation Instruction.........................................................................................50

1About This Guide
1.1Purpose
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of GW1N (R), GW1NS, and GW2A (R)
series of FPGA products. It helps users to use Gowin FPGAproducts to
their full potential.
1.2 Supported Products
The information in the guide applies to all Gowin FPGA products.
1.3 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
GW1N series of Products Data Sheet
GW2A series of FPGA Products Data Sheet
GW1NR series of FPGAProducts Data Sheet
GW2AR series of FPGA Products Data Sheet
GW1NS series of FPGA Products Data Sheet

1About This Guide
1.4Abbreviations and Terminology
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1.4 Abbreviations and Terminology
The abbreviations and terminology used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and
Terminology
Full Name
Meaning
LUT
Look-up Table
Look-up Table
FPGA
Field Programmable GateArray
Field Programmable Gate
Array
JTAG
Joint Test Action Group
Joint Test Action Group
GPIO
General Purpose Input Output
General Purpose Input
Output
SPI
Serial Peripheral Interface
Serial Peripheral Interface
SRAM
Static Random Access Memory
Static Random Access
Memory
MSPI
Master Serial Peripheral Interface
Master Serial Peripheral
Interface
IEEE
Institute of Electrical and Electronics
Engineers
Institute of Electrical and
Electronics Engineers
ID
Identification
Identification
CRC
Cyclic Redundancy Check
Cyclic Redundancy Check
1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]
+Tel: [phone]

2Glossary
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2Glossary
This chapter presents an overview of the terms that are commonly
used when programming and configuring Gowin FPGAproducts.
Familiarizing yourself with the glossary items listed below will help you to
make the most out of the Gowin FPGA products.
Table 2-1 Glossary
Glossary
Meaning
Program
Write bitstream data generated by Gowin software
to FPGA on-chip Flash or off-chip SPI Flash that is
connected to the FPGA.
Configure
Load bitstream data generated by Gowin software
into the FPGA SRAM storage area via external
interfaces or on-chip Flash.
GowinCONFIG
In addition to the generic JTAG configuration
mode, Gowin FPGA products support additional
configurations, includingAUTO BOOT
configuration, DUAL BOOT configuration, MSPI
configuration, SSPI configuration, SERIAL
configuration, and CPU configuration. The
GowinCONFIG configuration mode that is
supported for each device depends on the device
model and packages.
AUTO BOOT
FPGA loads bitstream data into the SRAM from an
on-chip Flash. Only non-volatile devices support
this mode.
DUAL BOOT
FPGA loads bitstream data into the SRAM from
on-chip Flash or off-chip Flash. Two bitstream files
are stored in on-chip Flash and off-chip Flash.
Switch to standby Flash if the preferred Flash fails
to configure. Only non-volatile devices support this
mode.
MSPI
As a master, FPGA configures bitstream by
automatically reading from the off chip Flash via
the SPI interface.