GOWIN GW1N Series Owner's manual

Gowin FPGA Products
Programming and Configuraion Guide
UG290-1.04E, 8/8/2018

Copyright©2018 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
No part of this document may be reproduced or transmitted in any form or by any denotes,
electronic, mechanical, photocopying, recording or otherwise, without the prior written
consent of GOWINSEMI.
Disclaimer
GOWINSEMI®, LittleBee®, AroraTM, and the GOWINSEMI logos are trademarks of
GOWINSEMI and are registered in China, the U.S. Patent and Trademark Office and other
countries. All other words and logos identified as trademarks or service marks are the
property of their respective holders, as described at www.gowinsemi.com.cn. GOWINSEMI
assumes no liability and provides no warranty (either expressed or implied) and is not
responsible for any damage incurred to your hardware, software, data, or property resulting
from usage of the materials or intellectual property except as outlined in the GOWINSEMI
Terms and Conditions of Sale. All information in this document should be treated as
preliminary. GOWINSEMI may make changes to this document at any time without prior
notice. Anyone relying on this documentation should contact GOWINSEMI for the current
documentation and errata.

Revision History
Date
Version
Description
4/17/2017
1.00E
Initial version published.
5/31/2017
1.01E
Update configuration mode and value of different
supported device;
Update RECONFIG N notes during programming built-in
Flash.
10/13/2017
1.02E
Description of reusing pins updated.
3/16/2018
1.03E
Add GW1NS programming and configuration description.
8/8/2018
1.04E
Operation procedures for multiple configurations updated;
When MODE[0]=1, JTAG pins reuse description updated;
The programming features of B version devices updated;
Configuration notes and the timing for different
configuration modes added.

Contents
UG290-1.04E
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Contents
Contents...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Supported Products............................................................................................................1
1.3 Related Documents............................................................................................................ 1
1.4 Abbreviations and Terminology...........................................................................................2
1.5 Support and Feedback ....................................................................................................... 2
2 Glossary...........................................................................................................3
3 Configuration Mode and Power-on Requirements .......................................5
3.1 GW1N(R/S) series of FPGA Products................................................................................5
3.1.1 Configuration Modes .......................................................................................................6
3.1.2 Power Supply Voltage ..................................................................................................... 6
3.2 GW2A(R) series of FPGA Products....................................................................................7
3.2.1 Configuration Modes ....................................................................................................... 7
3.2.2 Power Supply Voltage ..................................................................................................... 8
4 Configuration Pin.............................................................................................9
4.1 Configuration Pin List and Reuse Options ......................................................................... 9
4.1.1 Configuration Pin List and Reuse Options ...................................................................... 9
4.1.2 Pin Multiplexing..............................................................................................................10
4.2 Pin Function and Application ............................................................................................12
5 Configuration Mode.......................................................................................18
5.1 Configuration Notes..........................................................................................................19
5.2 JTAG Configuration ..........................................................................................................23
5.3 AUTO BOOT Configuration (supported by GW1N(R/S) only)..........................................26
5.4 SSPI..................................................................................................................................27
5.5 MSPI.................................................................................................................................29
5.6 AUTO BOOT Configuration (supported by GW1N(R/S) only)..........................................36
5.7 CPU Mode........................................................................................................................38
5.8 SERIAL.............................................................................................................................39
6 Bitstream File Configuration ........................................................................41
6.1 Configuration Options.......................................................................................................42

Contents
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6.2 Data Encryption (supported by GW2A(R) series only)..................................................... 42
6.3 Configuration File Size......................................................................................................45
7 Safety Precautions ........................................................................................46
8 Boundary Scan ..............................................................................................48
9 SPI Flash Selection........................................................................................50

List of Figures
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List of Figures
Figure 4-1 Configuring Pin Reuse......................................................................................................12
Figure 4-2 MCLK Frequency Setting .................................................................................................17
Figure 5-1 Recommended Pin Connection........................................................................................ 20
Figure 5-2 Power Recycle Timing......................................................................................................21
Figure 5-3 Trigger Timing................................................................................................................... 22
Figure 5-4 Connection Diagram for the JTAG Configuration Mode...................................................24
Figure 5-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode .....................................25
Figure5-6 JTAG Configuration timing................................................................................................. 25
Figure 5-7 SSPI Configuration Mode Connection Diagram...............................................................27
Figure 5-8 SSPI Programming via External Flash Connection Diagram........................................... 28
Figure 5-9 JTAG Configuration Timing...............................................................................................28
Figure 5-10 MSPI Configuration Mode Connection Diagram ............................................................31
Figure 5-11 Connection Diagram of JTAG Programming External Flash..........................................31
Figure 5-12 Input the Start Address for the Next BitStream .............................................................. 33
Figure 5-13 Set the ProgrammingAddress for the External Flash....................................................34
Figure 5-14 Connection Diagram for Configuring Multi-Chip FPGA via Single Flash .......................35
Figure5-15 MSPI Download Timing...................................................................................................35
Figure 5-16 Dual Boot Flow Chart .....................................................................................................37
Figure 5-17 Connection Diagram for the CPU Mode......................................................................... 38
Figure 5-18 Connection Diagram for the SERIAL Mode....................................................................39
Figure 6-1 Configuration Options....................................................................................................... 42
Figure 6-2 Encryption Key Setting Method........................................................................................ 43
Figure 6-3 Setting the Decryption Key............................................................................................... 44
Figure 6-4Bitstream Format Conversion Tool....................................................................................45
Figure 8-1 Boundary Scan Operation Schematic Diagram ............................................................... 49

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology..........................................................................................2
Table 2-1 Glossary.............................................................................................................................3
Table 3-1 Configuration Modes..........................................................................................................6
Table3-2 Recommended Power Supply Voltage ...............................................................................7
Table 3-3 Configuration Modes..........................................................................................................7
Table3-4 Recommended Power Supply Voltage ...............................................................................8
Table 4-1 Configuration Pin List.........................................................................................................10
Table 4-2 Pin Reuse Options ............................................................................................................. 11
Table 4-3 Pin Function ....................................................................................................................... 12
Table 5-1Corresponding MODE Value............................................................................................... 21
Table 5-2 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 22
Table 5-3 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 22
Table 5-4 Pin Description in JTAG Configuration Mode..................................................................... 23
Table 5-5 JTAG Configuration Timing Parameters ............................................................................25
Table 5-6 SSPI Mode Pins.................................................................................................................27
Table 5-7 SSPI Configuration Timing Parameters............................................................................. 29
Table 5-8 Pin Description in JTAG Configuration Mode..................................................................... 30
Table 5-9 MSPI Configuration Timing Parameters.............................................................................35
Table 5-10 CPU Mode Pins................................................................................................................38
Table 5-11 Pin Definition in SERIAL Configuration Mode.................................................................. 39
Table 6-1 Gowin FPGA Products Configuration File Size.................................................................. 45
Table 9-1 SPI Flash Operation Instruction.........................................................................................50

1About This Guide
1.1Purpose
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of GW1N (R), GW1NS, and GW2A (R)
series of FPGA products. It helps users to use Gowin FPGAproducts to
their full potential.
1.2 Supported Products
The information in the guide applies to all Gowin FPGA products.
1.3 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
GW1N series of Products Data Sheet
GW2A series of FPGA Products Data Sheet
GW1NR series of FPGAProducts Data Sheet
GW2AR series of FPGA Products Data Sheet
GW1NS series of FPGA Products Data Sheet

1About This Guide
1.4Abbreviations and Terminology
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1.4 Abbreviations and Terminology
The abbreviations and terminology used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and
Terminology
Full Name
Meaning
LUT
Look-up Table
Look-up Table
FPGA
Field Programmable GateArray
Field Programmable Gate
Array
JTAG
Joint Test Action Group
Joint Test Action Group
GPIO
General Purpose Input Output
General Purpose Input
Output
SPI
Serial Peripheral Interface
Serial Peripheral Interface
SRAM
Static Random Access Memory
Static Random Access
Memory
MSPI
Master Serial Peripheral Interface
Master Serial Peripheral
Interface
IEEE
Institute of Electrical and Electronics
Engineers
Institute of Electrical and
Electronics Engineers
ID
Identification
Identification
CRC
Cyclic Redundancy Check
Cyclic Redundancy Check
1.5 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]
+Tel: [phone]

2Glossary
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2Glossary
This chapter presents an overview of the terms that are commonly
used when programming and configuring Gowin FPGAproducts.
Familiarizing yourself with the glossary items listed below will help you to
make the most out of the Gowin FPGA products.
Table 2-1 Glossary
Glossary
Meaning
Program
Write bitstream data generated by Gowin software
to FPGA on-chip Flash or off-chip SPI Flash that is
connected to the FPGA.
Configure
Load bitstream data generated by Gowin software
into the FPGA SRAM storage area via external
interfaces or on-chip Flash.
GowinCONFIG
In addition to the generic JTAG configuration
mode, Gowin FPGA products support additional
configurations, includingAUTO BOOT
configuration, DUAL BOOT configuration, MSPI
configuration, SSPI configuration, SERIAL
configuration, and CPU configuration. The
GowinCONFIG configuration mode that is
supported for each device depends on the device
model and packages.
AUTO BOOT
FPGA loads bitstream data into the SRAM from an
on-chip Flash. Only non-volatile devices support
this mode.
DUAL BOOT
FPGA loads bitstream data into the SRAM from
on-chip Flash or off-chip Flash. Two bitstream files
are stored in on-chip Flash and off-chip Flash.
Switch to standby Flash if the preferred Flash fails
to configure. Only non-volatile devices support this
mode.
MSPI
As a master, FPGA configures bitstream by
automatically reading from the off chip Flash via
the SPI interface.

2Glossary
1.5Support and Feedback
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Glossary
Meaning
SSPI
As a slave, FPGA is configured by the external
master writing bitstream via the SPI interface.
SERIAL
As a slave, FPGA is configured by the external
master writing bitstream via a serial interface.
CPU
As a slave, FPGA is configured by the external
master writing bitstream via a parallel interface
(8-bit).
MULTI BOOT
The derivative concept of MSPI refers to the fact
that FPGA reads bitstream data from different
addresses stored on external Flash. The loading
address of the bitstream data is written in previous
bitstream data and finishes configuration via
triggering RECONFIG_N to switch the data stream
file when the power is on. FPGA products that
support MSPI support this mode.
Remote Upgrade
An application scenario for users. After operating
FPGA, if an upgrade is required, write bitstream
onto on-chip or off-chip Flash through remote
operation. FPGA accesses the off-chip Flash by
triggering RECONFIG_N or powering up again to
complete the configuration.
Daisy Chain
FPGA devices are connected in serial ways, which
can be configured according to the sequence of
connections in order to transmit data between
adjacent devices.
User Mode
When this mode is selected, once the
configuration has been completed for the FPGA,
the user can control the functions as needed.
ID CODE
Identification for the the Gowin FPGA device.
Each series of devices has a different number.
USER CODE
Write to identify the FPGA device through the
Gowin programming software, which can be up to
32-bit.
Security Bit
A special design for protecting the security of the
Gowin FPGA product configuration data. After
writing the bitstream with security bit to the device,
data readback will not be performed. Gowin
software sets a security bit for the bitstream data
of all FPGA products by default.
Encryption
The GW2A (R) series of FPGA product support
this feature. After the encrypted bitstream is
written to FPGA, the device will match the
pre-stored key automatically, and then decrypt and
wake up the device after successful matching. The
device cannot work if matching fails.

3Configuration Mode and Power-on Requirements
3.1GW1N(R/S) series of FPGA Products
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3Configuration Mode and Power-on
Requirements
3.1 GW1N(R/S) series of FPGA Products
Besides JTAG, the GW1N(R/S) series of FPGA products also support
GOWINSEMI's own configuration mode: GowinCONFIG. GowinCONFIG
configuration modes that are available and supported for each device
depend on the device model and package. All the devices support JTAG
and AUTO BOOT. Up to six configuration modes can be employed.
The programming and configuration features of the GW1N(R/S) series
of FPGA products are as follows:
Instant start –millisecond
Flexible configuration modes
High security
High capacity flash memory
Note!
For details about configuration pins, pin multiplexing, and pin functions and application,
please refer to 4Configuration Pin.

3Configuration Mode and Power-on Requirements
3.1GW1N(R/S) series of FPGA Products
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3.1.1 Configuration Modes
Table 3-1 lists the configuration modes that are supported by the
GW1N(R/S) series of FPGA products.
Table 3-1 Configuration Modes
Configuration
MODE[2:0]1
Instructions
JTAG
XXX2
The GW1N(R) series of FPGA products
are configured by hardware processor via
the JTAG interface.
GowinCONFIG
AUTO
BOOT
000
FPGAis configured by reading data from
the built-in Flash
SSPI
001
The GW1N(R) series of FPGA products
are configured by hardware processor via
SPI interface.
MSPI
010
As master, the GW1N series of FPGA
products are configured by reading data
from the external Flash (or another
device) through the SPI interface3.
DUAL
BOOT4
100
Reads from built-in flash first and then
from the external flash if the built-in flash
configuration fails.
SERIAL5
101
The GW1N(R) series of FPGAproducts
are configured by hardware processor via
the DIN interface.
CPU5
111
The GW1N(R) series of FPGA products
are configured by hardware processor via
the DBUS interface.
Note!
[1] For some of the device packages, all the mode pins are not bonded out. The
unbound mode pins are grounded;
[2] The JTAG configuration mode is independent of the input value of the MODE pins;
[3] The SPI interfaces of the SSPI and MSPI modes are independent of each other;
[4] GW1N(R)-2 and GW1N(R)-4 do not currently support DUAL BOOT; GW1N(R)-6
and GW1N(R)-9 support DUAL BOOT with MODE value 100 and mode which start
first from external Flash. The value of the MODE pins is 110.
[5] The CPU configuration mode and SERIAL configuration mode share SCLK,
WE_N and CLKHOLD_N. The data bus pins for the CPU configuration mode share
pins with MSPI and SSPI configuration modes.
3.1.2 Power Supply Voltage
The GW1N(R/S) series of FPGA products contain one power-on reset
module. The recommended power supply voltage is as shown in Table3-2.
The device remains in a reset state until the power supply conditions
are met. When the conditions are met, the power-on reset circuit is
released, allowing the device to begin its initialization process.

3Configuration Mode and Power-on Requirements
3.2GW2A(R) series of FPGA Products
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Table3-2 Recommended Power Supply Voltage
Name
Description
Min.
Max.
VCC
LV: Core Power
1.14V
1.26V
UV: Core Power
1.71V
3.465V
VCCO
I/O Bank Power
1.14V
3.6V
VCCX
Auxiliary Power
2.3V
3.465V
3.2 GW2A(R) series of FPGA Products
Besides JTAG, the GW2A(R) series of FPGAproducts also support
GOWINSEMI's own configuration mode: GowinCONFIG. The
GowinCONFIG configuration modes that are available and supported for
each device depend on the device model and package. The GW2A(R)
series support bitstream encryption and security bit setting, which is safety
for user design. The GW2A(R) series of FPGA products support bitstream
decompression; users can compress bitstream to save storage memory.
Note!
For details about configuration pins, pin multiplexing, and pin functions and application,
please refer to 4Configuration Pin.
3.2.1 Configuration Modes
Table 3-1 lists the configuration modes that are supported by the
GW2A(R) series of FPGA products.
Table 3-3 Configuration Modes
Configuration
MODE[2:0]1
Instructions
JTAG
XXX2
The GW2A(R) series of FPGA products
are configured by the external Host via a
JTAG interface.
GowinCONFIG
MSPI
000
As master, the GW2A/GW2AR series
FPGA products are configured by reading
data from the external Flash (or another
device) through the SPI interface3.
SSPI
001
The GW2A(R) series of FPGA products
are configured from an external Host via a
SPI interface.
SERIAL4
101
The GW2A(R) series of FPGA products
are configured by the external Host via a
DIN interface.
CPU4
111
The GW2A(R) series of FPGA products
are configured by the external Host via a
DBUS interface.
Note!
[1] For some of the device packages, all the mode pins are not bonded out. The
unbound mode pins are grounded;
[2] The JTAG configuration mode is independent of the input value of the MODE pins;
[3] The SPI interfaces of the SSPI and MSPI modes are independent of each other;
[4] The CPU configuration mode and SERIAL configuration mode share SCLK,
WE_N and CLKHOLD_N. The data bus pins for the CPU configuration mode share
pins with MSPI and SSPI configuration modes.

3Configuration Mode and Power-on Requirements
3.2GW2A(R) series of FPGA Products
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3.2.2 Power Supply Voltage
The GW2A(R) series of FPGA products contain one power-on reset
module. The recommended power supply voltage is as shown in Table3-2.
The device remains in a reset state until the power supply conditions
are met. When the conditions are met, the power-on reset circuit is
released, allowing the device to begin its initialization process.
Table3-4 Recommended Power Supply Voltage
Name
Description
Min.
Max.
VCC
Core voltage
0.95V
1.05V
VCCO
I/O Bank Power
1.14V
3.465V
VCCX
Auxiliary Power
3.135V
3.465V

4Configuration Pin
4.1Configuration Pin List and Reuse Options
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4Configuration Pin
Gowin FPGA products have various configuration modes that can be
selected to satisfy the diverse needs of different users across a range of
peripherals. Some of the options that are available include general JTAG
configuration, master configuration, slave configuration, serial configuration,
and parallel configuration. The pins related to the respective programming
configuration can both complete configuration function and be set to
ordinary I/O for users as required. Users also can configure pins according
to the functions to meet their unique needs.
4.1 Configuration Pin List and Reuse Options
4.1.1 Configuration Pin List and Reuse Options
Table 4-1 contains a list of all the pins of that are required to configure
Gowin FPGA products together with the details of the shared pins in each
configuration mode and chip packaging process.

4Configuration Pin
4.1Configuration Pin List and Reuse Options
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Table 4-1 Configuration Pin List
Pin Name
I/O
JTAG
GowinCONFIG
AUTO
BOOT
SSPI
MSPI
DUAL
BOOT
SERIAL
CPU
RECONFIG_N
I
√
√
√
√
√
√
√
JTAGSEL_N
I
√
TDO
O
√
TMS
I
√
TCK
I
√
TDI
I
√
READY
I/O
√
√
√
√
√
√
√
DONE
I/O
√
√
√
√
√
√
√
MODE[2:0]
I
√
√
√
√
√
√
SCLK
I
√
√
√
CLKHOLD_N/DIN
I
√
√
√
WE_N/DOUT
O
√
√
MI /D7
I/O
√
√
MO /D6
I/O
√
√
MCS_N /D5
I/O
√
√
MCLK /D4
I/O
√
√
FASTRD_N /D3
I/O
√
√
SI /D2
I/O
√
√
SO /D1
I/O
√
√
SSPI_CS_N/D0
I/O
√
√
Note!
Devices with different modes and packaging support different configuration modes.
Refer to GW1N (R) series of FPGA Products Programming Configuration Guide and
GW2A (R) series of FPGA Products Configuration Guide for configuration modes
supported for different devices;
Please refer to 5Configuration Mode for the definition of each pin in each respective
configuration mode.
4.1.2 Pin Multiplexing
To maximize the utilization of the I/O, Gowin FPGA product support set

4Configuration Pin
4.1Configuration Pin List and Reuse Options
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the configuration pins to regular I/O pins. Before any configuration
operation is performed on the products in the FPGAseries, the pins
associated with the configuration are used as configuration pins by default.
After successful configuration, the device enters into user mode and
redistributes the pin functions according to the reuse options selected by
the user.
Note!
When setting the pin reuse option, ensure the external initial connection state of the pins
does not affect the device configuration. Isolate the connection that affects the
configuration first, then modify in user mode.
The reuse options for the configuration pins are detailed in Table 4-2.
Table 4-2 Pin Reuse Options
Name
Options
Description
JTAG PORT
NON-RECOVERY
TMS, TCK, TDI, and TDO are used as
dedicated configuration pins. JTAGSEL_N is
used as GPIO.
RECOVERY
JTAGSEL_N pins are used as dedicated
configuration pins:
JTAGSEL_N=0, TMS, TCK, TDI, and
TDO are used as configuration pins:
JTAGSEL_N = 1, TMS, TCK, TDI, and
TDO are used as GPIO after
configuration.
SSPI PORT
NON-RECOVERY
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO are used as dedicated configuration
pins.
RECOVERY
SCLK, CLKHOLD_N, SSPI_CS_N, SI and
SO are used as GPIO after configuration.
MSPI PORT
NON-RECOVERY
FASTRD_N, MCLK, MCS_N, MO and MI
are used as dedicated configuration pins.
RECOVERY
FASTRD_N, MCLK, MCS_N, MO and MI
are used as GPIO after configuration.
RECONFIG_N
NON-RECOVERY
Dedicated configuration pins.
RECOVERY
Used as GPIO after configuration.
READY
NON-RECOVERY
Dedicated configuration pins.
RECOVERY
Used as GPIO after configuration.
DONE
NON-RECOVERY
Dedicated configuration pins.
RECOVERY
Used as GPIO after configuration.
Note!
[1] For the devices with JTAGSEL_N unpackaged, when debugging JTAG pin reuse,
the MODE value should be set to non-auto configuration mode (being neither
AUTOBOOT, DUALBOOT, nor MSPI) before power up to avoid the other bitstream
data affecting configuration. The device turns into user MODE, and the JTAG pin
changes into GPIO after the device has been powered up and the JTAG has been
manually configured. For the GW1N(R/S) series of FPGA products, when
MODE[0]=1, the JTAGSEL_N pin and the four pins (TCK, TMS, TDI, TDO) configured
with JTAG can be set as a GPIO simultaneously, but the JTAG pin cannot be
recovered as a configuration pin by JTAGSEL_N. It can be recovered when the
device reenters the configuration state.
[2] The SERIAL and CPU modes share pins with other configuration modes and
cannot be set to GPIO separately, however, the pins can be set to GPIO in
non-shared configuration modes.

4Configuration Pin
4.2Pin Function and Application
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To configure pin reuse via the Gowin software:
1. Open the corresponding project in Gowin software;
2. Select “Project > Configuration > Dual Purpose Pin” from the menu
options, as shown in Figure 4-1;
3. Check the corresponding checkbox to set the pin reuse option.
Figure 4-1 Configuring Pin Reuse
4.2 Pin Function and Application
The Pins RECONFIG_N, READY, and DONE pins are used in each
mode. Other pins may be set as dedicated pins or user pins according to
their specific application.
Table 4-3 Pin Function
Pin Name
Functional Description
RECONFIG_N
As a configuration pin, RECONFIG_N is an input
pin that has an internal weak pull-up. Active low is
used as the reset function for the FPGA
programming configuration. FPGA can't
configure if RECONFIG_N is set to low.
As a configuration pin, a low level signal with pulse
width no less than 25ns is required for
GowinCONFIG to reload bitstream data according
to the MODE setting value. Through write logic,
the control pins trigger the device to reconfigure as
required. As a GPIO pin, RECONFIG_N can only

4Configuration Pin
4.2Pin Function and Application
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Pin Name
Functional Description
be used as an output type. To ensure a smooth
configuration, set the initial value of
RECONFIG_N to high.
READY
In-out pins. High level is valid, configure FPGA
only when the READY signal is pulled up. When
the READY signal is pulled down, restore it by
power up or triggering RECONFIG_N.
As an output configuration pin, FPGAcan be
indicated for the current configuration state. If the
device meets the configuration condition, the
READY signal is high. If the configuration
condition is not met, READY signal is low. As an
input configuration pin, you can reduce the
READY signal via its own logic or manually
operate it outside the device to delay
configuration. As a GPIO, it can be used as an
input or output type. As an input GPIO, the initial
value of READY should be 1 before
configuring. Otherwise, the FPGA will fail to
configure.
DONE
In-out pins. A signal which FPGA is configured
successfully, signal is pulled up after successfully
configuring.
As a output configuration pin, it indicates the
current configuration of FPGA: if configured
successfully, DONE is high and the device enters
into working state. if configuration fails, DONE
signal keeps low. For the input type, the user can
reduce the READY signal via its own internal logic
or manually operate outside the device to delay
progression to user mode. When the
RECONFIG_N or READY signals are low. The
DONE signal is low. DONE has no influence when
configuring SRAM through the JTAG circuit. As a
GPIO, it can be used as an input or output type.
As an input GPIO, the initial value of DONE
should be 1 before configuring, otherwise
FPGA fails to enter user mode after
configuring.
MODE
As the selection pin of GowinCONFIG modes,
MODE is an input pin that has internal weak
pull-up. The maximum bit width is 3-bit. When
FPGA powers up or a low level pulse triggers
RECONFIG_N, the device turns into the
corresponding state in accordance with the
GowinCONFIG MODE value, each MODE value
of the Gowin series of FPGA products that
corresponds to the configuration MODE is slightly
different. Please refer to the corresponding device