GOWIN GW1N Series User manual

Gowin FPGA Products
Programming and Configuration Guide
UG290-2.5.2E, 07/14/2022

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, Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin
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and is not responsible for any damage incurred to your hardware, software, data, or
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the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
4/17/2017
1.00E
Initial version published.
5/31/2017
1.01E
Configuration mode and value of different supported
device updated;
RECONFIG N notes during programming built-in Flash
updated.
10/13/2017
1.02E
Description of reusing pins updated.
3/16/2018
1.03E
GW1NS programming and configuration description added.
8/8/2018
1.04E
The description of configuration process when Flash is
empty updated;
Operation procedures for multiple configurations
updated;
When MODE[0]=1, JTAG pins reuse description updated;
The programming features of B version devices updated;
Configuration notes and the timing for different
configuration modes added.
1/8/2019
1.05E
The configuration timing and parameters for SERIAL
mode added;
The description of power supply requirements deleted.
8/16/2019
1.06E
Power up description and configuration flow added;
The description of File Size Configuration modified.
5/15/2020
2.0E
The note of JTAGSEL_N used as IO added.
GW1N(R)-2/GW1N(R)-2B/GW1N(R)-6 removed;
Configuration mode description optimized.
8/20/2020
2.1E
JTAG Configuration added;
SSPI Configuration added;
AES Programming added;
10/30/2020
2.2E
Configuration File Loading Time added.
02/07/2021
2.3E
I2C Configuration added.
09/24/2021
2.4E
Configuration process added;
The flow chart of configuring or programming
SRAM/Flash for GW1N-2 added;
Process of internal Flash programming added.
01/20/2022
2.4.1E
Remarks about I2C configuration mode added.
05/07/2022
2.5E
Information on GW2AN-9X/18X deleted.
6.5 MSPI section updated.
05/10/2022
2.5.1E
CPU Mode Configuration Timing diagram updated.
07/14/2022
2.5.2E
Information on configuration file size added.
Count of address and length of one address of GW1N-2
SRAM updated.
Description of loading frequency for GW1N-2 devices
added.

Contents
UG290-2.5.2E
i
Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................ 1
1.3 Terminology and Abbreviations .......................................................................................... 1
1.4 Support and Feedback.......................................................................................................2
2 Glossary ...........................................................................................................3
3 Configuration Modes.......................................................................................5
3.1 LittleBee® Family of FPGA Products ..................................................................................5
3.2 Arora Family of FPGA Products .........................................................................................7
4 Configuration Process ....................................................................................8
4.1 Power-up Sequence......................................................................................................... 10
4.2 Initialization........................................................................................................................11
4.3 Configuration.....................................................................................................................11
4.4 Wake-up ............................................................................................................................11
4.5 User Mode........................................................................................................................12
5 Configuration Pin...........................................................................................13
5.1 Configuration Pin List and Reuse Options .......................................................................13
5.1.1 Configuration Pin List .................................................................................................... 13
5.1.2 Configuration Pin Reuse ...............................................................................................14
5.2 Configuration Pin Function and Application ..................................................................... 16
6 Configuration Mode Introduction .................................................................21
6.1 Configuration Notes..........................................................................................................21
6.2 JTAG Configuration .......................................................................................................... 25
6.2.1 JTAG Configuration Mode Pins..................................................................................... 25
6.2.2 Connection Diagram for the JTAG Configuration Mode................................................26
6.2.3 JTAG Configuration Timing ........................................................................................... 27
6.2.4 JTAG Configuration Process......................................................................................... 28

Contents
UG290-2.5.2E
ii
6.3 AUTO BOOT Configuration (Supported by LittleBee® Family Only) ................................55
6.4 SSPI ................................................................................................................................. 57
6.4.1 SSPI Mode Pins ............................................................................................................57
6.4.2 SSPI Configuration Timing ............................................................................................ 58
6.4.3 Configuration Instruction ...............................................................................................58
6.4.4 Connection Diagram for SSPI Configuration Mode ......................................................62
6.4.5 Multiple FPGA Connection View in SSPI Mode ............................................................63
6.5 MSPI.................................................................................................................................64
6.5.1 MSPI Mode Pins............................................................................................................65
6.5.2 Connection Diagram for MSPI Configuration Mode ......................................................66
6.5.3 MSPI Mode Configuration Attempts................................................................................ 67
6.5.4 MULTI BOOT................................................................................................................. 67
6.5.5 MSPI Configuration Timing............................................................................................71
6.6 DUAL BOOT Configuration (Supported by LittleBee® Family Only) ................................ 72
6.7 CPU Mode........................................................................................................................74
6.7.1 Configuration Timing .....................................................................................................75
6.8 SERIAL Mode................................................................................................................... 75
6.9 I2C Mode........................................................................................................................... 77
6.9.1 Process of GW1N-2 Configuring or Programming SRAM/Flash ..................................80
7 Bitstream File Configuration.........................................................................81
7.1 Configuration Options.......................................................................................................81
7.2 Configuration Data Encryption (Supported by Arora Family only).................................... 82
7.2.1 Definition .......................................................................................................................82
7.2.2 Enter Encryption KEY....................................................................................................83
7.2.3 Enter the Decrypt Key ................................................................................................... 83
7.2.4 Programming Operation................................................................................................84
7.2.5 Programming Flow ........................................................................................................86
7.3 Configuration File Size ..................................................................................................... 89
7.4 Configuration File Loading Time ......................................................................................91
8 Safety Precautions ........................................................................................94
9 Boundary Scan ..............................................................................................96
10 SPI Flash Selection......................................................................................98

List of Figures
UG290-2.5.2E
iii
List of Figures
Figure 4-1 POR Power-up Timing......................................................................................................10
Figure 5-1 Configuring Pin Reuse ..................................................................................................... 16
Figure 5-2 MCLK Frequency Setting ................................................................................................. 19
Figure 6-1 Recommended Pin Connection........................................................................................ 23
Figure 6-2 Power Recycle Timing......................................................................................................24
Figure 6-3 Trigger Timing................................................................................................................... 24
Figure 6-4 Connection Diagram for JTAG Configuration Mode......................................................... 26
Figure 6-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode ..................................... 27
Figure 6-6 JTAG Configuration timing................................................................................................27
Figure 6-7 TAP State Machine........................................................................................................... 28
Figure 6-8 Instruction Register Access Timing ..................................................................................29
Figure 6-9 Data Register Access Timing ........................................................................................... 29
Figure 6-10 Read Machine Flow Chart in ID Code State ..................................................................31
Figure 6-11 The Access Timing of Read ID Code Instruction- 0x11 .................................................. 31
Figure 6-12 Read ID Code Data Register Access Timing .................................................................31
Figure 6-13 SRAM Configuration Flow .............................................................................................. 33
Figure 6-14 Process of reading SRAM .............................................................................................. 35
Figure 6-15 Process of Normal Programming ................................................................................... 37
Figure 6-16 Process of Background Programming............................................................................38
Figure 6-17 The Embedded Flash Erasing process of T Technology................................................40
Figure 6-18 The Embedded Flash Erasing process of H Technology ............................................... 42
Figure 6-19 Process of Programming Internal Flash View ................................................................44
Figure 6-20 X-page Programming .....................................................................................................45
Figure 6-21 Y-page Programming ..................................................................................................... 46
Figure 6-22 Process of Reading Internal Flash ................................................................................. 47
Figure 6-23 Process of Reading a Y-page ........................................................................................48
Figure 6-24 GW1N-4 Background Programming Flow......................................................................49
Figure 6-25 Transfer JTAG Instruction Sample & Extest Flow Chart ................................................ 50
Figure 6-26 Connection Diagram of JTAG Programming External Flash..........................................51
Figure 6-27 Process View of Programming SPI Flash SPI................................................................51
Figure 6-28 Timing Diagram of Sending 0x06 via GW2A series JTAG Simulating SPI..................... 52

List of Figures
UG290-2.5.2E
iv
Figure 6-29 Timing Diagram of Sending 0x06 via GW1N series JTAG Simulating SPI ....................52
Figure 6-30 Process of Use Boundary Scan Mode To Program SPI Flash.......................................53
Figure 6-31 Connection Diagram of Daisy-Chain.............................................................................. 55
Figure 6-32 SSPI Configuration Timing ............................................................................................. 58
Figure 6-33 Read ID Code Timing ..................................................................................................... 59
Figure 6-34 Write Enable (0x15) Timing ............................................................................................60
Figure 6-35 Write Disable(0x3A00) Timing........................................................................................ 60
Figure 6-36 Write Data (0x3B) Timing ............................................................................................... 61
Figure 6-37 SSPI Configuration Mode Connection Diagram..................................................................62
Figure 6-38 Connection Diagram of Programming External Flash via SSPI..................................... 62
Figure 6-39 The Flow of Programming External Flash via SSPI .......................................................63
Figure 6-40 Multiple FPGA Connection Diagram 1............................................................................ 63
Figure 6-41 Multiple FPGA Connection Diagram 2............................................................................ 63
Figure 6-42 Connection Diagram for MSPI Configuration Mode........................................................ 66
Figure 6-43 Connection Diagram of JTAG Programming External Flash.......................................... 66
Figure 6-44 Example of Bitstream Image Distribution in Flash Memory ........................................... 68
Figure 6-45 Input the Start address for the Next Bitstream................................................................ 69
Figure 6-46 Set the Programming Address for the External Flash ....................................................70
Figure 6-47 Connection Diagram for Configuring Multiple FPGAs via Single Flash.......................... 71
Figure 6-48 MSPI Download Timing ..................................................................................................71
Figure 6-49 Multiple FPGA Connection Diagram in MSPI Configuration Mode.................................72
Figure 6-50 Dual Boot Flow Chart .....................................................................................................73
Figure 6-51 Connection Diagram for CPU Mode...............................................................................75
Figure 6-52 CPU Mode Configuration Timing....................................................................................75
Figure 6-53 Connection Diagram for SERIAL Mode..........................................................................76
Figure 6-54 SERIAL Configuration Timing.........................................................................................76
Figure 6-55 Connection Diagram for I2C Mode ................................................................................. 78
Figure 6-56 I2C Mode Timing .............................................................................................................78
Figure 6-57 Process of GW1N-2 Configuring or Programming SRAM/Flash.................................... 80
Figure 7-1 Configuration Options....................................................................................................... 82
Figure 7-2 Encryption Key Setting Method........................................................................................83
Figure 7-3 Setting the Decryption Key............................................................................................... 84
Figure 7-4 AES Security Configure.................................................................................................... 85
Figure 7-5 Prepare.............................................................................................................................86
Figure 7-6 Read AES Key Flow ......................................................................................................... 87
Figure 7-7 Program AES Key Flow.................................................................................................... 88
Figure 7-8 Lock AES Key Flow .......................................................................................................... 89
Figure 7-9 Bitstream Format generation............................................................................................90
Figure 9-1 Boundary Scan Operation Schematic Diagram ............................................................... 97

List of Tables
UG290-2.5.2E
v
List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 1
Table 2-1 Glossary ............................................................................................................................. 3
Table 3-1 Configuration Modes..........................................................................................................6
Table 3-2 Configuration Modes..........................................................................................................7
Table 4-1 Power Rails Monitored by POR Circuits of Different Devices............................................ 10
Table 5-1 Configuration Pin List.........................................................................................................13
Table 5-2 Pin Reuse Options ............................................................................................................. 15
Table 5-3 Pin Function ....................................................................................................................... 16
Table 6-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 24
Table 6-2 Timing Parameters for Power-on again and RECONFIG_N Triggering (Arora Family) .... 25
Table 6-3 Pin Description in JTAG Configuration Mode..................................................................... 25
Table 6-4 JTAG Configuration Timing Parameters ............................................................................ 27
Table 6-5 Gowin FPGA IDCODE ....................................................................................................... 29
Table 6-6 Change of TDI and TMS Value in The Process of Sending Instructions ........................... 30
Table 6-7 Count of Address and Length of One Address ..................................................................34
Table 6-8 TCK Frequency Requirements for JTAG ........................................................................... 38
Table 6-9 Readback-pattern / Autoboot-pattern................................................................................. 43
Table 6-10 Pin State........................................................................................................................... 52
Table 6-11 Status Register Definition.................................................................................................54
Table 6-12 SSPI Mode Pins...............................................................................................................57
Table 6-13 SSPI Configuration Timing Parameters ........................................................................... 58
Table 6-14 Configuration Instruction .................................................................................................. 59
Table 6-15 Pin Description in MSPI Configuration Mode ................................................................... 65
Table 6-16 MSPI Configuration Timing Parameters........................................................................... 72
Table 6-17 CPU Mode Pins................................................................................................................ 74
Table 6-18 Pin Definition in SERIAL Configuration Mode.................................................................. 76
Table 6-19 SERIAL Configuration Timing Parameters....................................................................... 77
Table 6-20 Pin Definition in SERIAL Configuration Mode.................................................................. 77
Table 6-21 I2C Configuration Timing Parameters ..............................................................................78
Table 7-1 Gowin FPGA Products Configuration File Size (Max.) ...................................................... 90
Table 7-2 Loading Frequency of Config File......................................................................................92
Table 7-3 Loading Time in MSPI Mode..............................................................................................93

List of Tables
UG290-2.5.2E
vi
Table 7-4 Loading Time in Autoboot Mode ........................................................................................ 93
Table 10-1 SPI Flash Operation Instruction.......................................................................................98

1 About This Guide
1.1 Purpose
UG290-2.5.2E
1(98)
1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of LittleBee® family devices and Arora
family devices. It helps users to use Gowin FPGA products to their full
potential.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS100, GW1N series of FPGA Products Data Sheet
DS102, GW2A series of FPGA Products Data Sheet
DS117, GW1NR series of FPGA Products Data Sheet
DS226, GW2AR series of FPGA Products Data Sheet
DS961, GW2ANR series of FPGA Products Data Sheet
DS821, GW1NS series of FPGA Products Data Sheet
DS841, GW1NZ series of FPGA Products Data Sheet
DS861, GW1NSR series of FPGA Products Data Sheet
DS871, GW1NSE series of FPGA Products Data Sheet
DS881, GW1NSER series of FPGA Products Data Sheet
DS891, GW1NRF series of FPGA Products Data Sheet
DS961, GW2ANR series of FPGA Products Data Sheet
DS976, GW2AN-55 Data Sheet
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
Table 1-1.
Table 1-1 Abbreviations and Terminology
Terminology and Abbreviations
Full Name
LUT
Look-up Table
FPGA
Field Programmable Gate Array
JTAG
Joint Test Action Group