GOWIN GW1N Series User manual

Gowin FPGA Products
Programming and Configuration Guide
UG290-2.5.2E, 07/14/2022

Copyright © 2022 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, LittleBee, and GOWINSEMI are trademarks of Guangdong Gowin
Semiconductor Corporation and are registered in China, the U.S. Patent and Trademark
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
4/17/2017
1.00E
Initial version published.
5/31/2017
1.01E
Configuration mode and value of different supported
device updated;
RECONFIG N notes during programming built-in Flash
updated.
10/13/2017
1.02E
Description of reusing pins updated.
3/16/2018
1.03E
GW1NS programming and configuration description added.
8/8/2018
1.04E
The description of configuration process when Flash is
empty updated;
Operation procedures for multiple configurations
updated;
When MODE[0]=1, JTAG pins reuse description updated;
The programming features of B version devices updated;
Configuration notes and the timing for different
configuration modes added.
1/8/2019
1.05E
The configuration timing and parameters for SERIAL
mode added;
The description of power supply requirements deleted.
8/16/2019
1.06E
Power up description and configuration flow added;
The description of File Size Configuration modified.
5/15/2020
2.0E
The note of JTAGSEL_N used as IO added.
GW1N(R)-2/GW1N(R)-2B/GW1N(R)-6 removed;
Configuration mode description optimized.
8/20/2020
2.1E
JTAG Configuration added;
SSPI Configuration added;
AES Programming added;
10/30/2020
2.2E
Configuration File Loading Time added.
02/07/2021
2.3E
I2C Configuration added.
09/24/2021
2.4E
Configuration process added;
The flow chart of configuring or programming
SRAM/Flash for GW1N-2 added;
Process of internal Flash programming added.
01/20/2022
2.4.1E
Remarks about I2C configuration mode added.
05/07/2022
2.5E
Information on GW2AN-9X/18X deleted.
6.5 MSPI section updated.
05/10/2022
2.5.1E
CPU Mode Configuration Timing diagram updated.
07/14/2022
2.5.2E
Information on configuration file size added.
Count of address and length of one address of GW1N-2
SRAM updated.
Description of loading frequency for GW1N-2 devices
added.

Contents
UG290-2.5.2E
i
Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................ 1
1.3 Terminology and Abbreviations .......................................................................................... 1
1.4 Support and Feedback.......................................................................................................2
2 Glossary ...........................................................................................................3
3 Configuration Modes.......................................................................................5
3.1 LittleBee® Family of FPGA Products ..................................................................................5
3.2 Arora Family of FPGA Products .........................................................................................7
4 Configuration Process ....................................................................................8
4.1 Power-up Sequence......................................................................................................... 10
4.2 Initialization........................................................................................................................11
4.3 Configuration.....................................................................................................................11
4.4 Wake-up ............................................................................................................................11
4.5 User Mode........................................................................................................................12
5 Configuration Pin...........................................................................................13
5.1 Configuration Pin List and Reuse Options .......................................................................13
5.1.1 Configuration Pin List .................................................................................................... 13
5.1.2 Configuration Pin Reuse ...............................................................................................14
5.2 Configuration Pin Function and Application ..................................................................... 16
6 Configuration Mode Introduction .................................................................21
6.1 Configuration Notes..........................................................................................................21
6.2 JTAG Configuration .......................................................................................................... 25
6.2.1 JTAG Configuration Mode Pins..................................................................................... 25
6.2.2 Connection Diagram for the JTAG Configuration Mode................................................26
6.2.3 JTAG Configuration Timing ........................................................................................... 27
6.2.4 JTAG Configuration Process......................................................................................... 28

Contents
UG290-2.5.2E
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6.3 AUTO BOOT Configuration (Supported by LittleBee® Family Only) ................................55
6.4 SSPI ................................................................................................................................. 57
6.4.1 SSPI Mode Pins ............................................................................................................57
6.4.2 SSPI Configuration Timing ............................................................................................ 58
6.4.3 Configuration Instruction ...............................................................................................58
6.4.4 Connection Diagram for SSPI Configuration Mode ......................................................62
6.4.5 Multiple FPGA Connection View in SSPI Mode ............................................................63
6.5 MSPI.................................................................................................................................64
6.5.1 MSPI Mode Pins............................................................................................................65
6.5.2 Connection Diagram for MSPI Configuration Mode ......................................................66
6.5.3 MSPI Mode Configuration Attempts................................................................................ 67
6.5.4 MULTI BOOT................................................................................................................. 67
6.5.5 MSPI Configuration Timing............................................................................................71
6.6 DUAL BOOT Configuration (Supported by LittleBee® Family Only) ................................ 72
6.7 CPU Mode........................................................................................................................74
6.7.1 Configuration Timing .....................................................................................................75
6.8 SERIAL Mode................................................................................................................... 75
6.9 I2C Mode........................................................................................................................... 77
6.9.1 Process of GW1N-2 Configuring or Programming SRAM/Flash ..................................80
7 Bitstream File Configuration.........................................................................81
7.1 Configuration Options.......................................................................................................81
7.2 Configuration Data Encryption (Supported by Arora Family only).................................... 82
7.2.1 Definition .......................................................................................................................82
7.2.2 Enter Encryption KEY....................................................................................................83
7.2.3 Enter the Decrypt Key ................................................................................................... 83
7.2.4 Programming Operation................................................................................................84
7.2.5 Programming Flow ........................................................................................................86
7.3 Configuration File Size ..................................................................................................... 89
7.4 Configuration File Loading Time ......................................................................................91
8 Safety Precautions ........................................................................................94
9 Boundary Scan ..............................................................................................96
10 SPI Flash Selection......................................................................................98

List of Figures
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List of Figures
Figure 4-1 POR Power-up Timing......................................................................................................10
Figure 5-1 Configuring Pin Reuse ..................................................................................................... 16
Figure 5-2 MCLK Frequency Setting ................................................................................................. 19
Figure 6-1 Recommended Pin Connection........................................................................................ 23
Figure 6-2 Power Recycle Timing......................................................................................................24
Figure 6-3 Trigger Timing................................................................................................................... 24
Figure 6-4 Connection Diagram for JTAG Configuration Mode......................................................... 26
Figure 6-5 Connection Diagram of JTAG Daisy-Chain Configuration Mode ..................................... 27
Figure 6-6 JTAG Configuration timing................................................................................................27
Figure 6-7 TAP State Machine........................................................................................................... 28
Figure 6-8 Instruction Register Access Timing ..................................................................................29
Figure 6-9 Data Register Access Timing ........................................................................................... 29
Figure 6-10 Read Machine Flow Chart in ID Code State ..................................................................31
Figure 6-11 The Access Timing of Read ID Code Instruction- 0x11 .................................................. 31
Figure 6-12 Read ID Code Data Register Access Timing .................................................................31
Figure 6-13 SRAM Configuration Flow .............................................................................................. 33
Figure 6-14 Process of reading SRAM .............................................................................................. 35
Figure 6-15 Process of Normal Programming ................................................................................... 37
Figure 6-16 Process of Background Programming............................................................................38
Figure 6-17 The Embedded Flash Erasing process of T Technology................................................40
Figure 6-18 The Embedded Flash Erasing process of H Technology ............................................... 42
Figure 6-19 Process of Programming Internal Flash View ................................................................44
Figure 6-20 X-page Programming .....................................................................................................45
Figure 6-21 Y-page Programming ..................................................................................................... 46
Figure 6-22 Process of Reading Internal Flash ................................................................................. 47
Figure 6-23 Process of Reading a Y-page ........................................................................................48
Figure 6-24 GW1N-4 Background Programming Flow......................................................................49
Figure 6-25 Transfer JTAG Instruction Sample & Extest Flow Chart ................................................ 50
Figure 6-26 Connection Diagram of JTAG Programming External Flash..........................................51
Figure 6-27 Process View of Programming SPI Flash SPI................................................................51
Figure 6-28 Timing Diagram of Sending 0x06 via GW2A series JTAG Simulating SPI..................... 52

List of Figures
UG290-2.5.2E
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Figure 6-29 Timing Diagram of Sending 0x06 via GW1N series JTAG Simulating SPI ....................52
Figure 6-30 Process of Use Boundary Scan Mode To Program SPI Flash.......................................53
Figure 6-31 Connection Diagram of Daisy-Chain.............................................................................. 55
Figure 6-32 SSPI Configuration Timing ............................................................................................. 58
Figure 6-33 Read ID Code Timing ..................................................................................................... 59
Figure 6-34 Write Enable (0x15) Timing ............................................................................................60
Figure 6-35 Write Disable(0x3A00) Timing........................................................................................ 60
Figure 6-36 Write Data (0x3B) Timing ............................................................................................... 61
Figure 6-37 SSPI Configuration Mode Connection Diagram..................................................................62
Figure 6-38 Connection Diagram of Programming External Flash via SSPI..................................... 62
Figure 6-39 The Flow of Programming External Flash via SSPI .......................................................63
Figure 6-40 Multiple FPGA Connection Diagram 1............................................................................ 63
Figure 6-41 Multiple FPGA Connection Diagram 2............................................................................ 63
Figure 6-42 Connection Diagram for MSPI Configuration Mode........................................................ 66
Figure 6-43 Connection Diagram of JTAG Programming External Flash.......................................... 66
Figure 6-44 Example of Bitstream Image Distribution in Flash Memory ........................................... 68
Figure 6-45 Input the Start address for the Next Bitstream................................................................ 69
Figure 6-46 Set the Programming Address for the External Flash ....................................................70
Figure 6-47 Connection Diagram for Configuring Multiple FPGAs via Single Flash.......................... 71
Figure 6-48 MSPI Download Timing ..................................................................................................71
Figure 6-49 Multiple FPGA Connection Diagram in MSPI Configuration Mode.................................72
Figure 6-50 Dual Boot Flow Chart .....................................................................................................73
Figure 6-51 Connection Diagram for CPU Mode...............................................................................75
Figure 6-52 CPU Mode Configuration Timing....................................................................................75
Figure 6-53 Connection Diagram for SERIAL Mode..........................................................................76
Figure 6-54 SERIAL Configuration Timing.........................................................................................76
Figure 6-55 Connection Diagram for I2C Mode ................................................................................. 78
Figure 6-56 I2C Mode Timing .............................................................................................................78
Figure 6-57 Process of GW1N-2 Configuring or Programming SRAM/Flash.................................... 80
Figure 7-1 Configuration Options....................................................................................................... 82
Figure 7-2 Encryption Key Setting Method........................................................................................83
Figure 7-3 Setting the Decryption Key............................................................................................... 84
Figure 7-4 AES Security Configure.................................................................................................... 85
Figure 7-5 Prepare.............................................................................................................................86
Figure 7-6 Read AES Key Flow ......................................................................................................... 87
Figure 7-7 Program AES Key Flow.................................................................................................... 88
Figure 7-8 Lock AES Key Flow .......................................................................................................... 89
Figure 7-9 Bitstream Format generation............................................................................................90
Figure 9-1 Boundary Scan Operation Schematic Diagram ............................................................... 97

List of Tables
UG290-2.5.2E
v
List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 1
Table 2-1 Glossary ............................................................................................................................. 3
Table 3-1 Configuration Modes..........................................................................................................6
Table 3-2 Configuration Modes..........................................................................................................7
Table 4-1 Power Rails Monitored by POR Circuits of Different Devices............................................ 10
Table 5-1 Configuration Pin List.........................................................................................................13
Table 5-2 Pin Reuse Options ............................................................................................................. 15
Table 5-3 Pin Function ....................................................................................................................... 16
Table 6-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger ................................... 24
Table 6-2 Timing Parameters for Power-on again and RECONFIG_N Triggering (Arora Family) .... 25
Table 6-3 Pin Description in JTAG Configuration Mode..................................................................... 25
Table 6-4 JTAG Configuration Timing Parameters ............................................................................ 27
Table 6-5 Gowin FPGA IDCODE ....................................................................................................... 29
Table 6-6 Change of TDI and TMS Value in The Process of Sending Instructions ........................... 30
Table 6-7 Count of Address and Length of One Address ..................................................................34
Table 6-8 TCK Frequency Requirements for JTAG ........................................................................... 38
Table 6-9 Readback-pattern / Autoboot-pattern................................................................................. 43
Table 6-10 Pin State........................................................................................................................... 52
Table 6-11 Status Register Definition.................................................................................................54
Table 6-12 SSPI Mode Pins...............................................................................................................57
Table 6-13 SSPI Configuration Timing Parameters ........................................................................... 58
Table 6-14 Configuration Instruction .................................................................................................. 59
Table 6-15 Pin Description in MSPI Configuration Mode ................................................................... 65
Table 6-16 MSPI Configuration Timing Parameters........................................................................... 72
Table 6-17 CPU Mode Pins................................................................................................................ 74
Table 6-18 Pin Definition in SERIAL Configuration Mode.................................................................. 76
Table 6-19 SERIAL Configuration Timing Parameters....................................................................... 77
Table 6-20 Pin Definition in SERIAL Configuration Mode.................................................................. 77
Table 6-21 I2C Configuration Timing Parameters ..............................................................................78
Table 7-1 Gowin FPGA Products Configuration File Size (Max.) ...................................................... 90
Table 7-2 Loading Frequency of Config File......................................................................................92
Table 7-3 Loading Time in MSPI Mode..............................................................................................93

List of Tables
UG290-2.5.2E
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Table 7-4 Loading Time in Autoboot Mode ........................................................................................ 93
Table 10-1 SPI Flash Operation Instruction.......................................................................................98

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
This guide mainly introduces general features and functions on
programming and configuration of LittleBee® family devices and Arora
family devices. It helps users to use Gowin FPGA products to their full
potential.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS100, GW1N series of FPGA Products Data Sheet
DS102, GW2A series of FPGA Products Data Sheet
DS117, GW1NR series of FPGA Products Data Sheet
DS226, GW2AR series of FPGA Products Data Sheet
DS961, GW2ANR series of FPGA Products Data Sheet
DS821, GW1NS series of FPGA Products Data Sheet
DS841, GW1NZ series of FPGA Products Data Sheet
DS861, GW1NSR series of FPGA Products Data Sheet
DS871, GW1NSE series of FPGA Products Data Sheet
DS881, GW1NSER series of FPGA Products Data Sheet
DS891, GW1NRF series of FPGA Products Data Sheet
DS961, GW2ANR series of FPGA Products Data Sheet
DS976, GW2AN-55 Data Sheet
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown in
Table 1-1.
Table 1-1 Abbreviations and Terminology
Terminology and Abbreviations
Full Name
LUT
Look-up Table
FPGA
Field Programmable Gate Array
JTAG
Joint Test Action Group

1 About This Guide
1.4 Support and Feedback
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Terminology and Abbreviations
Full Name
GPIO
General Purpose Input Output
SPI
Serial Peripheral Interface
SRAM
Static Random Access Memory
MSPI
Master Serial Peripheral Interface
SSPI
Slave Serial Peripheral Interface
CPU
Central Processing Unit
IEEE
Institute of Electrical and Electronics Engineers
ID
Identification
CRC
Cyclic Redundancy Check
FS file
Fuses file
Configuration
Configuration
Configuration Data
Configuration Data
Bitstream
Bitstream Data
Configuration Mode
Configuration Mode
EFlash/EmbFlash
Embedded Flash
Internal Flash
Internal Flash
Programming
Programming
Edit Mode
Edit Mode
User Mode
User Mode
Background Programming
Embedded Flash Background Programming
LSB
Least Significant Bit
MSB
Most Significant Bit
TAP
Test Access Port
Security Bit
Security Bit
Bscan
Boundary Scan
I2C (I2C、IIC)
Inter-Integrated Circuits
SCL
Serial Clock
SDA
Serial Data
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail:[email protected]

2 Glossary
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2Glossary
This chapter presents an overview of the terms that are commonly
used in the process of programming and configuring of Gowin FPGA
products to help users get familiar with the related concepts.
Table 2-1 Glossary
Glossary
Meaning
Program
Write the bitstream data generated by Gowin software to the
embedded Flash or external SPI Flash of FPGA.
Configure
Load the bitstream data generated by Gowin software to the
FPGA SRAM via external interfaces or embedded Flash.
GowinCONFIG
In addition to the generic JTAG configuration mode, Gowin
FPGA products support additional configurations, including
AUTO BOOT configuration, DUAL BOOT configuration, MSPI
configuration, SSPI configuration, SERIAL configuration, and
CPU configuration. How many GowinCONFIG configuration
modes each device supports depend on the device model and
package.
MODE[2:0]
A representation of the three MODE pin values associated
with GowinCONFIG.
AUTO BOOT
Configuration
FPGA loads bitstream data into the SRAM from an embedded
Flash. Only non-volatile devices support this mode.
DUAL BOOT Configuration
Two bitstream files are stored in embedded Flash and
external Flash separately. Switch to the embedded Flash if the
external Flash fails to configure. Only non-volatile devices
support this mode.
MSPI Configuration
As a master, FPGA is configured by reading bitstream from
the external Flash via the SPI interface automatically.
SSPI Configuration
As a slave device, the bitstream data is written into the FPGA
via the SPI interface by the external master.
SERIAL Configuration
As a slave device, the bitstream data is written into the FPGA
via the serial interface by the external master.
CPU Configuration
As a slave device, the bitstream data is written into the FPGA
via the parallel interface (8-bit) by the external master.

2 Glossary
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Glossary
Meaning
I2C Configuration
As a slave device, the bitstream data is written into the FPGA
via the I2C interface by the external master.
MULTI BOOT
Configuration
The derivative concept of MSPI, it refers to that FPGA reads
bitstream data from different addresses of external Flash. The
loading address of the latter bitstream data is written in
previous bitstream data and the configuration is completed by
triggering RECONFIG_N to switch the data stream file under
the condition that the device power is on. FPGA products that
support MSPI all support this mode.
Remote Upgrade
After FPGA starts to work, if an upgrade is required, first write
bitstream to an embedded or external Flash through remote
operation, and then FPGA reads the external Flash by
triggering RECONFIG_N or powering up again to complete
the configuration.
Daisy Chain
FPGA devices are connected sequentially in a serial way.
Devices can be configured from the head of the chain in
sequence according to the connection order, and data can
only be transmitted between adjacent devices.
User Mode
Hands over control to users when the FPGA configuration has
been completed. Only in user mode, configuration pins can be
reused as GPIOs (Gowin Programmable I/O).
Edit Mode
FPGA can be programmed and configured in this mode.
All configuration pins cannot be reused as GPIOs. The output
of all GPIOs is high-impedance state, except transparent
transmission.
ID CODE
Identification for the Gowin FPGA device. Each series of
devices has a different number.
USER CODE
Used to identify the FPGA device that used. The user code
can be written to the FPGA device through Gowin
programmer. Up to 32-bit can be supported.
Security Bit
A special design for the configuration data security of Gowin
FPGA product. After you write the bitstream with security bit to
the device SRAM, no one will be able to read back the data.
Gowin software sets a security bit for the bitstream data of all
FPGA products by default.
Encryption
The Arora family of FPGA products supports this feature. After
the encrypted bitstream is written to FPGA, the device will
match the pre-stored key automatically, and then decrypt and
wake up the device after successful matching. The device
cannot work if matching fails.

3 Configuration Modes
3.1 LittleBee® Family of FPGA Products
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3Configuration Modes
3.1 LittleBee®Family of FPGA Products
Besides the JTAG configuration mode that is commonly used in the
industry, the LittleBee® Family of FPGA products also support
GOWINSEMI's own configuration mode: GowinCONFIG. GowinCONFIG
configuration modes that are available and supported for each device
depend on the device model and package. All non-volatile devices support
JTAG and AUTO BOOT modes. Up to six configuration modes are
supported, as shown in Table 3-1.

3 Configuration Modes
3.1 LittleBee® Family of FPGA Products
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Table 3-1 Configuration Modes
Configuration Modes
MODE[2:0][1]
Description
JTAG
XXX[2]
The LittleBee® Family of FPGA products
are configured via JTAG interface by
external Host.
GowinCONFIG
AUTO
BOOT
000
FPGA reads data from embedded Flash
for configuration
I2C[6]
100
FPGA products are configured via I2C
interface by external Host.
SSPI
001
FPGA products of LittleBee® Family are
configured via SPI interface.
MSPI
010
As a Master, FPGA reads data from
external Flash (or other devices) via the
SPI interface[3].
DUAL
BOOT[4]
110
FPGA reads data from external Flash
first and if the external Flash
configuration fails, it reads from the
Internal Flash.
SERIAL[5]
101
External Host configure FPGA products
of LittleBee® Family via DIN interface.
CPU[5]
111
External Host configure FPGA products
of LittleBee® Family via DBUS interface.
Note!
[1] The unbound mode pins are grounded by default;
[2] The JTAG configuration mode is independent of MODE value;
[3] The SPI interfaces of the SSPI and MSPI modes are independent of each other;
[4] Currently GW1N(R)-4 / GW1N(R)-4B do not support DUAL BOOT;
[5] The CPU configuration mode and SERIAL configuration mode share SCLK,
WE_N and CLKHOLD_N. The data bus pins for the CPU configuration mode share
pins with MSPI and SSPI configuration modes.
[6] I2C is only supported in some devices. Autoboot is automatically enabled in I2C
mode. In I2C mode, following power-on the LittleBee devices will attempt to read data
from internal Flash first. The I2C SCL and SDA lines MUST be held inactive (pulled-up)
during Autoboot, otherwise the device maynot be configured correctly.
Note!
For details about configuration pins, pin reuse, and pin functions and application, please
refer to 5 Configuration Pin.

3 Configuration Modes
3.2 Arora Family of FPGA Products
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3.2 Arora Family of FPGA Products
Besides the JTAG configuration mode that is commonly used in the
industry, the Arora Family of FPGA products also support GOWINSEMI's
own configuration mode: GowinCONFIG. The GowinCONFIG configuration
modes that are available and supported for each device depend on the
device model and package. The Arora Family of FPGA Products support
bitstream encryption and security bit setting, which provides safety for user
designs. The Arora Family FPGA products support bitstream
decompression; users can compress bitstream to save storage memory.
Table 3-2 lists the configuration modes that are supported by the Arora
Family FPGA products.
Table 3-2 Configuration Modes
Configuration Modes
MODE[2:0]1
Description
JTAG
XXX2
External Host configures Arora Family of
FPGA products via JTAG interface.
GowinCONFIG
MSPI
000
As Master, FPGA reads data from
external Flash (or other devices) via the
SPI interface3.
SSPI
001
External Host configures Arora Family of
FPGA products via SPI interface.
SERIAL4
101
External Host configures Arora Family of
FPGA products via DIN interface.
CPU4
111
External Host configures Arora Family of
FPGA products via DBUS interface.
Note!
[1] The unbound mode pins are grounded by default;
[2] The JTAG configuration mode is independent of MODE value;
[3] The SPI interfaces of the SSPI and MSPI modes are independent of each other;
[4] The CPU configuration mode and SERIAL configuration mode share SCLK,
WE_N and CLKHOLD_N. The data bus pins for the CPU configuration mode share
pins with MSPI and SSPI configuration modes.
Note!
For details about configuration pins, pin reuse, and pin functions and application, please
refer to 5 Configuration Pin.

4 Configuration Process
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4Configuration Process
After power on, the FPGA goes through a sequence of states including
initialization, SRAM configuration, and wake-up. The configuration flow is
as shown in below.

4 Configuration Process
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Figure 4-1 Configuration Flow
Power Up
(VCC/VCCO/VCCX
meets power
requirements)
READY and DONE
Internal Driven Low
Initialization
READY Driven High
and MODE Value
Sampled
Write SRAM
Memory and
Verify
FPGA Waken
Up
DONE Driven High
User Mode
RECONFIG_N or
READY = Low
RECONFIG_N = High
READY = Low
ERROR
All configuration data received
RECONFIG_N Driven
Low or Device Refresh
RECONFIG_N Driven
Low or Device Refresh
RECONFIG_N Driven
Low or Device Refresh

4 Configuration Process
4.1 Power-up Sequence
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4.1 Power-up Sequence
During the power-on process, the power-on reset (POR) circuit inside
the FPGA becomes active. The actie POR circuit makes sure the external
I/O pins are in a high-impedance state and monitors the
VCC/VCCX/VCCOn input rails. When VCC/VCCX/VCCOn meets the
minimum reset voltage level (Voltage level may vary for different devices,
and different devices monitor different power rails.), POR circuit releases
an internal reset signal, allowing the FPGA to bigin its initialization process.
When READY and DONE are driven low, the FPGA moves to the
initialization state, as shown in Figure 5-2.
Figure 4-1 POR Power-up Timing
tINTL
VCC/VCCX/VCCOn
READY
DONE
Table 4-1 lists different power rails monitored by POR circuits of
different devices.
Table 4-1 Power Rails Monitored by POR Circuits of Different Devices
Series
Device
Power Rails
GW1N
GW1N-1
GW1N-4
GW1N-9
VCC/VCCX/VCCO1/VCCO3
GW1N-1P5
GW1N-2
VCC/VCCX/VCCO0
GW1N-1S
VCC/VCCX/VCCO0/VCCO2
GW1NZ
GW1NZ-1
VCC/VCCX/VCCO1/VCCO3
GW1NR
GW1NR-1
GW1NR-4
GW1NR-9
VCC/VCCX/VCCO1/VCCO3
GW1NS
GW1NS-4
GW1NS-4C
VCC/VCCX/VCCO0/VCCO1
GW1NSR
GW1NSR-4
GW1NSR-4C
VCC/VCCX/VCCO0/VCCO1
GW1NSE
GW1NSE-4C
VCC/VCCX/VCCO0/VCCO1
GW1NSER
GW1NSER-4C
VCC/VCCX/VCCO0/VCCO1
GW1NRF
GW1NRF-4B
VCC/VCCX/VCCO1/VCCO3
GW2A
GW2A-18
GW2A-55
VCC/VCCX/VCCO3
GW2AR
GW2AR-18
VCC/VCCX/VCCO3
GW2AN
GW2AN-9X
VCC/VCCX/VCCO1/VCCO5

4 Configuration Process
4.2 Initialization
UG290-2.5.2E
11(98)
Series
Device
Power Rails
GW2AN-18X
GW2AN-55
VCC/VCCX/VCCO3
GW2ANR
GW2ANR-18
VCC/VCCX/VCCO3
4.2 Initialization
After the power on reset circuit drives the READY and DONE status
pins low, the FPGAs enter the memory initialization immediately. The
purpose of the initialization is to clear all the SRAM memory inside the
FPGA.
The FPGA remains in the initialization state until all of the following
conditions are met:
The TINITL time period has elapsed.
The RECONFIG_N pin is high.
The READY pin is not driven low by an external driver.
The READY pin provides two functions during the initialization phase:
To indicate that the FPGA is currently clearing its configuration SRAM
To act as an input preventing the FPGA transition from the initialization
state to the configuration state when it’s driven low by an eternal driver.
4.3 Configuration
The rising edge of the READY pin causes the FPGA to enter the
configuration state. The internal configuration SRAM of FPGA can be
configured via multiple modes according to the MODE pin values. During
the time the FPGA receives its configuration data, the READY pin can
indicate its internal state. When READY is high, configuration proceeds
without issue. If READY is low, an error has occurred and the FPGA does
not operate.
4.4 Wake-up
When all the configuration data is reveived correctly, the FPGA enters
the wake-up state and set the internal status bit of DONE to 1. In the
wake-up state, the FPGA will perform the following operations in sequence:
1. Enable the Global output enable (GOE) signal, and then the FPGA I/O
exits a high-impedance state and take on its programmed function. The
input signals are prevented from performing any action on the FPGA
flip-flops by the assertion of the Global Set/Reset (GSR).
2. Release the Global Set/Reset (GSR) signal and the Global Write
Disable (GWDISn) signal. Enabling the Global Write Disable (GWDISn)
signalp revents the FPGA from mistakenly overwriting the initialization
data in the internal RAM.
3. Enable the external DONE pin. The external DONE is a bidirectional,
open-drain I/O when it’s enabled. Keep the FPGA wake-up by
externally driving the DONE pin low. When the DONE pin is driven high,
the FPGA wake-up pahse is complete and enters user mode.