GOWIN GW1NS Series User manual

GW1NS series of FPGA Products
Package & Pinout User Guide
UG823-1.7.2E, 06/30/2021

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, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
09/10/2018
1.0E
Initial version published (Preliminary).
11/22/2018
1.1E
Pins distribution view for different packages added.
01/10/2019
1.2E
Quantity of GW1NS-2/GW1NS-2C Pins updated;
Introduction to the I/O BANK updated.
04/03/2019
1.3E
CS36 package outline updated.
10/12/2019
1.4E
GW1NS-4 / GW1NS-4C added.
11/12/2019
1.5E
CS49 package info. added and CS49 POD added.
03/30/2020
1.6E
GW1NS-2/GW1NS-2C CS36U package info. added.
04/16/2020
1.6.1E
GW1NS-2C CS36U package info. removed;
The pins distribution view and pin number of
GW1NS-4/GW1NS-4C QN48 updated.
07/28/2020
1.7E
GW1NS-4/4C MG64 package info.Added.
11/25/2020
1.7.1E
CS49 package outline updated.
06/30/2021
1.7.2E
Section 2.4.1 and 3.1 updated.

Contents
UG823-1.7.2E
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Contents
Contents.................................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................2
1.4 Support and Feedback ....................................................................................................... 2
2Overview ........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................4
2.3 Power Pin ...........................................................................................................................4
2.4 Pin Quantity........................................................................................................................5
2.4.1 Quantity of GW1NS-2 / GW1NS-2C Pins........................................................................5
2.4.2 Quantity of GW1NS-4 / GW1NS-4C Pins........................................................................6
2.5 Pin Definitions.....................................................................................................................7
2.6 Introduction to the I/O BANK .............................................................................................. 9
3View of Pin Distribution.............................................................................. 11
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution ............................................................. 11
3.1.1 View of QN32 Pins Distribution ..................................................................................... 11
3.1.2 View of QN32U Pins Distribution...................................................................................12
3.1.3 View of CS36 Pins Distribution......................................................................................13
3.1.4 View of CS36U Pins Distribution................................................................................... 14
3.1.5 View of QN48 Pins Distribution .....................................................................................15
3.1.6 View of LQ144Pins Distribution.....................................................................................16
3.2 View of GW1NS-4/GW1NS-4C Pins Distribution ............................................................. 17
3.2.1 View of CS49 Pins Distribution......................................................................................17
3.2.2 View of QN48 Pins Distribution .....................................................................................18
3.2.3 View of MG64 Pins Distribution.....................................................................................19

Contents
UG823-1.7.2E
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4Package Diagrams ......................................................................................20
4.1 QN32 Package Outline (5mm x 5mm)..............................................................................20
4.2 QN32U Package Outline (5mm x 5mm)...........................................................................21
4.3 CS36 Package Outline (2.5mm x 2.5mm)........................................................................22
4.4 CS36U Package Outline (2.5mm x 2.5mm) .....................................................................23
4.5 CS49 Package Outline (2.9mm x 2.9mm)........................................................................24
4.6 QN48Package Outline (GW1NS-2 / GW1NS-2C, 6mm x 6mm)......................................25
4.7 QN48Package Outline (GW1NS-4 / GW1NS-4C, 6msm x 6mm)....................................26
4.8 LQ144 Package Outline (22mm x 22mm)........................................................................27
4.9 MG64 Package Outline (4.2mm x 4.2mm).......................................................................28

List of Figures
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List of Figures
Figure 2-1 GW1NS I/O Bank Distribution ..........................................................................................9
Figure 3-1 View of GW1NS-2/ GW1NS-2C QN32 Pins Distribution (Top View)................................ 11
Figure 3-2 View of GW1NS-2/GW1NS-2C QN32 Pins Distribution (Top View)................................. 12
Figure 3-3 View of GW1NS-2/GW1NS-2C CS36 Pin Distribution (Top View)...................................13
Figure 3-4 View of GW1NS-2 CS36U Pins Distribution (Top View)...................................................14
Figure 3-5 View of GW1NS-2/GW1NS-2C QN48 Pins Distribution (Top View)................................. 15
Figure 3-6 View of GW1NS-2/GW1NS-2C LQ144 Pins Distribution (Top View)............................... 16
Figure 3-7 View of GW1NS-4/ GW1NS-4C CS49 Pins Distribution (Top View)................................ 17
Figure 3-8 View of GW1NS-4/ GW1NS-4C QN48 Pins Distribution (Top View)................................18
Figure 3-9 View of GW1NS-4/ GW1NS-4C MG64 Pins Distribution (Top View)............................... 19
Figure 4-1 Package Outline QN32.....................................................................................................20
Figure 4-2 Package Outline QN32U.................................................................................................. 21
Figure 4-3 Package Outline CS36..................................................................................................... 22
Figure 4-4 Package Outline CS36U .................................................................................................. 23
Figure 4-5 Package Outline CS49.....................................................................................................24
Figure 4-6 Package Outline QN48 (GW1NS-2 / GW1NS-2C)...........................................................25
Figure 4-7 Package Outline QN48 (GW1NS-4 / GW1NS-4C)...........................................................26
Figure 4-8 LQ144 Package Outline ................................................................................................... 27
Figure 4-9 MG64 Package Outline ....................................................................................................28

List of Tables
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List of Tables
Table 1-1 Abbreviations and Terminology..........................................................................................2
Table 2-1 Package and Max. User I/O Information............................................................................4
Table 2-2 GW1NS Power Pin............................................................................................................. 4
Table 2-3 Quantity of GW1NS-2 / GW1NS-2C Pins........................................................................... 5
Table 2-4 Quantity of GW1NS-4 / GW1NS-4C Pins........................................................................... 6
Table 2-5 Definition of the Pins in the GW1NS series of FPGA products.......................................... 7
Table 3-1 Other Pins in GW1NS-2/GW1NS-2C QN32 ...................................................................... 11
Table 3-2 Other pins in GW1NS-2/GW1NS-2C QN32U.................................................................... 12
Table 3-3 Other pins in GW1NS-2/GW1NS-2C CS36....................................................................... 13
Table 3-4 Other pins in GW1NS-2 CS36U......................................................................................... 14
Table 3-5 Other pins in GW1NS-2/GW1NS-2C QN48.......................................................................15
Table 3-6 Other pins in GW1NS-2/GW1NS-2C LQ144 .....................................................................16
Table 3-7 Other pins in GW1NS-4/GW1NS-4C CS49....................................................................... 17
Table 3-8 Other pins in GW1NS-4/GW1NS-4C QN48.......................................................................18
Table 3-9 Other pins in GW1NS-4/GW1NS-4C MG64 ...................................................................... 19

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NS series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guides are available on GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS821, GW1NS series of FPGA Products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration
User Guide
3. UG823, GW1NS series of FPGA Products Package and Pinout
4. UG822, GW1NS-2 Pinout
5. UG825, GW1NS-2C Pinout
6. UG824, GW1NS-4&4C Pinout

1 About This Guide
1.3 Abbreviations and Terminology
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1.3 Abbreviations and Terminology
The abbreviations and terminologies used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Meaning
FPGA
Field Programmable GateArray
GPIO
Gowin Programmable IO
QN32
QFN32 package
QN32U
QFN32U package
CS36
WLCSP36 package
CS36U
WLCSP36U package
CS49
WLCSP49 package
QN48
QFN48 Package
LQ144
LQFP144 package
MG64
MBGA64
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided
below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
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2Overview
The GW1NS series of FPGA products are the first-generation
products in the LittleBee®family and include SoC FPtGA devices and
non-SoC FPGA devices. SoC FPFA is embedded with an ARM
Cortex-M3 hard core processor, while no ARM Cortex-M3 hard core
processor is included in the non-SoC FPGAdevices. In addition, the
GW1NS series of FPGA products are also embedded with USB2.0 PHY,
user flash, and ADC. When the ARM Cortex-M3 hard-core processor is
employed as the core, the needs of the Min. memory can be met. FPGA
logic resources and other embedded resources can flexibly facilitate the
peripheral control functions, which provide excellent calculation
functions and exceptional system response interrupts. They also offer
high performance, low power consumption, a small number of pins,
flexible usage, instant start-up, affordability, nonvolatile, high security,
and abundant package types, among other benefits. The GW1NS series
of SoC FPFAproducts achieve seamless connection between
programmable logic devices and embedded processors. They are
compatible with multiple peripheral device standards and can,
therefore, reduce costs of operation and be widely deployed in industrial
control, communication, Internet of Things, servo drive, consumption
fields, etc.
2.1 PB-Free Package
The GW1NS series of FPGA products are PB free in line with the
EU ROHS environmental directives. The substances used in the
GW1NS series of FPGAproducts are in full compliance with the
IPC-1752 standards.