GOWIN GW1NS Series User manual

GW1NS series of FPGA Products
Package & Pinout User Guide
UG823-1.7.2E, 06/30/2021

Copyright©2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin
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Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
09/10/2018
1.0E
Initial version published (Preliminary).
11/22/2018
1.1E
Pins distribution view for different packages added.
01/10/2019
1.2E
Quantity of GW1NS-2/GW1NS-2C Pins updated;
Introduction to the I/O BANK updated.
04/03/2019
1.3E
CS36 package outline updated.
10/12/2019
1.4E
GW1NS-4 / GW1NS-4C added.
11/12/2019
1.5E
CS49 package info. added and CS49 POD added.
03/30/2020
1.6E
GW1NS-2/GW1NS-2C CS36U package info. added.
04/16/2020
1.6.1E
GW1NS-2C CS36U package info. removed;
The pins distribution view and pin number of
GW1NS-4/GW1NS-4C QN48 updated.
07/28/2020
1.7E
GW1NS-4/4C MG64 package info.Added.
11/25/2020
1.7.1E
CS49 package outline updated.
06/30/2021
1.7.2E
Section 2.4.1 and 3.1 updated.

Contents
UG823-1.7.2E
i
Contents
Contents.................................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................2
1.4 Support and Feedback ....................................................................................................... 2
2Overview ........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................4
2.3 Power Pin ...........................................................................................................................4
2.4 Pin Quantity........................................................................................................................5
2.4.1 Quantity of GW1NS-2 / GW1NS-2C Pins........................................................................5
2.4.2 Quantity of GW1NS-4 / GW1NS-4C Pins........................................................................6
2.5 Pin Definitions.....................................................................................................................7
2.6 Introduction to the I/O BANK .............................................................................................. 9
3View of Pin Distribution.............................................................................. 11
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution ............................................................. 11
3.1.1 View of QN32 Pins Distribution ..................................................................................... 11
3.1.2 View of QN32U Pins Distribution...................................................................................12
3.1.3 View of CS36 Pins Distribution......................................................................................13
3.1.4 View of CS36U Pins Distribution................................................................................... 14
3.1.5 View of QN48 Pins Distribution .....................................................................................15
3.1.6 View of LQ144Pins Distribution.....................................................................................16
3.2 View of GW1NS-4/GW1NS-4C Pins Distribution ............................................................. 17
3.2.1 View of CS49 Pins Distribution......................................................................................17
3.2.2 View of QN48 Pins Distribution .....................................................................................18
3.2.3 View of MG64 Pins Distribution.....................................................................................19

Contents
UG823-1.7.2E
ii
4Package Diagrams ......................................................................................20
4.1 QN32 Package Outline (5mm x 5mm)..............................................................................20
4.2 QN32U Package Outline (5mm x 5mm)...........................................................................21
4.3 CS36 Package Outline (2.5mm x 2.5mm)........................................................................22
4.4 CS36U Package Outline (2.5mm x 2.5mm) .....................................................................23
4.5 CS49 Package Outline (2.9mm x 2.9mm)........................................................................24
4.6 QN48Package Outline (GW1NS-2 / GW1NS-2C, 6mm x 6mm)......................................25
4.7 QN48Package Outline (GW1NS-4 / GW1NS-4C, 6msm x 6mm)....................................26
4.8 LQ144 Package Outline (22mm x 22mm)........................................................................27
4.9 MG64 Package Outline (4.2mm x 4.2mm).......................................................................28

List of Figures
UG823-1.7.2E
iii
List of Figures
Figure 2-1 GW1NS I/O Bank Distribution ..........................................................................................9
Figure 3-1 View of GW1NS-2/ GW1NS-2C QN32 Pins Distribution (Top View)................................ 11
Figure 3-2 View of GW1NS-2/GW1NS-2C QN32 Pins Distribution (Top View)................................. 12
Figure 3-3 View of GW1NS-2/GW1NS-2C CS36 Pin Distribution (Top View)...................................13
Figure 3-4 View of GW1NS-2 CS36U Pins Distribution (Top View)...................................................14
Figure 3-5 View of GW1NS-2/GW1NS-2C QN48 Pins Distribution (Top View)................................. 15
Figure 3-6 View of GW1NS-2/GW1NS-2C LQ144 Pins Distribution (Top View)............................... 16
Figure 3-7 View of GW1NS-4/ GW1NS-4C CS49 Pins Distribution (Top View)................................ 17
Figure 3-8 View of GW1NS-4/ GW1NS-4C QN48 Pins Distribution (Top View)................................18
Figure 3-9 View of GW1NS-4/ GW1NS-4C MG64 Pins Distribution (Top View)............................... 19
Figure 4-1 Package Outline QN32.....................................................................................................20
Figure 4-2 Package Outline QN32U.................................................................................................. 21
Figure 4-3 Package Outline CS36..................................................................................................... 22
Figure 4-4 Package Outline CS36U .................................................................................................. 23
Figure 4-5 Package Outline CS49.....................................................................................................24
Figure 4-6 Package Outline QN48 (GW1NS-2 / GW1NS-2C)...........................................................25
Figure 4-7 Package Outline QN48 (GW1NS-4 / GW1NS-4C)...........................................................26
Figure 4-8 LQ144 Package Outline ................................................................................................... 27
Figure 4-9 MG64 Package Outline ....................................................................................................28

List of Tables
UG823-1.7.2E
iv
List of Tables
Table 1-1 Abbreviations and Terminology..........................................................................................2
Table 2-1 Package and Max. User I/O Information............................................................................4
Table 2-2 GW1NS Power Pin............................................................................................................. 4
Table 2-3 Quantity of GW1NS-2 / GW1NS-2C Pins........................................................................... 5
Table 2-4 Quantity of GW1NS-4 / GW1NS-4C Pins........................................................................... 6
Table 2-5 Definition of the Pins in the GW1NS series of FPGA products.......................................... 7
Table 3-1 Other Pins in GW1NS-2/GW1NS-2C QN32 ...................................................................... 11
Table 3-2 Other pins in GW1NS-2/GW1NS-2C QN32U.................................................................... 12
Table 3-3 Other pins in GW1NS-2/GW1NS-2C CS36....................................................................... 13
Table 3-4 Other pins in GW1NS-2 CS36U......................................................................................... 14
Table 3-5 Other pins in GW1NS-2/GW1NS-2C QN48.......................................................................15
Table 3-6 Other pins in GW1NS-2/GW1NS-2C LQ144 .....................................................................16
Table 3-7 Other pins in GW1NS-4/GW1NS-4C CS49....................................................................... 17
Table 3-8 Other pins in GW1NS-4/GW1NS-4C QN48.......................................................................18
Table 3-9 Other pins in GW1NS-4/GW1NS-4C MG64 ...................................................................... 19

1 About This Guide
1.1 Purpose
UG823-1.7.2E
1(28)
1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NS series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guides are available on GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
1. DS821, GW1NS series of FPGA Products Data Sheet
2. UG290, Gowin FPGA Products Programming and Configuration
User Guide
3. UG823, GW1NS series of FPGA Products Package and Pinout
4. UG822, GW1NS-2 Pinout
5. UG825, GW1NS-2C Pinout
6. UG824, GW1NS-4&4C Pinout

1 About This Guide
1.3 Abbreviations and Terminology
UG823-1.7.2E
2(28)
1.3 Abbreviations and Terminology
The abbreviations and terminologies used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Meaning
FPGA
Field Programmable GateArray
GPIO
Gowin Programmable IO
QN32
QFN32 package
QN32U
QFN32U package
CS36
WLCSP36 package
CS36U
WLCSP36U package
CS49
WLCSP49 package
QN48
QFN48 Package
LQ144
LQFP144 package
MG64
MBGA64
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided
below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG823-1.7.2E
3(28)
2Overview
The GW1NS series of FPGA products are the first-generation
products in the LittleBee®family and include SoC FPtGA devices and
non-SoC FPGA devices. SoC FPFA is embedded with an ARM
Cortex-M3 hard core processor, while no ARM Cortex-M3 hard core
processor is included in the non-SoC FPGAdevices. In addition, the
GW1NS series of FPGA products are also embedded with USB2.0 PHY,
user flash, and ADC. When the ARM Cortex-M3 hard-core processor is
employed as the core, the needs of the Min. memory can be met. FPGA
logic resources and other embedded resources can flexibly facilitate the
peripheral control functions, which provide excellent calculation
functions and exceptional system response interrupts. They also offer
high performance, low power consumption, a small number of pins,
flexible usage, instant start-up, affordability, nonvolatile, high security,
and abundant package types, among other benefits. The GW1NS series
of SoC FPFAproducts achieve seamless connection between
programmable logic devices and embedded processors. They are
compatible with multiple peripheral device standards and can,
therefore, reduce costs of operation and be widely deployed in industrial
control, communication, Internet of Things, servo drive, consumption
fields, etc.
2.1 PB-Free Package
The GW1NS series of FPGA products are PB free in line with the
EU ROHS environmental directives. The substances used in the
GW1NS series of FPGAproducts are in full compliance with the
IPC-1752 standards.

2 Overview
2.2 Package and Max. User I/O Information
UG823-1.7.2E
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2.2 Package and Max. User I/O Information
Table 2-1 Package and Max. User I/O Information
Package
Pitch(mm)
Size(mm)
GW1NS-2
GW1NS-2C
GW1NS-4/GW1NS-4C
QN32
0.5
5 x 5
25(4)
25(4)
–
QN32U
0.5
5 x 5
16(2)
16(2)
–
CS36
0.4
2.5 x 2.5
30(6)
30(6)
–
CS36U
0.4
2.5 x 2.5
22(5)
–
-
QN48
0.4
6 x 6
38(7)
38(7)
38(4)
CS49
0.4
2.9 x 2.9
–
–
42(8)
MG64
0.5
4.2 x 4.2
-
-
57(8)
LQ144
0.5
20 x 20
95(12)
95(12)
–
Note!
In this manual, abbreviations are employed to refer to the package types. See 1.3
Abbreviations and Terminology.
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data
in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are
used as I/O. When mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK,
TDI, TDO, and TMS) can be used as GPIO simultaneously, and the Max. user I/O
plus one.
2.3 Power Pin
Table 2-2 GW1NS Power Pin
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCX
VSS
NC
VCCPLL
VCCP

2 Overview
2.4 Pin Quantity
UG823-1.7.2E
5(28)
2.4 Pin Quantity
2.4.1 Quantity of GW1NS-2 / GW1NS-2C Pins
Table 2-3 Quantity of GW1NS-2 / GW1NS-2C Pins
Pin Type
GW1NS-2/GW1NS-2C
QN32
QN32U
CS36
CS36U
(GW1NS-2)
QN48
LQ144
I/O Single
end/Differential pair
/LVDS[1]
BANK0
4/1/0
3/0/0
10/5/0
6/3/0
11/5/0
32/14/0
BANK1
9/4/2
2/1/0
5/2/1
4/2/1
9/4/2
16/8/3
BANK2
3/1/1
2/1/1
10/5/5
8/4/4
11/5/4
26/13/6
BANK3
9/4/1
9/3/1
5/2/0
4/1/0
7/2/1
21/9/3
Max. User I/O[2]
25
16
30
22
38
95
Differential Pair
10
5
14
10
16
44
True LVDS Output
4
2
6
5
7
12
VCCO0
1
0
0
0
0
0
VCCO1
0
0
0
0
1
1
VCCO2
1
1
1
1
1
2
VCCO3
0
1
0
1
0
2
VCC/VCCPLL[3]
2
0
1
0
2
0
VCCO1/VCCO3/VCCP/VCCX
2
0
0
0
0
0
VCCO1/VCCX/VDDAUSB/VDDDU
SB
0
0
0
1
0
0
VBUSPAD/VCCO1/VCCX/VDDAU
SB/VDDDUSB
0
2
0
0
0
0
VCC/VCCPLL/VDDPL
0
3
0
1
0
4
VCCO0/VDDA
0
2
1
1
0
3
VCCO1/VCCO3
0
0
1
0
0
0
VCCP/VCCX
0
0
1
0
2
0
VCCO0/VCCO3/VDDA
0
0
0
0
1
0
VCCX/VDDAUSB
0
0
0
0
0
3
VSS
1
1
1
0
2
10
VSS/AGND
0
0
0
1
0
0
MODE0
1
0
0
0
0
1
MODE1
0
0
0
0
0
1
MODE2
0
0
0
0
1
1
JTAGSEL_N
0
0
0
1
1
1
NC
0
0
0
0
0
15
Note!
[1]Single end/ Differential I/O quantity include CLK pins, and download pins;

2 Overview
2.4 Pin Quantity
UG823-1.7.2E
6(28)
[2]The max. user I/O excludes dedicated MODE pins. The JTAGSEL_N and JTAG
pins cannot be used as I/O simultaneously. The data in this table is when the
loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O.
[3]Pin multiplexing.
2.4.2 Quantity of GW1NS-4 / GW1NS-4C Pins
Table 2-4 Quantity of GW1NS-4 / GW1NS-4C Pins
Pin Type
GW1NS-4/GW1NS-4C
CS49
QN48
MG64
I/O Single end/Differential
pair/LVDS1
BANK0
8/3/0
8/3/0
9/3/0
BANK1
18/9/0
10/5/0
28/14/0
BANK2
16/8/8
9/4/4
18/9/9
BANK3
0/0/0
11/5/0
0/0/0
Max. User I/O2
42
38
56
Differential Pair
20
17
26
True LVDS output
8
4
9
VCC
1
2
1
VCCX
1
1
1
VCCO0
0
1
1
VCCO1
1
1
1
VCCO2
1
1
1
VCCO3
0
2
1
VCCO0/VCCO33
1
0
0
VSS
2
1
2
MODE0
0
0
0
MODE1
0
1
0
MODE2
0
0
0
JTAGSEL_N
0
1
1
NC
0
0
0
Note!
[1]Single end/ Differential I/O quantity include CLK pins, and download pins;
[2]The max. user I/O excludes dedicated MODE pins. The JTAGSEL_N and JTAG
pins cannot be used as I/O simultaneously. The data in this table is when the
loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as I/O.
[3]Pin multiplexing.

2 Overview
2.5 Pin Definitions
UG823-1.7.2E
7(28)
2.5 Pin Definitions
The location of the pins in the GW1NS series of FPGA products
varies according to the different packages.
Table 2-5 provides a detailed overview of user I/O, multi-function
pins, dedicated pins, and other pins.
Table 2-5 Definition of the Pins in the GW1NS series of FPGA products
Pin Name
I/O
Description
User I/O Pins
IO[End][Row/Column
Number][A/B]
I/O
[End] indicates the pin location, including L(left)
R(right) B(bottom), and T(top)
[Row/Column Number] indicates the pin
Row/Column number.If [End] is T(top) or
B(bottom), the pin indicates the column number of
the corresponding CFU. If [End] is L(left) or
R(right), the pin indicates the Row number of the
corresponding CFU.
[A/B] indicates differential signal pair information.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the other
functions in addition to being general purpose user
I/O. These pins can be used as user I/O when the
functions are not used.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when low pulse
READY
I/O
When high level, the device can be programmed
and configured
When low level, the device cannot be programmed
and configured
DONE
I/O
High level indicates successful program and
configure
Low level indicates incomplete or failed to program
and configure
FASTRD_N /D3
I/O
In MSPI mode, FASTRD_N is used as Flash
access speed port. Low indicates high-speed Flash
access mode; high indicates regular Flash access
mode.
Data port D3 in CPU mode
MCLK /D4
I/O
Clock output MCLK in MSPI mode
Data port D4 in CPU mode
MCS_N /D5
I/O
Enable signal MCS_N in MSPI mode, active-low
Data port D5 in CPU mode
MI /D7
I/O
MISO in MSPI mode: Master data input/Slave data
output
Data port D7 in CPU mode
MO /D6
I/O
MISO in MSPI mode: Master data output/Slave
data input
Data port D6 in CPU mode
SSPI_CS_N/D0
I/O
Enable signal SSPI_CS_N in SSPI mod,
active-low, Internal Weak Pull Up
Data port D0 in CPU mode
SO /D1
I/O
MISO in MSPI mode: Master data input/Slave data
output

2 Overview
2.5 Pin Definitions
UG823-1.7.2E
8(28)
Pin Name
I/O
Description
Data port D1 in CPU mode
SI /D2
I/O
MISO in MSPI mode: Master data output/Slave
data input
Data port D2 in CPU mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK
I
Serial clock input in JTAG mode, which needs to be
connected with 4.7 K drop-down resistance on
PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO
O
Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK
I
Clock input in SSPI, SERIAL, and CPU mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT
O
Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected internally in
SSPI mode or CPU mode
Low level, SCLK will be disconnected from SSPI
mode or CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU mode
GCLKT_[x]
I
Pins in global clock input, T(True), [x]: global clock
No.
GCLKC_[x]
I
Differential comparison input pin of GCLKT_[x],
C(Comp), [x]: global clock No.[1].
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True)
LPLL_C_fb/RPLL_C_fb
I
L/R PLL feedback input pin, C(Comp)
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp)
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is
not bonded, it's internal grounded.
Other Pins
NC
NA
Reserved.
VSS
NA
Ground pins
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of I/O
BANK#.
VCCX
NA
Power supply pins of auxiliary voltage.
VCCP
NA
FLASH Power supply pin (1.8V)
VCCPLL
NA
Power supply pins of PLL
USB Power supply pin
DM
NA
USB data pin Data-

2 Overview
2.6 Introduction to the I/O BANK
UG823-1.7.2E
9(28)
Pin Name
I/O
Description
DP
NA
USB data pin Data+
REXT
NA
12.7K high-accuracy resistance
XIN
NA
Crystal input signals
XOUT
NA
Crystal oscillator signals
IDPAD
NA
ID signal
VBUSPAD
NA
VBUS signal
VDDA
NA
Analog power supply voltage, VDDA=3.3V
VDDAUSB
NA
Analog power supply pin (3.3V)
VDDDUSB
NA
Analog power supply pin (3.3V)
VDDPL
NA
Power supply pin for driver (1.2V)
Note！
[1]When the input is single-ended, the GLKC_[x] pin is not a global clock pin.
2.6 Introduction to the I/O BANK
There are four I/O Banks in the GW1NS series of FPGA products,
as shown in Figure 2-1.
Figure 2-1 GW1NS I/O Bank Distribution
GW1NS
I/O BANK0
I/O BANK2
I/O BANK1 I/O BANK3
This manual provides an overview of the distribution view of the
pins in the GW1NS series of FPGA products. The four I/O Banks of the
GW1NS series of FPGA products are marked with four different colors.
User I/O, power, and ground are also marked with different symbols
and colors. The various symbols and colors used for the various pins are
defined as follows:
“ ” denotes I/Os in BANK0.
” ” denotes I/Os in BANK1.
” ” denotes I/Os in BANK2.
” ” denotes I/Os in BANK3.
” ” denotes VCC, VCCX, and VCCO.

2 Overview
2.6 Introduction to the I/O BANK
UG823-1.7.2E
10(28)
” ” denotes VCC. The filling color does not change.
” ” denotes VSS. The filling color does not change.
” ” denotes NC.

3 View of Pin Distribution
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution
UG823-1.7.2E
11(28)
3View of Pin Distribution
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution
3.1.1 View of QN32 Pins Distribution
Figure 3-1 View of GW1NS-2/ GW1NS-2C QN32 Pins Distribution (Top View)
Table 3-1 Other Pins in GW1NS-2/GW1NS-2C QN32
VCCO0
19
VCCO2
6
VCC/VCCPLL
2, 18
VCCO1/VCCO3/VCC
P/VCCX
15, 31
VSS
3

3 View of Pin Distribution
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution
UG823-1.7.2E
12(28)
3.1.2 View of QN32U Pins Distribution
Figure 3-2 View of GW1NS-2/GW1NS-2C QN32 Pins Distribution (Top View)
Table 3-2 Other pins in GW1NS-2/GW1NS-2C QN32U
VCCO0/VDDA
19, 23
VCCO2
6
VCCO3
31
VCC/VDDPL/VCCPLL
2, 18, 7
VBUSPAD/VCCO1/VCCX/VDDAUSB/
VDDDUSB
11, 15
VSS
3

3 View of Pin Distribution
3.1 View of GW1NS-2/GW1NS-2C Pins Distribution
UG823-1.7.2E
13(28)
3.1.3 View of CS36 Pins Distribution
Figure 3-3 View of GW1NS-2/GW1NS-2C CS36 Pin Distribution (Top View)
Table 3-3 Other pins in GW1NS-2/GW1NS-2C CS36
VCCO1/VCCO3
C4
VCCO2
F1
VCCX/VCCP
D3
VCC/VCCPLL
D4
VSS
C3
VDDA/VCCO0
A6