GOWIN DK-START-GW1NR9 User manual

DK-START-GW1NR9 V1.1
User Guide
DBUG361-1.3E, 2021/08/20

Copyright © 2021 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, Gowin, and GOWINSEMI are trademarks of Guangdong Gowin Semiconductor
Corporation and are registered in China, the U.S. Patent and Trademark Office, and other
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or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. All information in this document should be
treated as preliminary. GOWINSEMI may make changes to this document at any time
without prior notice. Anyone relying on this documentation should contact GOWINSEMI for
the current documentation and errata.

Revision History
Date
Version
Description
03/19/2019
1.0E
Initial version published.
11/29/2019
1.1E
MIPI input function removed.
12/19/2019
1.2E
The version of DK-START-GW1NR9 added.
08/20/2021
1.3E
The Quick Start in 2.2 A Development Board Suite removed;
The Chapter 6 Quick Start added.

Contents
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Contents
Contents ...............................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1About This Guide ..........................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................1
1.3 Terminology and Abbreviations...........................................................................................1
1.4 Support and Feedback ....................................................................................................... 2
2Development Board Introduction.................................................................3
2.1 Overview.............................................................................................................................3
2.2 A Development Board Suite................................................................................................ 4
2.3 PCB Components ............................................................................................................... 5
2.4 System Diagram .................................................................................................................5
2.5 Feature ............................................................................................................................... 6
2.6 Development Board Specification ......................................................................................7
3Development Board Circuit ..........................................................................9
3.1 FPGA Module ..................................................................................................................... 9
3.1.1 Overview..........................................................................................................................9
3.1.2 I/O BANK Introduction ..................................................................................................... 9
3.2 Download.......................................................................................................................... 11
3.2.1 Overview........................................................................................................................ 11
3.2.2 USB Download Circuit ................................................................................................... 11
3.2.3 Download Flow ..............................................................................................................12
3.2.4 Pinout.............................................................................................................................12
3.3 Power Supply....................................................................................................................12
3.3.1 Overview........................................................................................................................12
3.3.2 Power System Distribution ............................................................................................12

Contents
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3.3.3 Pinout.............................................................................................................................13
3.4 Clock, Reset .....................................................................................................................14
3.4.1 Overview........................................................................................................................14
3.4.2 Clock, Reset .................................................................................................................. 14
3.4.3 Pinout.............................................................................................................................14
3.5 LED ...................................................................................................................................14
3.5.1 Overview........................................................................................................................14
3.5.2 LED Circuit.....................................................................................................................15
3.5.3 Pinout.............................................................................................................................15
3.6 Switches ...........................................................................................................................15
3.6.1 Overview........................................................................................................................15
3.6.2 Switch Circuit .................................................................................................................15
3.6.3 Pinout.............................................................................................................................16
3.7 Key....................................................................................................................................16
3.7.1 Overview........................................................................................................................16
3.7.2 Key Circuit .....................................................................................................................16
3.7.3 Pinout.............................................................................................................................16
3.8 GPIO .................................................................................................................................17
3.8.1 Overview........................................................................................................................17
3.8.2 GPIO Circuit...................................................................................................................17
3.8.3 Pinout.............................................................................................................................18
3.9 MIPI/LVDS ........................................................................................................................20
3.9.1 Overview........................................................................................................................20
3.9.2 MIPI/LVDS Circuit ..........................................................................................................20
3.9.3 Pinout.............................................................................................................................21
4Considerations ............................................................................................25
5Gowin Software ...........................................................................................26
6Quick Start ...................................................................................................27

List of Figures
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List of Figures
Figure 2-1 DK-START-GW1NR9 V1.1 Development Board.............................................................. 3
Figure 2-2 A Development Board Suite11..........................................................................................4
Figure 2-3 PCB Components............................................................................................................. 5
Figure 2-4 System Diagram ...............................................................................................................5
Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution ..................................................... 10
Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View) ................................................... 10
Figure 3-3 Connection Diagram for FPGA USB Download ............................................................... 11
Figure 3-4 Power System Distribution ............................................................................................... 13
Figure 3-5 Clock, Reset ..................................................................................................................... 14
Figure 3-6 LED Circuit .......................................................................................................................15
Figure 3-7 Switch Circuit.................................................................................................................... 15
Figure 3-8 Key Circuit Diagram.......................................................................................................... 16
Figure 3-9 GPIO Circuit .....................................................................................................................17
Figure 3-10 LVDS Circuit ................................................................................................................... 20

List of Tables
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List of Tables
Table 1-1 Abbreviation and Terminology............................................................................................2
Table 2-1 Development Board Specification......................................................................................7
Table 3-1 GW1NR-9 FPGA Resources List .......................................................................................9
Table 3-2 FPGA I/O Pinout.................................................................................................................11
Table 3-3 FPGA Download Pinout .....................................................................................................12
Table 3-4 FPGA Power Pinout ...........................................................................................................13
Table 3-5 FPGA Clock and Reset Pinout...........................................................................................14
Table 3-6 LED Pinout ......................................................................................................................... 15
Table 3-7 Switch Circuit Pinout ..........................................................................................................16
Table 3-8 Key Circuit Pinout............................................................................................................... 16
Table 3-9 J14 GPIO Pinout ................................................................................................................ 18
Table 3-10 J13 GPIO Pinout .............................................................................................................. 18
Table 3-11 J15 FPGA Pinout (IDES16:1 Supported) .........................................................................21
Table 3-12 J17 FPGA Pinout.............................................................................................................. 22
Table 3-13 J16 FPGA Pinout (IDES16:1 Supported) .........................................................................23
Table 3-14 J18 FPGA Pinout (IDES16:1 Supported).........................................................................24

1 About This Guide
1.1 Purpose
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1About This Guide
1.1 Purpose
The DK-START-GW1NR9 V1.1 user manual consists of the following
four parts:
1. A brief introduction to the features and hardware resources of the
development board;
2. An introduction to the function, circuit, and pin distribution of each
module;
3. Considerations for the use of the development board;
4. An introduction to the usage of the FPGA development software.
1.2 Related Documents
The user manuals are available on the GOWINSEMI Website. You can
find the related documents at www.gowinsemi.com
1. DS117, GW1NR Series FPGA Products Data Sheet
2. UG119, GW1NR Series of FPGA Products Package and Pinout Manual
3. UG801, GW1NR-9 Devices Pinout Manual
4. UG290, Gowin FPGA Products Programming and Configuration
Manual
5. SUG100, Gowin Software User Guide
1.3 Terminology and Abbreviations
The terminology and abbreviations used in this manual are as shown
in Table 1-1 below.

1 About This Guide
1.4 Support and Feedback
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Table 1-1 Abbreviation and Terminology
Terminology and Abbreviation
Meaning
FPGA
Field Programmable Gate Array
SIP
System in Package
SDRAM
Synchronous Dynamic RAM
PSRAM
Pseudo static random access memory
CFU
Configurable Function Unit
CLS
Configurable Logic Slice
CRU
Configurable Routing Unit
LUT4
Four-input Look-up Table
LUT5
Five-input Look-up Table
LUT6
Six-input Look-up Table
LUT7
Seven-input Look-up Table
LUT8
Eight-input Look-up Table
REG
Register
ALU
Arithmetic Logic Unit
IOB
Input/Output Block
S-SRAM
Shadow SRAM
B-SRAM
Block Static Random Access Memory
SP
Single Port
SDP
Semi Dual Port
DP
Dual Port
DSP
Digital Signal Processing
DQCE
Dynamic Quadrant Clock Enable
DCS
Dynamic Clock Selector
PLL
Phase-locked Loop
DLL
Delay-locked Loop
LQ144
LQFP144 package
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Development Board Introduction
2.1 Overview
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2Development Board Introduction
2.1 Overview
Figure 2-1 DK-START-GW1NR9 V1.1 Development Board
The development board adopts the GW1NR-9 device, which is
embedded with PSRAM of 64Mbit, user flash memory and other resources.
The GW1NR series of FPGA products are the first generation of the Gowin
LittleBee® family and it is a SIP chip. Based on GW1N, GW1NR series
integrates abundant PSRAM. At the same time, it has the characteristics of
low power consumption, instant-start, low cost, non-volatility, high security,
rich packages, convenient and flexible usage, etc., which can effectively
reduce the learning cost and help users quickly enter the design and
development field of programmable logic devices.
The development board offers abundant external interfaces, including
MIPI/LVDS interfaces, GPIO interfaces, etc. There are also sliding switch,
button switch, LED, clock, reset and other resources for developers or fans
to learn to use.

2 Development Board Introduction
2.2 A Development Board Suite
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2.2 A Development Board Suite
A development board suite includes the following items:
DK-START-GW1NR9 V1.1 Development Board
USB Cable
Figure 2-2 A Development Board Suite11
1
2
①DK-START-GW1NR9 V1.1
Development Board
②USB Cable

2 Development Board Introduction
2.3 PCB Components
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2.3 PCB Components
Figure 2-3 PCB Components
GPIO
1.2V 3.3V
OSC
LED
Reset
FPGA
Download
5V IN
FPGA
1.8V
LVDS
LVDS2.5V
LVDS
LVDS
GPIO
Switch
Key
2.4 System Diagram
Figure 2-4 System Diagram
4*LED4*SWITCH
OSC
50MHz
10Pairs
LVDS/MIPI
INPUT
4*BUTTON
10Pairs
LVDS/MIPI
OUTPUT
20PIN
GPIO
FPGA
Mini USB Interface
40PIN
GPIO
GW1NR9_V1.1
5V LDO
1.2V/1.8V/2.5V/3.3V

2 Development Board Introduction
2.5 Feature
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2.5 Feature
The structure and feature of the development board are as follows:
1. FPGA
LQFP144 package
Up to 120 user I/O
Embedded flash, data not easily lost if power down
Abundant LUT4 resources
Multiple modes and capacities of B-SRAM
2. FPGA Configuration Mode
JTAG
AUTO BOOT
3. Clock resource
50MHz Clock Crystal Oscillator
4. Key switch and slide switch
One reset button
Four key switches
Four Slide switch
5. LED
One power indicator (green)
One DONE indicator (green)
Four LEDs (green)
6. Memory
1Mbit embedded Flash
64Mbit embedded PSRAM
7. MIPI/LVDS
10 pairs of LVDS differential input
10 pairs of MIPI/LVDS differential output
8. GPIO
55 I/O extended resources
9. LDO Power
3.3 V, 2.5V, 1.8V, and1.2V supported

2 Development Board Introduction
2.6 Development Board Specification
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2.6 Development Board Specification
Table 2-1 Development Board Specification
No.
Item
Functional Description
Technical Condition
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, AUTOBOOT
USB to JTAG chip
integrated on board
–
3
Power
Supply
3.3 V, 2.5V and 1.2 V
output via LDO circuit
Input power: 5V
Provide power for
FPGA, download circuit
and other circuits via
5V–3.3V circuit;
Provide power for
FPGA via 5V to 2.5V
circuit;
Provide power for
FPGA via 5V–1.2V
circuit.
–
4
Slide
Switches
Available for testing
4
–
5
Key
Switches
Available for testing
4
–
6
Reset button
Reset for FPGA
1
–
7
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicators,
green
One DONE indicator,
green
One Power indicator,
green
–
8
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
9
Memory
Provides abundant
Flash and PSRAM for
design
1Mbit embedded Flash
64Mbit embedded
PSRAM
–
10
GPIO
I/O, convenient for user
extension and test
36
–
11
MIPI/LVDS
MIPI/LVDS, used for
testing
10 pairs of input
10 pairs of output
–
12
Protection
USB interface: ESD
protection;
Power interface:
Inverse current and
USB interface ESD
protection: ±15kV
non-contact discharge,
± 8kV contact
–

2 Development Board Introduction
2.6 Development Board Specification
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No.
Item
Functional Description
Technical Condition
Note
over current protection
discharge;
Schottky diode is
connected between
positive and negative
anodes of power
interface;
2A self-recovery fuses
are connected at power
inlet
13
Voltage
–
Input Voltage: 5V
–
14
Humidity
–
95%
–
15
Temperature
–
Operating range: –20°~70°
–

3 Development Board Circuit
3.1 FPGA Module
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3Development Board Circuit
3.1 FPGA Module
3.1.1 Overview
The resources of GW1NR series of FPGA products are shown in Table
3-1.
Table 3-1 GW1NR-9 FPGA Resources List
Device
GW1NR-9
LUT4
8,640
Flip-Flop (FF)
6,480
Shadow SRAM
S-SRAM (bits)
17,280
Block Static Random Access Memory
B-SRAM (bits)
468K
B-SRAM quantity
B-SRAM
26
User Flash (bits)
608K
PSRAM(bits)
64M
18 x 18 Multiplier
20
PLLs+DLLs
2+4
Total number of I/O banks
4
Max. user I/O1
120
Core Voltage (LV)
1.2V
Note!
See DS117, GW1NR series of FPGA Products Data Sheet for further details.
3.1.2 I/O BANK Introduction
There are four I/O Banks in the GW1NR series of FPGA products, as
shown in Figure 3-1.

3 Development Board Circuit
3.1 FPGA Module
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Figure 3-1 GW1NR series FPGA Products I/O Bank Distribution
GW1NR
I/O BANK0
I/O BANK2
I/O BANK1
I/O BANK3
Figure 3-2 GW1N-9 LQ144 Package Pins Distribution (Top View)

3 Development Board Circuit
3.2 Download
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Table 3-2 FPGA I/O Pinout
I/O BANK No.
Modules Connected
I/O BANK0
Pins selection for download mode
LVDS differential input
GPIO
I/O BANK1
GPIO
50MHz clock input
LED
Slide Switches
Key Switches
Reset
I/O BANK2
MIPI/LVDS differential output
GPIO
I/O BANK3
GPIO Interface
JTAG download
3.2 Download
3.2.1 Overview
The development board provides an USB download interface. The
data stream file can be download to the internal SRAM, or internal flash as
needed.
Note!
When downloaded to SRAM, the data stream file will be lost if the device is powered
down, and it will need to be downloaded again after power-on.
If downloaded to flash, the data stream file will not be lost if the device is powered
down.
3.2.2 USB Download Circuit
Figure 3-3 Connection Diagram for FPGA USB Download
TMS_FTDI
TCK_FTDI
TDI_FTDI
TDO_FTDI
USB to JTAG
Chip
USB_D+
USB_D- 14
13
16
18
U1
U17
GW1NR9_V1.1

3 Development Board Circuit
3.3 Power Supply
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3.2.3 Download Flow
Please plug USB download cable into the USB interface (J6) of the
development board to download FPGA, and then open Programmer, click
SRAM mode or Embedded flash mode to download bit stream file to SRAM
or flash.
3.2.4 Pinout
Table 3-3 FPGA Download Pinout
Signal Name
Pin No.
BANK
Description
I/O Level
TMS_FTDI
13
3
JTAG Signal
1.8V
TCK_ FTDI
14
3
JTAG Signal
1.8V
TDI_ FTDI
16
3
JTAG Signal
1.8V
TDO_ FTDI
18
3
JTAG Signal
1.8V
MODE0
144
0
Mode selection pin
2.5V
MODE1
143
0
Mode selection pin
2.5V
RECONFIG_N
20
3
RECONFIG_N
1.8V
DONE
21
3
One DONE indicator
1.8V
READY
22
3
READY
1.8V
3.3 Power Supply
3.3.1 Overview
DC5V is input by USB interface. The TI LDO power supply chip is used
to step down voltage from 5V to 3.3V, 2.5V, 1.8V and 1.2V, which can meet
the power demand of the development board.
3.3.2 Power System Distribution

3 Development Board Circuit
3.3 Power Supply
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Figure 3-4 Power System Distribution
USB Interface
DC5V Input
TPS7A7001
LDO
1.2V
TPS7A7001
LDO
3.3V
TPS7A7001
LDO
2.5V
USB to JTAG
（FT2232）
Key&LED&Reset&
switch
FPGA VCCO2
(LVDS)
FPGA
VCCX&VCCO0
&VCCO1
FPGA VCC
FPGA VCCO2
(MIPI)
TPS7A7001
LDO
1.8V
FPGA VCCO3
(PSRAM)
3.3.3 Pinout
Table 3-4 FPGA Power Pinout
Signal Name
Pin No.
BANK
Description
I/O Level
VCCO0
109, 127
0
I/O Bank Voltage
2.5V
VCCO1
91, 103
1
I/O Bank Voltage
2.5V
VCCO2
37, 55
2
I/O Bank Voltage
2.5V/1.2V
VCCO3
9, 19
3
I/O Bank Voltage
1.8V
VCCX
31, 77
-
Auxiliary voltage
2.5V
VCC
1, 36, 73, 108
-
Core voltage
1.2V
VSS
2, 17, 33, 35, 53,
74, 89, 105, 107
-
GND
-