GOWIN GW1NZ Series User manual

GW1NZ series of FPGA Products
Package & Pinout User Guide
UG843-1.8.1E,09/12/2023

Copyright © 2023 Guangdong Gowin Semiconductor Corporation. All Rights Reserved.
, LittleBee, and GOWIN are trademarks of Guangdong Gowin Semiconductor
Corporation and are registered in China, the U.S. Patent and Trademark Office, and other
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or otherwise, without the prior written consent of GOWINSEMI.
Disclaimer
GOWINSEMI assumes no liability and provides no warranty (either expressed or implied)
and is not responsible for any damage incurred to your hardware, software, data, or
property resulting from usage of the materials or intellectual property except as outlined in
the GOWINSEMI Terms and Conditions of Sale. GOWINSEMI may make changes to this
document at any time without prior notice. Anyone relying on this documentation should
contact GOWINSEMI for the current documentation and errata.

Revision History
Date
Version
Description
10/24/2018
1.0E
Initial version published.
01/10/2019
1.1E
Introduction to the I/O BANK updated.
04/03/2019
1.2E
I/O Bank View updated;
CS16 package outline updated.
08/23/2019
1.3E
The POD style of CS16 unified.
12/10/2019
1.4E
The QN48 package information added.
07/01/2020
1.5E
The FN32F package information added.
12/18/2020
1.6E
The new device of GW1NZ-2 added.
01/20/2021
1.6.1E
The GW1NZ-2 QN48 and QN48M added.
02/26/2021
1.7E
GW1NZ-2 removed.
11/25/2021
1.7.1E
The QN48 package information updated.
08/18/2023
1.8E
The units in the package diagrams standardized in millimeters.
The info. of QN48 and CS100H packages for GW1NZ-2 devices
added.
The recommended PCB layout in chapter 4 “Package Diagrams”
added.
09/12/2023
1.8.1E
The info. of FN24 and CG25 packages for GW1NZ-1 devices added.

Contents
UG843-1.8.1E
i
Contents
Contents.................................................................................................................i
List of Figures....................................................................................................iii
List of Tables......................................................................................................iv
1 About This Guide.............................................................................................1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................ 1
1.3 Abbreviations and Terminology........................................................................................... 1
1.4 Support and Feedback .......................................................................................................2
2 Overview...........................................................................................................3
2.1 PB-Free Package ...............................................................................................................3
2.2 Package and Max. User I/O Information ............................................................................3
2.3 Power Pin ........................................................................................................................... 4
2.4 Pin Quantity ........................................................................................................................4
2.4.1 Quantity of GW1NZ-1 Pins .............................................................................................. 4
2.4.2 Quantity of GW1NZ-2 Pins .............................................................................................. 5
2.5 Introduction to the I/O BANK ..............................................................................................6
3 View of Pin Distribution ..................................................................................7
3.1 View of GW1NZ-1 Pin Distribution ..................................................................................... 7
3.1.1 View of CS16 Pin distribution ..........................................................................................7
3.1.2 View of FN32 Pin Distribution .......................................................................................... 8
3.1.3 View of FN32F Pin Distribution........................................................................................9
3.1.4 View of QN48 Pin Distribution .......................................................................................10
3.1.5 View of CG25 Pin Distribution ....................................................................................... 11
3.1.6 View of FN24 Pin Distribution ........................................................................................ 12
3.2 View of GW1NZ-2 Pin Distribution ...................................................................................13
3.2.1 View of QN48 Pin Distribution .......................................................................................13
3.2.2 View of CS100H Pin Distribution ...................................................................................14
4 Package Diagrams.........................................................................................15
4.1 CS16 Package Outline (1.8mm x 1.8mm) ........................................................................15

Contents
UG843-1.8.1E
ii
4.2 FN32 Package Outline (4mm x 4mm) ..............................................................................17
4.3 FN32F Package Outline (4mm x 4mm)............................................................................19
4.4 QN48 Package Outline (6mm x 6mm, GW1NZ-1/2) ........................................................21
4.5 CS100H Package Outline (4mm x 4mm) .........................................................................23
4.6 CG25 Package Outline (1.8mm x 1.8mm) .......................................................................25
4.7 FN24 Package Outline (3mm x 3mm) ..............................................................................26

List of Figures
UG843-1.8.1E
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List of Figures
Figure 3-1 View of GW1NZ-1 CS16 Pin Distribution (Top View) ....................................................... 7
Figure 3-2 View of GW1NZ-1 FN32 Pin Distribution (Top View) .......................................................8
Figure 3-3 View of GW1NZ-1 FN32F Pin Distribution (Top View) ..................................................... 9
Figure 3-4 View of GW1NZ-1 QN48 Pin Distribution (Top View).......................................................10
Figure 3-5 View of GW1NZ-1 CG25 Pin Distribution (Top View).......................................................11
Figure 3-6 View of GW1NZ-1 FN24 Pin Distribution (Top View) .......................................................12
Figure 3-7 View of GW1NZ-2 QN48 Pin Distribution (Top View).......................................................13
Figure 3-8 View of GW1NZ-2 CS100H Pin Distribution (Top View)................................................... 14
Figure 4-1 Package Outline CS16 .....................................................................................................15
Figure 4-2 Recommended PCB Layout CS16...................................................................................16
Figure 4-3 Package Outline FN32 .....................................................................................................17
Figure 4-4 Recommended PCB Layout FN32 ...................................................................................18
Figure 4-5 Package Outline FN32F ...................................................................................................19
Figure 4-6 Recommended PCB Layout FN32F.................................................................................20
Figure 4-7 Package Outline QN48..................................................................................................... 21
Figure 4-8 Recommended PCB Layout QN48 ..................................................................................22
Figure 4-9 Package Outline CS100H ................................................................................................23
Figure 4-10 Recommended PCB Layout CS100H ............................................................................ 24
Figure 4-11 Package Outline CG25 ...................................................................................................25
Figure 4-12 Recommended PCB Layout CG25 ................................................................................25
Figure 4-13 Package Outline FN24 ...................................................................................................26
Figure 4-14 Recommended PCB Layout FN24 .................................................................................27

List of Tables
UG843-1.8.1E
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List of Tables
Table 1-1 Abbreviations and Terminology .......................................................................................... 1
Table 2-1 Package and Max. User I/O Information............................................................................ 3
Table 2-2 GW1NZ Power Pin.............................................................................................................4
Table 2-3 Quantity of GW1NZ-1Pins ..................................................................................................4
Table 3-1 Other Pins in GW1NZ-1 CS16 ........................................................................................... 7
Table 3-2 Other Pins in GW1NZ-1 FN32 ...........................................................................................8
Table 3-3 Other Pins in GW1NZ-1 FN32F ......................................................................................... 9
Table 3-4 Other Pins in GW1NZ-1 QN48...........................................................................................10
Table 3-5 Other Pins in GW1NZ-1 CG25........................................................................................... 11
Table 3-6 Other Pins in GW1NZ-1 FN24 ...........................................................................................12
Table 3-7 Other Pins in GW1NZ-2 QN48........................................................................................... 13
Table 3-8 Other pins in GW1NZ-2 CS100H.......................................................................................14

1 About This Guide
1.1 Purpose
UG843-1.8.1E
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1About This Guide
1.1 Purpose
This manual contains an introduction to the GW1NZ series of FPGA
products together with a definition of the pins, list of pin numbers,
distribution of pins, and package diagrams.
1.2 Related Documents
The latest user guides are available on the GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS841, GW1NZ series of FPGA Products Data Sheet
UG290, Gowin FPGA Products Programming and Configuration User
Guide
UG843, GW1NZ series of FPGA Products Package and Pinout
UG842, GW1NZ-1 Pinout
UG847, GW1NZ-2 Pinout
1.3 Abbreviations and Terminology
The abbreviations and terminology used in this manual are as shown in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Meaning
CG
WLCSP Package
FN
QFN Package
FPGA
Field Programmable Gate Array
GPIO
Gowin Programmable IO
QN
QFN Package

1 About This Guide
1.4 Support and Feedback
UG843-1.8.1E
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1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG843-1.8.1E
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2Overview
The GW1NZ series of FPGA products are the first generation products
in the LittleBee® family. They offer ultra-low power consumption, instant on,
low cost, non-volatile, high security, various packages, and flexible usage.
They can be widely used in industry control, communication, consumer,
video control, etc.
GOWINSEMI provides a new generation of FPGA hardware
development environment through market-oriented independent research
and development that supports the GW1NZ series of FPGA products and
applies to FPGA synthesizing, layout, place and routing, data bitstream
generation and download, etc.
2.1 PB-Free Package
The GW1NZ series of FPGA products are PB free in line with the EU
ROHS environmental directives. The substances used in the GW1NZ
series of FPGA products are in full compliance with the IPC-1752
standards.
2.2 Package and Max. User I/O Information
Table 2-1 Package and Max. User I/O Information
Package
Pitch (mm)
Size (mm)
GW1NZ-1
GW1NZ-2
CG25
0.35
1.8 x 1.8
20
-
CS100H
0.4
4 x 4
-
88 (27)
CS16
0.4
1.8 x 1.8
11
-
FN24
0.4
3 x 3
18
-
FN32
0.4
4 x 4
25
-
FN32F
0.4
4 x 4
25
-
QN48
0.4
6 x 6
41
41 (12)
Note!
In this manual, abbreviations are employed to refer to the package types. See 1.3
Abbreviations and Terminology.

2 Overview
2.3 Power Pin
UG843-1.8.1E
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The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. When mode
[2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS) can be
used as GPIO simultaneously.
2.3 Power Pin
Table 2-2 GW1NZ Power Pin
VCC
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCX
VCCPLL
VCCM
VCCD
VCCIOD
2.4 Pin Quantity
2.4.1 Quantity of GW1NZ-1 Pins
Table 2-3 Quantity of GW1NZ-1Pins
Pin Type
GW1NZ-1
CS16
CG25
FN24
FN32
FN32F
QN48
I/O Single
end/Differential pair[1]
BANK0
7/2
8/2
6/1
12/5
12/5
17/8
BANK1
4/0
12/6
12/6
13/5
13/5
23/11
Max. User I/O[2]
11
20
18
25
25
41
Differential Pair
2
8
7
10
10
19
VCC
1
1
1
1
1
2
VCCX
1
1
1
1
1
1
VCCIO0
1
1
1
1
1
1
VCCIO1
1
1
1
1
1
1
VSS
1
1
2
2
2
2
MODE0
1
1
1
0
0
1
MODE1
0
0
0
0
0
1
MODE2
0
1
1
0
0
0
JTAGSEL_N
0
0
0
1
1
1
Note!
[1] The number of single-ended/ Differential I/O pins includes CLK pins and download
pins.
[2] The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. When
mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS)
can be used as GPIO simultaneously.

2 Overview
2.4 Pin Quantity
UG843-1.8.1E
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2.4.2 Quantity of GW1NZ-2 Pins
Pin Type
GW1NZ-2
CS100H
QN48
I/O Single
end/Differential pair[1]
BANK0
26/11/6
10/4/1
BANK1
17/8/7
10/5/5
BANK2
23/11/7
8/4/1
BANK3
7/3/2
4/2/2
BANK4
8/4/2
2/1/1
BANK5
6/3/3
6/3/2
Max. User I/O[2]
88
41
Differential Pair
40
19
VCC
0
0
VCC/VCCPLL
1
1
VCCX
1
0
VCCIO0
1
1
VCCIO1
1
1
VCCIO2
1
0
VCCIO3
1
0
VCCIO4
1
0
VCCIO5
1
0
VCCIO3/VCCIO4/VCCIO5
0
1
VCCX/VCCIO2
0
1
VCCD/VCCIOD
1
0
VSS
2
2
MODE0
1
1
MODE1
0
0
MODE2
1
0
JTAGSEL_N
1
1
Note!
[1] The number of single-ended/ Differential I/O pins includes CLK pins and download
pins.
[2] The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. When
mode [2:0] = 001, JTAGSEL_N and the four JTAG pins (TCK, TDI, TDO, and TMS)
can be used as GPIO simultaneously.

2 Overview
2.5 Introduction to the I/O BANK
UG843-1.8.1E
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2.5 Introduction to the I/O BANK
GW1NZ-1 includes two I/O banks.
GW1NZ-2 includes six I/O banks.
Please refer to DS841, GW1NZ series of FPGA Products Data Sheet >
2.3 Input/Output Blocks for detailed bank distribution schematic.
This manual provides an overview of the distribution view of the pins in
the GW1NZ series of FPGA products. Please refer to 3 View of Pin
Distribution for further details. Different IO Banks in the GW1NZ series of
FPGA products are marked with different colors.
User I/O, power, and ground are marked with different symbols and
colors. The various symbols and colors used for various pins are defined
as follows:
“ ” denotes I/Os in BANK0.
“ ” denotes I/Os in BANK1.
“” denotes I/Os in BANK2.
“ ” denotes I/Os in BANK3.
“ ” denotes I/Os in BANK4.
“ ” denotes I/Os in BANK5.
“ ” denotes VCC, VCCX, and VCCIO. The filling color does not
change.
“ ” denotes VCC. The filling color does not change.
“ ” denotes NC.

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
UG843-1.8.1E
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3View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
3.1.1 View of CS16 Pin distribution
Figure 3-1 View of GW1NZ-1 CS16 Pin Distribution (Top View)
Table 3-1 Other Pins in GW1NZ-1 CS16
VCCIO0
B2
VCCIO1
C3
VCC
D4
VCCX
A1
VSS
C2

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
UG843-1.8.1E
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3.1.2 View of FN32 Pin Distribution
Figure 3-2 View of GW1NZ-1 FN32 Pin Distribution (Top View)
Table 3-2 Other Pins in GW1NZ-1 FN32
VCCIO0
5
VCCIO1
13
VCC
9
VCCX
4
VSS
8, 10

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
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3.1.3 View of FN32F Pin Distribution
Figure 3-3 View of GW1NZ-1 FN32F Pin Distribution (Top View)
Table 3-3 Other Pins in GW1NZ-1 FN32F
VCCIO0
5
VCCIO1
13
VCC
9
VCCX
4
VSS
8、10

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
UG843-1.8.1E
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3.1.4 View of QN48 Pin Distribution
Figure 3-4 View of GW1NZ-1 QN48 Pin Distribution (Top View)
Table 3-4 Other Pins in GW1NZ-1 QN48
VCC
12,37
VCCIO0
1
VCCIO1
25
VCCX
36
VSS
2,26

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
UG843-1.8.1E
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3.1.5 View of CG25 Pin Distribution
Figure 3-5 View of GW1NZ-1 CG25 Pin Distribution (Top View)
Table 3-5 Other Pins in GW1NZ-1 CG25
VCC
E5
VCCIO0
D4
VCCIO1
B2
VCCX
A1
VSS
C3

3 View of Pin Distribution
3.1 View of GW1NZ-1 Pin Distribution
UG843-1.8.1E
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3.1.6 View of FN24 Pin Distribution
Figure 3-6 View of GW1NZ-1 FN24 Pin Distribution (Top View)
Table 3-6 Other Pins in GW1NZ-1 FN24
VCC
6
VCCIO0
18
VCCIO1
9
VCCX
2
VSS
12,17

3 View of Pin Distribution
3.2 View of GW1NZ-2 Pin Distribution
UG843-1.8.1E
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3.2 View of GW1NZ-2 Pin Distribution
3.2.1 View of QN48 Pin Distribution
Figure 3-7 View of GW1NZ-2 QN48 Pin Distribution (Top View)
Table 3-7 Other Pins in GW1NZ-2 QN48
VCCIO0
1
VCCIO1
37
VCCIO3/VCCIO4/VCCIO5
25
VCC/VCCPLL
12
VCCX/VCCIO2
36
VSS
26,2