GOWIN GW2A Series User manual

GW2A series of FPGA Products
Package & Pinout User Guide
UG111-1.8E, 12/27/2021

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and is not responsible for any damage incurred to your hardware, software, data, or
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Revision History
Date
Version
Description
06/18/2018
1.06E
Initial version.
09/12/2018
1.07E
MBGA196 package information added;
PBGA256S package information added;
QFN88 package information added.
01/14/2019
1.08E
LVDS pairs added in Table 2-1;
IO BANK description and view of pin distribution updated.
04/11/2019
1.09E
PG256C package information added;
MG196 pins description updated;
EQ144 package information added.
06/04/2019
1.1E
PG484 package outline changed.
07/10/2019
1.2E
The GW2A-55 UG324 package added.
07/29/2019
1.3E
GW2A-18 PG484 package outline changed;
GW2A-55 PG484 package outline added.
12/12/2019
1.4E
GW2A-55 UG324D package information added;
GW2A-18 PG256E package information added;
03/06/2020
1.5E
Pin distribution table of GW2A-18 PG256C, UG324, and
PG256E updated;
Pin distribution table of GW2A-55 UG324 and UG324D
updated;
GW2A-18C and GW2A-55C added.
04/16/2020
1.5.1E
I/O Information of GW2A-55 UG324 updated.
09/25/2020
1.6E
The GW2A-55 UG676 package added.
07/16/2021
1.7E
The UG484 and PG256CF packages of GW2A-18 added.
08/25/2021
1.7.1E
PG256 package outline updated.
12/27/2021
1.8E
The PG256SF package of GW2A-18 added.
The UG324F package of GW2A-55 added.

Contents
UG111-1.8E
i
Contents
Contents.................................................................................................................i
List of Figures....................................................................................................iii
List of Tables.......................................................................................................v
1 About This Guide.............................................................................................1
1.1 Purpose ..............................................................................................................................1
1.2 Related Documents ............................................................................................................1
1.3 Abbreviations and Terminology...........................................................................................2
1.4 Support and Feedback .......................................................................................................2
2 Overview...........................................................................................................3
2.1 PB-Free Package ............................................................................................................... 3
2.2 Package and Max. I/O Information .....................................................................................4
2.3 Power Pin ...........................................................................................................................4
2.4 Pin Quantity ........................................................................................................................5
2.4.1 Quantity of GW2A-18 Pins ..............................................................................................5
2.4.2 Quantity of GW2A-55 Pins ..............................................................................................8
2.5 Pin Definitions.....................................................................................................................9
2.6 Introduction to the I/O BANK .............................................................................................11
3 View of Pin Distribution ................................................................................13
3.1 View of GW2A-18 Pins Distribution..................................................................................14
3.1.1 View of QN88 Pins Distribution .....................................................................................14
3.1.2 View of LQ144 Pins Distribution ....................................................................................15
3.1.3 View of EQ144 Pins Distribution.................................................................................... 16
3.1.4 View of MG196 Pins Distribution ...................................................................................17
3.1.5 View of PG256 Pins Distribution.................................................................................... 18
3.1.6 View of PG256S Pins Distribution ................................................................................. 19
3.1.7 View of PG256C Pins Distribution................................................................................. 20
3.1.8 View of UG324 Pins Distribution ...................................................................................21
3.1.9 View of PG484 Pins Distribution.................................................................................... 22
3.1.10 View of PG256E Pins Distribution ...............................................................................24
3.1.11 View of UG484 Pins Distribution..................................................................................25

Contents
UG111-1.8E
ii
3.1.12 View of PG256CF Pins Distribution.............................................................................26
3.1.13 View of PG256SF Pins Distribution............................................................................. 27
3.2 View of GW2A-55 Pin Distribution....................................................................................28
3.2.1 View of UG324 Pin Distribution .....................................................................................28
3.2.2 View of UG324D Pin Distribution................................................................................... 29
3.2.3 View of PG484 Pin Distribution .....................................................................................30
3.2.4 View of PG1156 Pin Distribution.................................................................................... 32
3.2.5 View of UG676 Pin Distribution .....................................................................................34
3.2.6 View of UG324F Pin Distribution ...................................................................................35
4 Package Diagrams.........................................................................................36
4.1 QN88 Package Outline (10mm x 10mm)..........................................................................37
4.2 LQ144 Package Outline (20mm x 20mm) ........................................................................38
4.3 EQ144 Package Outline (20mm x 20mm)........................................................................ 39
4.4 MG196 Package Outline (8mm x 8mm) ........................................................................... 40
4.5 PG256 Package Outline (17mm x 17mm)........................................................................ 41
4.6 PG256C/ PG256CF Package Outline (17mm x 17mm) ...................................................42
4.7 PG256S / PG256SF Package Outline (17mm x 17mm) .................................................. 43
4.8 PG256E Package Outline (17mm x 17mm) .....................................................................44
4.9 PG484 Package Outline (23mm x 23mm, GW2A-18)......................................................45
4.10 PG484 Package Outline (23mm x 23mm, GW2A-55)....................................................46
4.11 PG1156 Package Outline (35mm x 35mm) ....................................................................47
4.12 UG324/UG324D/UG324F Package Outline (15mm x 15mm)........................................ 48
4.13 UG484 Package Outline (19mm x 19mm) .....................................................................49
4.14 UG676 Package Outline (21mm x 21mm) .....................................................................50

List of Figures
UG111-1.8E
iii
List of Figures
Figure 2-1 GW2A I/O Bank Distribution ............................................................................................. 11
Figure 3-1 GW2A-18 QN88 View of Pins Distribution (Top View) .....................................................14
Figure 3-2 GW2A-18 LQ144 View of Pins Distribution ...................................................................... 15
Figure 3-3 GW2A-18 EQ144 View of Pins Distribution...................................................................... 16
Figure 3-4 GW2A-18 MG196 View of Pins Distribution ..................................................................... 17
Figure 3-5 GW2A-18 PG256View of Pins Distribution....................................................................... 18
Figure 3-6 GW2A-18 PG256S View of Pins Distribution ...................................................................19
Figure 3-7 GW2A-18 PG256C View of Pins Distribution................................................................... 20
Figure 3-8 GW2A-18 UG324 View of Pins Distribution (Top View) ................................................... 21
Figure 3-9 GW2A-18 PG484 View of Pins Distribution (Top View) ...................................................22
Figure 3-10 GW2A-18 PG256E View of Pins Distribution ................................................................. 24
Figure 3-11 GW2A-18 UG484 View of Pins Distribution.................................................................... 25
Figure 3-12 GW2A-18 PG256CF View of Pins Distribution............................................................... 26
Figure 3-13 GW2A-18 PG256SF View of Pins Distribution............................................................... 27
Figure 3-14 View of GW2A-55 UG324 Pin Distribution ..................................................................... 28
Figure 3-15 View of GW2A-55 UG324D Pin Distribution...................................................................29
Figure 3-16 View of GW2A-55 PG484 Pin Distribution ..................................................................... 30
Figure 3-17 View of GW2A-55 PG1156 Pin Distribution (Top View).................................................. 32
Figure 3-18 View of GW2A-55 UG676 Pin Distribution (Top View) ................................................... 34
Figure 3-19 View of GW2A-55 UG324F Pin Distribution (Top View)................................................. 35
Figure 4-1 Package Outline QN88..................................................................................................... 37
Figure 4-2 Package Outline LQ144 ...................................................................................................38
Figure 4-3 Package Outline EQ144................................................................................................... 39
Figure 4-4 Package OutlineMG196 ...................................................................................................40
Figure 4-5 Package Outline PG256................................................................................................... 41
Figure 4-6 Package Outline PG256C ................................................................................................ 42
Figure 4-7 Package Outline PG256S / PG256SF..............................................................................43
Figure 4-8 Package Outline PG256E ................................................................................................44
Figure 4-9 Package Outline PG484................................................................................................... 45
Figure 4-10 Package Outline PG484.................................................................................................46
Figure 4-11 Package Outline PG1156 ...............................................................................................47
Figure 4-12 Package Outline UG324/UG324D/UG324F................................................................... 48

List of Figures
UG111-1.8E
iv
Figure 4-13 Package Outline UG484................................................................................................. 49
Figure 4-14 Package Outline UG676................................................................................................. 50

List of Tables
UG111-1.8E
v
List of Tables
Table 1-1 Abbreviations and Terminology ..........................................................................................2
Table 2-1 Package and Max. I/O Information ....................................................................................4
Table 2-2 GW2A Power Pin ...............................................................................................................4
Table 2-3 Quantity of GW2A-18 Pins................................................................................................. 6
Table 2-4 Quantity of GW2A-55 Pins................................................................................................. 8
Table 2-5 Definition of the Pins in the GW2A series of FPGA Products ............................................ 9
Table 3-1 Other Pins in GW2A-18 QN88 ........................................................................................... 14
Table 3-2 Other Pins in GW2A-18 LQ144.......................................................................................... 15
Table 3-3 Other Pins in GW2A-18 EQ144 .........................................................................................16
Table 3-4 Other Pins in GW2A-18 MG196......................................................................................... 17
Table 3-5 Other Pins in GW2A-18 PG256 (Power, MODE, and Ground, compatible with GW1N)...18
Table 3-6 Other Pins in GW2A-18 PG256S.......................................................................................19
Table 3-7 Other Pins in GW2A-18 PG256C....................................................................................... 20
Table 3-8 Other Pins in GW2A-18 UG324 .........................................................................................21
Table 3-9 Other Pins in GW2A-18 PG484 .........................................................................................23
Table 3-10 Other Pins in GW2A-18 PG256E.....................................................................................24
Table 3-11 Other Pins in GW2A-18 UG484 ....................................................................................... 25
Table 3-12 Other Pins in GW2A-18 PG256CF .................................................................................. 26
Table 3-13 Other Pins in GW2A-18 PG256SF................................................................................... 27
Table 3-14 Other Pins of GW2A-55 UG324.......................................................................................28
Table 3-15 Other Pins of GW2A-55 UG324D ....................................................................................29
Table 3-16 Other Pins of GW2A-55 PG484 ....................................................................................... 31
Table 3-17 Other Pins in GW2A-55 PG1156 .....................................................................................33
Table 3-18 Other Pins in GW2A-55 UG676 .......................................................................................34
Table 3-19 Other Pins in GW2A-55 UG324F.....................................................................................35

1 About This Guide
1.1 Purpose
UG111-1.8E
1(50)
1About This Guide
1.1 Purpose
This manual mainly contains an introduction to the GW2A series of
FPGA products together with a definition of the pins, list of pin numbers,
distribution of pin, and package diagrams.
1.2 Related Documents
The latest user guides are available on GOWINSEMI Website. You
can find the related documents at www.gowinsemi.com:
DS102, GW2A series of FPGA Products Data Sheet
UG290, Gowin FPGA Products Programming and Configuration User
Guide
UG111, GW2A series FPGA Products Package and Pinout
UG110, GW2A-18 Pinout
UG113, GW2A-55 Pinout

1 About This Guide
1.3 Abbreviations and Terminology
UG111-1.8E
2(50)
1.3 Abbreviations and Terminology
The abbreviations and terminologies used in this manual are set out in
Table 1-1 below.
Table 1-1 Abbreviations and Terminology
Abbreviations and Terminology
Name
FPGA
Field Programmable Gate Array
LVDS
Low-Voltage Differential Signaling
GPIO
Gowin Programmable IO
LQ
LQFP
EQ
ELQFP
PG
PBGA
UG
UBGA
1.4 Support and Feedback
Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly using the information provided below.
Website: www.gowinsemi.com
E-mail: [email protected]

2 Overview
2.1 PB-Free Package
UG111-1.8E
3(50)
2Overview
The GW2A series of FPGA products are the first-generation products
of Arora® family. They are available in various forms that offer high I/O
compatibility and flexible usage.
2.1 PB-Free Package
The GW2A series of FPGA Products are PB free, in line with the EU
ROHS environmental directives. The substances used in the GW2A series
of FPGA products are in full compliance with the IPC-1752 standards.

2 Overview
2.2 Package and Max. I/O Information
UG111-1.8E
4(50)
2.2 Package and Max. I/O Information
Table 2-1 Package and Max. I/O Information
Package
Pitch(mm)
Size(mm)
GW2A-18
GW2A-55
QN88
0.4
10 x 10
66（22）
-
LQ144
0.5
22 x 22
119（34）
EQ144
0.5
22 x 22
119（34）
-
MG196
0.5
8 x 8
114（39）
-
PG256
1.0
17 x 17
207（73）
-
PG256S
1.0
17 x 17
192（72）
-
PG256SF
1.0
17 x 17
192（71）
-
PG256C
1.0
17 x 17
190（64）
-
PG256CF
1.0
17 x 17
190（65）
PG256E
1.0
17 x 17
162（29）
-
UG324
0.8
15 x 15
239（90）
240（86）
UG324F
0.8
15 x 15
-
240（86）
UG324D
0.8
15 x 15
-
240（72）
UG484
0.8
19 x 19
379（94）
-
UG676
0.8
21 x 21
-
525（97）
PG484
1.0
23 x 23
319（78）
319（76）
PG1156
1.0
35 x 35
-
607（97）
Note!
The package types in this manual are written with abbreviations. See 1.3 Abbreviations
and Terminology;
denotes that the various device pins are compatible when the package types are
the same;
The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O;
For GW2A-18 LQ144 package, I/O rate of JTAG pin multiplexing is less than 40 MHz.
2.3 Power Pin
Table 2-2 GW2A Power Pin
VCC
VCCO0
VCCO1
VCCO2
VCCO3
VCCO4
VCCO5
VCCO6
VCCO7
VCCX
VSS
NC
VCCPLLL0
VCCPLLL1
VCCPLLR0
VCCPLLR1
VCCPLLL
VCCPLLR

2 Overview
2.4 Pin Quantity
UG111-1.8E
5(50)
2.4 Pin Quantity
2.4.1 Quantity of GW2A-18 Pins

2 Overview
2.4 Pin Quantity
UG111-1.8E
6(50)
Table 2-3 Quantity of GW2A-18 Pins
Pin Type
GW2A-18
QN88
LQ144
EQ144
MG196
PG256
PG256S
PG256C
UG324
PG484
PG256E
UG484
PG256CF
PG256SF
I/O Single
end/Differential
pair /LVDS[1]
BANK0
8/4/2
19/8/4
19/8/4
12/6/4
29/14/10
20/10/8
25/12/8
28/14/12
40/20/10
26/13/5
48/24/12
26/12/8
20/10/8
BANK1
9/4/4
12/6/6
12/6/6
14/7/6
20/10/10
19/9/9
26/12/11
28/14/11
39/18/10
14/7/3
47/23/12
25/12/11
19/9/9
BANK2
4/2/1
12/6/3
12/6/3
16/8/5
20/10/7
30/15/11
16/7/5
28/14/10
46/23/11
12/6/2
47/23/11
16/7/5
30/15/11
BANK3
17/6/3
21/9/5
21/9/5
25/12/7
29/13/10
37/18/10
36/17/9
39/19/11
31/15/8
31/12/4
47/23/11
36/17/9
37/18/9
BANK4
8/3/3
17/8/6
17/8/6
13/6/4
36/18/12
16/7/7
27/13/11
28/14/12
40/20/10
18/9/3
48/24/12
27/13/11
16/7/7
BANK5
10/5/5
16/8/5
16/8/5
8/4/3
36/18/11
18/9/8
26/12/9
28/14/12
40/20/10
18/9/4
48/24/12
26/12/9
18/9/8
BANK6
9/4/4
11/5/3
11/5/3
12/6/5
18/9/8
24/12/8
19/9/7
28/14/11
34/17/8
20/10/4
47/23/12
19/9/7
24/12/8
BANK7
1/0/0
8/4/2
8/4/2
14/7/5
16/7/5
28/14/11
15/7/5
32/16/11
46/23/11
23/11/4
47/23/12
15/7/5
28/14/11
Max. User I/O[2]
66
119
119
114
207
192
190
239
319
162
379
190
192
Differential Pair
28
54
54
56
99
94
89
119
157
77
187
89
94
TrueLVDS Output
22
34
34
39
73
72
65
90
78
26
94
65
71
VCC
4
0
0
0
6
6
10
11
32
11
12
0
6
VCCX
0
0
0
8
2
8
0
12
8
6
0
0
8
VCCO0
1
1
1
2
2
3
3
3
3
2
4
3
3
VCCO1
1
1
1
2
2
2
3
3
3
2
5
3
2
VCCO2
0
0
0
3
1
3
2
3
3
2
0
2
3
VCCO3
1
2
2
3
2
3
2
3
3
3
5
2
3
VCCO4
1
1
1
2
2
2
3
3
3
2
4
3
2
VCCO5
1
1
1
2
2
2
3
3
3
6
5
3
2
VCCO6
0
0
0
3
1
3
2
3
3
2
0
2
3
VCCO7
1
2
2
3
2
2
0
3
3
2
0
0
2
VCCO6/VCCO7
0
0
0
0
0
0
0
0
0
0
9
0
0
VCCX/VCCO2
0
0
0
0
0
0
0
0
0
0
4
0
0

2 Overview
2.4 Pin Quantity
UG111-1.8E
7(50)
Pin Type
GW2A-18
QN88
LQ144
EQ144
MG196
PG256
PG256S
PG256C
UG324
PG484
PG256E
UG484
PG256CF
PG256SF
VCCX/VCCO7
0
0
0
0
0
0
2
0
0
0
0
2
0
VCC/VCCPLLL1[3]
0
4
4
0
0
0
0
0
0
0
0
0
0
VCCX/ VCCO2/ VCCO6[3]
2
2
2
0
0
0
0
0
0
0
0
0
0
VCCPLLL0
0
1
1
0
0
0
0
0
0
0
1
0
0
VCCPLLL1
1
0
0
0
0
0
0
0
0
0
1
0
0
VCCPLLR0
0
1
1
0
0
0
0
0
0
0
1
0
0
VCCPLLR1
1
1
1
0
0
0
0
0
0
0
1
0
0
VCCPLLL
0
0
0
0
1
1
1
0
2
0
0
0
1
VCCPLLR
0
0
0
0
1
1
1
0
2
0
0
0
1
VCC/VCCPLLL/VCCPLLR
0
0
0
0
0
0
10
11
0
11
0
10
0
VCC/VCCPLLL0/VCCPLLL1/
VCCPLLR0/VCCPLLR1
0
0
0
15
0
0
0
0
0
0
0
0
0
VSS
7
7
7
39
24
26
33
37
95
52
52
33
26
MODE0
1
1
1
1
1
1
1
1
1
0
1
1
1
MODE1
1
1
1
1
1
1
1
1
1
0
1
1
0
MODE2
0
1
1
0
1
0
1
1
1
0
1
1
1
EXTR
1
1
1
0
1
0
0
0
1
0
0
0
1
JTAGSEL_N
0
0
0
0
0
1
1
1
1
0
1
1
1
NC
0
0
0
0
0
1
2
0
0
4
0
2
1
Note!
[1]Single end/ Differential/LVDS I/O quantity include CLK pins, and download pins; The EXTR No. is excluded;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in this table is when the loaded four JTAG pins (TCK,
TDI, TDO, and TMS) are used as I/O;
[3]Pin multiplexing.

2 Overview
2.4 Pin Quantity
UG111-1.8E
8(50)
2.4.2 Quantity of GW2A-55 Pins
Table 2-4 Quantity of GW2A-55 Pins
Pin Type
GW2A-55
UG324
UG324D
PG484
PG1156
UG676
UG324F
I/O Single
end/Differential
pair/LVDS/LVDS
output1
BANK0
28/14/10
28/14/10
40/20/10
80/40/14/6
68/34/14/0
28/14/10
BANK1
28/14/13
28/14/13
39/19/10
79/39/16/4
71/35/16/0
28/14/13
BANK2
28/14/10
28/14/10
46/23/10
80/40/10/10
66/33/10/3
28/14/10
BANK3
40/20/9
40/20/9
31/15/8
61/30/9/7
58/29/9/4
40/20/9
BANK4
28/14/13
28/14/13
40/20/10
80/40/16/4
72/36/16/0
28/14/13
BANK5
28/14/13
28/14/13
40/20/10
80/40/14/6
68/34/14/0
28/14/13
BANK6
28/14/9/1
28/5/2
34/17/8
64/32/8/8
56/28/8/4
28/14/9/1
BANK7
32/16/10
32/5/1
46/23/10
80/40/10/10
66/33/10/3
32/16/10
Max. User I/O2
240
240
319
607
525
240
Differential Pair
120
100
157
301
262
120
True LVDS Output
86
71
76
97
97
86
Only True LVDS Output3
0
0
0
55
14
0
VCC
11
11
32
32
19
11
VCCX
12
12
8
16
14
12
VCCO0
3
3
3
12
5
3
VCCO1
3
3
3
11
4
3
VCCO2
3
3
3
12
5
3
VCCO3
3
3
3
11
4
3
VCCO4
3
3
3
12
5
3
VCCO5
3
3
3
11
4
3
VCCO6
3
3
3
12
5
3
VCCO7
3
3
3
11
4
3
VCCPLLL
0
0
2
2
2
0
VCCPLLR
0
0
2
2
2
0
VSS
37
37
95
172
77
37
MODE0
0
0
1
1
1
0
MODE1
0
0
1
1
1
0
MODE2
1
1
1
1
1
1
MODE0/MODE1
1
1
0
0
0
1
EXTR
0
0
1
1
0
0
NC
0
0
0
231
0
0
JTAGSEL_N
1
1
1
1
1
1
Note!
[1]I/O Single end/ Differential pair/LVDS/ LVDS output quantity include CLK pins and
download pins, PG484 has no LVDS output; The EXTR No. is excluded;

2 Overview
2.5 Pin Definitions
UG111-1.8E
9(50)
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The data in
this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS) are used as
I/O;
[3]Support true LVDS output only, do not support input.
2.5 Pin Definitions
The location of the Pins in the GW2A series of FPGA products varies
according to the different packages.
Table 2-5 provides a detailed overview of user I/O, multi-function pins,
dedicated pins, and other pins.
Table 2-5 Definition of the Pins in the GW2A series of FPGA Products
Pin Name
I/O
Description
User I/O Pins
IO[End][Row/Column
Number][A/B]
I/O/LVDS
[End] indicates the pin location, including L (left) R(right)
B(bottom), and T(top)
[Row/Column Number] indicates the pin Row/Column
number. If [End] is T (top) or B (bottom), the pin indicates
the column number of the corresponding CFU. If [End] is L
(left) or R (right), the pin indicates the Row number of the
corresponding CFU.
[A/B] indicates differential signal pair information.
LVDS in the I/O column indicates that the pin support
LVDS output only.
Multi-Function Pins
IO[End][Row/Column Number][A/B]/MMM
/MMM represents one or more of the other functions in
addition to being general purpose user I/O. These pins
can be used as user I/O when the functions are not used.
RECONFIG_N
I, internal weak
pull-up
Start new GowinCONFIG mode when low pulse
READY
I/O
When high level, the device can be programmed and
configured
When low level, the device cannot be programmed and
configured
DONE
I/O
High level indicates successful program and configure
Low level indicates incomplete or failed to program and
configure
FASTRD_N /D3
I/O
In MSPI mode, FASTRD_N is used as Flash access
speed port. Low indicates high-speed Flash access mode;
high indicates regular Flash access mode.
Data port D3 in CPU mode
MCLK /D4
I/O
Clock output MCLK in MSPI mode
Data port D4 in CPU mode
MCS_N /D5
I/O
Enable signal MCS_N in MSPI mode, active-low
Data port D5 in CPU mode
MI /D7
I/O
MISO in MSPI mode: Master data input/Slave data output
Data port D7 in CPU mode
MO /D6
I/O
MISO in MSPI mode: Master data output/Slave data input
Data port D6 in CPU mode
SSPI_CS_N/D0
I/O
Enable signal SSPI_CS_N in SSPI mod, active-low,

2 Overview
2.5 Pin Definitions
UG111-1.8E
10(50)
Pin Name
I/O
Description
Internal Weak Pull Up
Data port D0 in CPU mode
SO /D1
I/O
MISO in MSPI mode: Master data input/Slave data output
Data port D1 in CPU mode
SI /D2
I/O
MISO in MSPI mode: Master data output/Slave data input
Data port D2 in CPU mode
TMS
I, internal weak
pull-up
Serial mode input in JTAG mode
TCK
I
Serial clock input in JTAG mode, which needs to be
connected with 4.7 K drop-down resistance on PCB
TDI
I, internal weak
pull-up
Serial data input in JTAG mode
TDO
O
Serial data output in JTAG mode
JTAGSEL_N
I, internal weak
pull-up
Select signal in JTAG mode, active-low
SCLK
I
Clock input in SSPI, SERIAL, and CPU mode
DIN
I, internal weak
pull-up
Input data in SERIAL mode
DOUT
O
Output data in SERIAL mode
CLKHOLD_N
I, internal weak
pull-up
High level, SCLK will be connected internally in SSPI
mode or CPU mode
Low level, SCLK will be disconnected from SSPI mode or
CPU mode
WE_N
I
Select data input/output of D[7:0] in CPU mode
GCLKT_[x]
I
Pins for global clock input, T(True), [x]: global clock No.
GCLKC_[x]
I
Differential comparation input pin of GCLKT_[x],
C(Comp), [x]: global clock No.[1].
LPLL_T_fb/RPLL_T_fb
I
L/R PLL feedback input pin, T(True)
LPLL_C_fb/RPLL_C_fb
I
L/R PLL feedback input pin, C(Comp)
LPLL_T_in/RPLL_T_in
I
L/R PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in
I
L/R PLL clock input pin, C(Comp)
Dedicated Pins
MODE2
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE1
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
MODE0
I, internal weak
pull-up
GowinCONFIG modes selection pin; if this pin is not
bonded, it's internal grounded.
EXTR
NA
External 10K 1% resister grounding
The Other Pins
NC
NA
Reserved.
VSS
NA
Ground pins
VCC
NA
Power supply pins for internal core logic.
VCCO#
NA
Power supply pins for the I/O voltage of I/O BANK#.

2 Overview
2.6 Introduction to the I/O BANK
UG111-1.8E
11(50)
Pin Name
I/O
Description
VCCX
NA
Power supply pins for auxiliary voltage.
VCCPLLL01
NA
LQFP: Power supply pins for left PLL0/1, only available
for LQFP.
VCCPLLR0/1
NA
LQFP: Power supply pins for right PLL0/1, only available
for LQFP.
VCCPLLL
NA
PBGA: Power supply pins for left PLL0/1.
VCCPLLR
NA
PBGA: Power supply pins for right PLL0/1.
Note！
[1]When the input is single-ended, the GLKC_[x] pin is not a global clock pin.
2.6 Introduction to the I/O BANK
There are eight I/O Banks in the GW2A series of FPGA products, as
shown in Figure 2-1.
Figure 2-1 GW2A I/O Bank Distribution
GW2A
IO Bank0 IO Bank1
IO Bank2 IO Bank3
IO Bank4IO Bank5
IO Bank6IO Bank7
This manual provides an overview of the distribution view of the pins in
the GW2A series of FPGA products. The eight I/O Banks that form the
GW2A series of FPGA products are marked with eight different colors.
User I/O, power, and ground are marked with different symbols and
colors. The various symbols and colors used for the various pins are
defined as follows:
” ” denotes I/Os in BANK0. The filling color changes with the BANK;
“ ” denotes I/Os in BANK1. The filling color changes with the BANK;
“ ” denotes I/Os in BANK2. The filling color changes with the BANK;
“ ” denotes I/Os in BANK3. The filling color changes with the BANK;
” ” denotes I/Os in BANK4. The filling color changes with the BANK;
“ ” denotes I/Os in BANK5. The filling color changes with the BANK;
“ ” denotes I/Os in BANK6. The filling color changes with the BANK;
“ ” denotes I/Os in BANK7. The filling color changes with the BANK;

2 Overview
2.6 Introduction to the I/O BANK
UG111-1.8E
12(50)
” ” denotes VCC, VCCX, and VCCO. The filling color does not
change;
” ” denotes VSS. The filling color does not change;
” ” denotes NC;
” ” denotes dedicated pins EXTR.