HP MICRO 3000 User manual

Part No. 30534-90001
Ei 286
HP 3000 Computer Systems
MICRO 3000 SELFTEST and
MAINTENANCE MODE
Diagnostic Manual
8010 FOOTHILLS BLVD., ROSEVILLE, CA 95678
Printed in U. S. A. 12/86

NOTICE
The information contained in this document is subject to change without notice.
HEWLETT-PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS
MATERiAL, iNCLUDiNG, BUT NOT LiMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard shall not
be liable for errors contained herein or for incidental or consequential damages in connection with the
furnishing, performance or use of this material.
Hewlett-Packard assumes no responsibility for the use or reiiabiiity of its sofiware on equipment that
is not furnished by Hewlett -Packard.
This document contains proprietary information which is protected by copyright. All rights are
reserved. No part of this document may be photocopied, reproduced or translated to another language
without the prior written consent of Hewlett-Packard Company.
Copyright © 1986 by HEWLETf-PACKARD COMPANY

PRINTING HISTORY
New editions are complete revisions of the manual. Update packages, which are issued between editions,
contain additional and replacement pages to be merged into the manual by the customer. The dates on
the title page change only when a new edition or a new update is published. No information is
incorporated into a reprinting unless it appears as a prior update; the edition does not change when an
update is incorporated.
First Edition ......................................... Dec 1986
DEC 86
111

LIST OF EFFECTIVE PAGES
The List of Effective Pages gives the date of the most recent version of each page in the manual.
To verify that your manual contains the most current information, check the dates printed at
the bottom of each page with those listed below. The date on the bottom of each page reflects
the edition or subsequent update in which that page was printed.
Effective Pages
Date
all .................................... Dec 1986
DEC 1986
iv

CONTENTS
Section I
GENERAL INFORMATION
Introduction ............................................. )-1
Required Hardware ......................................... I-I
Selftest ROM Code ......................................... 1- 2
Seiftest Executive .......................................... i- 2
Power-On Selftest .......................................... 1- 2
Maintenance Mode ......................................... 1- 3
The Remote Console . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 4
Section 2
OPERA TING INSTRUCTIONS
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ........... 2-1
Keyswitch Capabilities. . . . . . . . . . . . . . . . . . . . . . . ........... 2-)
Test Execution Time. . . . . . . . . . . . . . . . . . . . . . . . ........... 2-2
Front Panel LED Indicators .................................... 2-2
Power-On Selftest Execution ................................... 2- 3
Maintenance Mode ............................. : ........... 2-4
Test Mode ............................................... 2-6
Remote Operator Interface .................................... 2-6
Establishing the Remote Console Link .................. , . , , .. , .. 2-7
Disconnecting the Remote Console Link ........................... 2-7
Section 3
MAINTENANCE MODE COMMAND DESCRIPTIONS
Introduction ............................................. 3-1
Maintenance Mode Commands .................................. 3-1
Automatic Warmstart. ..................................... 3-1
Automatic Restart ........................................ 3- 2
Coldstart .............................................. 3- 2
Cooistart .............................................. 3- 3
Disc
................................................. 3-3
Dump ................................................ 3-4
Help ................................................. 3-4
Load ................................................. 3- 5
Newsystem ............................................. 3-5
Panel ................................................ 3-6
Reload ............................................... 3-6
Run ................................................. 3-6
DEC 86
v

CONTENTS (continued)
DEC 86
Speed ....... .
Start. ....... .
Tape ........ .
Test ........ .
Update ...... .
Warmstart .... .
Section 4
TEST MODE COMMAND DESCRIPTIONS
Introduction ............................ .
Test Mode Commands ...................... .
All
................................. .
Channel ..... .
ATP Test ... .
PIC Test. ... .
LANIC Test ..
CPU ........ .
Exit ........................... .
Help ................. .
IOMA~ ..................... .
Memory .................... .
PON ....................... .
Section 5
SOFTPANEL
· ...... 3-6
· ...... 3-7
· ...... 3-7
· ...... 3-7
· ...... 3-8
· ...... 3-8
· .......... 4-1
· .......... 4-1
· .......... 4-1
· .......... 4-3
· .......... 4-3
. ........ 4-3
. ........ 4-4
· .. 4-4
· .. 4-5
· .. 4-6
· .. 4-6
· .. 4-7
· .......... 4~8
Introduction ............................................. 5-1
Command Parameters ....................................... 5-1
Com rna nd Descript ions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 2
Display Memory ......................................... 5- 2
Modify Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... 5- 3
Register Operations . . . . . . . . . . . . . . .. ...................... 5- 4
Execution Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-5
Input/Output Operations .................................... 5- 5
Miscellaneous Commands .................................... 5- 5
CPU ROMS Date Code 2647 Exceptions .......................... 5-6
I

CONTENTS (continued)
Appendix A
ERROR CODES
A TP Test Error Codes ..................................... , A-I
ATP Test Section I ..................... 0 ••••••••••••••• , A-I
ATP Test Section 2 ..................................... , A-I
ATP Test Section 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- 2
ATP Test Section 4 ...................................... A-2
A TP Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A- 2
ATP Test Section 6 ...................................... A-3
A TP Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- 3
PIC Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- 4
PIC Test Section 1 ...................................... , A-4
PIC Test Section 2 ...................................... , A-4
PIC Test Section 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- S
PIC Test Section 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- 5
PIC Test Section 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6
PIC Test Section 6 ...................................... , A-6
PIC Test Section 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-6
PIC Test Section 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A-7
PIC Test Section 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. A- 7
LANIC Selftest Subtest
and Error Codes ........................... A-8
LANIC Selftest Subtest Codes ................................ A-8
LANIC Selftest Error Codes ................................. A-9
CPU Test Error Codes . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . A-I 0
Memory Test Error Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-I 0
Power-On Selftest LED Interpretation ............................ A-II
Appendix B
TOe RAM INFORMATION
TOC RAM Data and Status Tables ............................... B-1
DEC 86
vii

FIGURES AND TABLES
LIST OF TABLES
Table 2-1. Keyswitch Capabilities ............................... 2-1
Table 2-2. Maintenance Mode Commands .......................... 2-5
Table 2-3. Test Mode Commands ................................ 2-6
Table A -1. Power-On Selftest LED Interpretation .................... A -II
Table B-1. TOC RAM Data and Status ............................ B-1
Table 8-2. Last-Stop Value Meanings ............................. B-2
Table B-3. System Halt Causes ................................. 8-3
LIST OF FIGURES
Figure 2-1.
ACTIVITY/FAULT LEOs and Keyswitch .................. 2-2
DEC 86
viii

~ER_R_O_R_C_O_D_E_S ______________ ~lrH!H,
Appendix A includes aU error codes associa ted wiih i he -MiCRO 3000 seJftest. The errOi codes are listed
according to the test sequence they are associated with: ATP, PIC, LANle. CPU, ur MEMOR Y.
A TP TEST ERROR CODES
The ATP error codes are divided according to one of the nine sections of the ATP test that detected the
error.
The slot test will display (lne of the following error codes if the ATP test fads. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
ATP Test Section 1
This section is the initializ.ation test which initiahl.es the ATP and verifies registers l:ontain expected data.
Code Error
0108 Register 8 initialization error (expected $0800)
0109 Register 9 initializ.ation error (expeded $08(0)
010A Register A initializ.ation error (expected $FFOU)
010C Register C initializa tion error (expected $0000)
0100 Register D initialization error (expected $0000)
010E Register E initializa tion error (expected $ 5004)
010F Register F initialization error (expected $ 5004)
ATP Test Section 2
This section tests basic operations, and OBII, IPOLL, SMSK and RMSK.
Code Error
0201 SMSK/RMSK test; ATP did not respond with mask bit set.
0202 SMSK/RMSK test; ATP did not respond with mask bit clear.
0203 A TP did not set IRQ.
0204 Improper IPOLL response (none, wrong, or mUltiple channels).
0205 Improper OBU response.
DEC 86
A-I

Error Codes
ATP Test Section 3
The section is the port register test which tests registers 0-7 on ports 0-7.
Code Error
0300 Port 0, register 0 pa ttern test failure
0301 Port 0, register I pa ttern test failure
0307 Port 0, register 7 pattern test failure
0310 Port I, register 0 pattern test failure
0377 Port 7, register 7 pattern test failure
ATP Test Section 4
This section is the DMA test. SIMB write Word.
Code
Error
0401 DMA state ma\,;hine failed to ~o to state 4.
0402 DMA state machine failed 10 K{) to litatc 3.
0403 DMA write to memory lrallliferrcd improper data.
0404 DMA read from memory to RBYTE transferred improper data.
0405 DMA read from memory to LBYTE transferred improper data.
0406 DMA counter test failed.
ATP Test Section 5
Port selftest.
Code
Error
0500 Port 0 selftest failure
0501 Port I selftest failure
0507 Port 7 selftesl failure
DEC 86

ATP Test Section 6
This section is the DMA loopback to port test.
Code
Error
0600 Port 0 loopback failure
0601 Port 1 loopback failure
0607 Port 7 loop back failure
A TP Test Section 7
This section is the DMA loopback data test.
Code
Error
0700 Port 0 loopback data failure
0701 Port 1 loopback data failure
0707 Port 7 loopback data failure
Error Codes
DEC 86
A-3
I
I

Error Codes
PIC TEST ERROR CODES
If the PIC test fails, the slot test will display one of the following error codes. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
PIC Test Section 1
This section is the initialization test whidl initializes the PIC and verifies regi!;ters contain expected data.
Code Error
0104 Register 4 initialization error (expected SOOOO)
0105 Register 5 initialization error (expected SOOOO)
0106 Register 6 initializa tion error (expected $0020)
0107 Register 7 initialization error (expected SOOnG)
0108 Register 8 initializa tion error (expected $0000)
010A Register A initialization error (expected $0000)
010C Register C initiallza tion error (expect.ed $0000)
010f Register F initialization error (expected $0087+(8
t
channelH»
PIC Test Section 2
This sedion tests basic operations and 0811, IPOLl, SMSK and RMSK.
Code Error
0201 St'tlSK/RMSK test; PIC did not respond with mask bit set.
0202 SMSK/RMSK test; PIC did not respond with mask bit cleared.
0203 PIC did not set IRQ after SMSK on selected channel.
0204 Improper IPOtl. response after SMSK (no response,
wrong response, or multiple channels responding).
0205 Improper OBII data from this channel after SMSK.
0206 Improper register D response after SMSK.
0207 Improper IPOll response (should have been clear).
0208 Received no CSRQ after issuing a SlOP.
0209 \Vrong channel is responding to SPOlL.
020A Improper CBS! data after SPOLL
0208 Improper register F data after SPOlL.
020C Improper CSRQ response after IIIOP (should have been zero).
0200 Improper SPOLl after IIIOP (should have been zero).
020E Improper 08SI response to SPOLL after IHOP
(should have pointed to device 7).
DEC 86
. _I'

Error Codes
PIC Test Section 3
This section tests the Btl-ill ~oniroiier chip Status Register (PIC Register n
Code Error
0301 Initialization error -bits 0 to 7 should be zero.
0302 Initialization error -bits 10, 13, and 14 slhluld he 7.cro
ami bits I I and 12 should be one.
0303 Hit 13 should be I, bit 14 should be zero when the IIP-IB
controller chip is addressed to talk, but not listen.
0304 Bits 13 and 14 should both be one when the liP-In controller
chip is addressed to talk and listen.
0305 Bit 14 should be one, bit 13 should be 7.cro when the 111'-18
controller chip is addresscd to listen, but not to talk.
0306 nits 13 and 14 should both be zero whcn the liP-In controller
chip is not addressed to talk or to listen.
PIC Test Section 4
This section tests the liP-III controller I.:hip Interrupt Register (PIC Register 2) and Interrupt Mask
Register (PIC Register 3).
Code Error
0401 Reg2, bit 0 should be set (an interrupt is pending).
0402 Reg 2, bits 9 and 13 should be clear
(no handshake abort and inbound FIFO empty).
0403 Reg2, bit 12 should be set (outbound FIFO room available).
0404 Reg 2, bit 14 should be set (outbound FIFO idle).
0405 Reg2, bit 8 should be clear (no status change).
0406 Reg 2, bit 0 should be clear (no interrupt pending).
0407 Reg 2, bit 8 should be set (status change occurred).
0408 Reg2. bit 9 should be clear (no handshake abort).
0409 Reg 2, bits 12 and 14 should be clear. nit I 3 should be set
(outbound FIFO
rOlll11 not available, l)utbllUlHI FIFO not idle,
and illh,llll11i FiFO not empiy. ._> FIFO Oits iii uprh'siCc
state).
040A Reg 2, bit 9 should be set (handshake abort).
0406 Reg2. bit 9 should be clear (no handshake abort).
DEC 86

Error Codes
PIC Test Section 5
This section tests PiC registers 4 and 5 by reading and writing data. Functions are not tested.
Code Error
0501 Register 4 fails to show data patterns SOOe.
0502 Register 5 fails to show data patterns SOOAA.
0503 Register 4 fails to show data patterns S0055.
0504 Register 5 fails to show data patterns S0055.
PIC Test Section 6
This section tests PIC register 6 (IIP-18 control register).
Code Error
0601 Register 6 fails to show patterns $802A for read/write test.
0602 Register 6 fails to show patterns $4054 for read/write test.
0603 Bits 12 and 14 of the liP-In controller chip interrupt
register (PIC register 2) should be set (outbound FIFO NOT
full and idle.
0604 Bits 12 and 14 of the liP-In controller chip interrupt
register (PIC register 2) should be clear (outbound 1-"1£70
NOT full and idle.
0605 Bit 15 of register 6 should be set (clear out bound FI£70) via
the liP-Ill controller chip interrupt register test. Bits 12
and 14 of the uP-In controller chip interrupt register
should be clear.
PIC Test Section 7
This section tests PIC register 7 {IIP-IB address).
Code Error
0701 Regisier 7 fails io show patterns $SOGA for read/write test.
0702 Register 7 fails to show patterns $4015 for read/write test.
0703 Bit 9 of Register 7 should be set (talk always) via the liP-In
controller chip status register (PIC register I) test.
Bits 13 or 14 of the IIP-IB controller chip register should
be off to indicate NOT a laik or a iisten.
0704 Bit 10 of register 7 should be set (listen always) via the
DEC 86
111)-11\ controller 'hip status register test. Bit 13 of the
HP-IB controller chip status register must be on to indicate
a talk always.

0705 Same as 0704 except bit 14 of the IIP-IB controller chip
stat us register must be off to indicate NOT a listen always.
0706 Same as 0704 except the IIP-IB controller chip status register
is again updated and bit 13 of the UP-In (;ontroller chip
status n:;gisler must be on to indicate NOT a listen always.
to indicate NOT a listen always.
PIC Test Section 8
Error Codes
TIllS section tests PIC register 8, 9 and 10 with read/write data only. Register H is tested for lower 8 bits
only. Register 9 and 10 (SA) are tested for all 16 bits.
Code
Error
0801 Register 8 fails to show da ta patterns SOOAA.
0802 Register 9 fails to show data patterns SAAAA.
0803 Register 10 fails to show data patterns SAAAA.
0804 Register 8 fails to show data patterns S0055.
0805 Register 9 fails to show data patterns S5555.
0806 Register 10 fails to show data patterns S5555.
PIC Test Section 9
This section tests DMA Write/Read/Abort from memory to PIC FIFO, and from PIC FIFO to memory.
Code Error
0901 CSRQ response & test via OBSI failed the DMA write to PIC.
0902 Data transferred to the PIC FIFO by the above transfer
(assuming the DMA write abort test passed) is incorrect.
0903 Bit 9 of the interrupt register (PIC reg 2) should be clear
(no handshake abort) the DMA write abort (PIC reg E) test.
0904 CSRQ response & test via OBSI failed the DMA write abort.
0905 Bit 5 of PIC register B should be set for the DMA write abort
termination test.
0906 Bit 6 of PIC register B should be set for the DMA write abort
termination test.
0907 CSRQ response & test via onsl failed the DMA read from PIC.
0908 Data reat! from PIC on J)MA read test dlffercnt than expected.
090A CSRQ response & test via onsl failed for the DMA read abort.
0908 Bit 5 of PIC register B should be set for the DMA read abort
termination test.
090e Bit 6 of PIC register B should be set for the DMA read abort
termination test.
090r Timeout. Waiting for CSRQ.
DEC 86
A-7

Error Codes
LANIC TEST ERROR CODES
LANIC Self test Subtest Codes
LANIC selftest subtest descriptions and c(l<ics are h!lited below:
Code Test
0001 Z80 instruction set
0002 EPROM checksum
0003 Station address PROM checksum
0004 Iligh byte la tch
0005 RAM data (background test)
0005 Byte RAM data (even addresses)
0006 Byte RAM data (odd addresses)
0007 Byte RAM address (in,rementing addresses)
0008 Byte RAM address (decrementing addresses)
0009 \Vord RAM address
OOOA \Vord/Byte address mapping
OOOB Z80 memory reference instructions
OOOC Values from reset MDIAG,SYSCON
0000 eTC data tcst
OOOE CTC mode 0 counting
OOOF CTC mode 2 counting
0010 eTC mode 4 counting
0011 Interrupt PAL (bit 4)
0012 Z80 interrupt
0013 Z80 non-maskable interrupt
0014 Master handshake disabled (MHSDIS)
0015 PAODR TO BADDR (low 15 bits)
0016 ZBANKL
0017 ZBANKH
0018 Preliminary FIFO (INREADY, ADVREAOY, OUTREADY)
00 19 FIFO data (HDATA 7)
001A FIFO data (ilEA 7,8)
001 B FIFO data (BOAT A 2:6)
OOtC FIFO data (BDATA 0,1,13:15)
0010 FIFO data (BDATA (8:12)
001 E FIFO data (BA 11: 15)
001F FIFO data (BA 6: I 0)
DEC 86

0020 FIFO data (SA 1: 5)
0021 R 14 configuration register
0022 OBII value; channel number not 0
0023 COMCON values from reset
0024 MAU power on/off
0025 R i 3 CR, CR fuii bit
0026 R 15 self test result register
0027 82586 interrupt
0028 81586 reset
0029 Register decode (PilUS register addressing)
002A 82586 LANIC RAM addressing
002B 82586 diagnose command
002C Level I chip lo\)pback
002D 82586 write to FIFOS
002£ MAU loopback on media
LANIC Self test Error. Codes
The system console will display ,)Ile of the following error codes if the LANIC test fails:
Code Error
0179 Failure while performing 82586 initiali1.ation for the
LANIC diagnostic.
017A The 82586 did not clear its command word prior to
interrupting.
o17B Self test result register (R 15) bit is bad.
o 17C Z 80 stack underflow during self test.
017D Unexpected Z80 non-maskable interrupt (NMI).
017£ Unexpected Z 80 interrupt.
017f LANIC was reset but selflest never started, or I.ED circuitry
failed. (This code is set in the LEDs by the hard reset
preceding every full selftest. ) In t his case, the selftest
may have a failure code or a random value.
Error Codes
DEC 86
A-9

Error Codes
CPU TEST ERROR CODES
The system console displays one of the following error codes if the epu test fails. The tests are run in the
same sequence as the test sections. Testing stops when the first failure is detected.
Test Section 1 - Bank register tests
a101 Pbank read/ A bank write failure
0102 Dbank read/Shank write failure
0103 Sbank read/Dbank write failure
0104 Abank read/Pbank write failure
Test Section 2 - Toe RAM tests
020 1 TOe RAM test not done (power fail)
0202 TOe RAM data failure
Test Section 3 - Toe count verification
0203 TOe not counting
Test Section 4 - MPE timer verification
0301 TOe not counting
Test Section 5 - Watchdog timer verification
050 1 Watchdog timer did not rollover
MEMORY TEST ERROR CODES
The system console displays one of the following error codes if the memory test fails. The tests are run in
the same sequence as the test sections. Testing stops when the first failure is detected.
Code
Error
0000 PFAR test failed (memory dead)
000 1 Memory size test failed
0002 Memory initialization test failed
0003 Memory address test failed
0004 Memory pattern test failed
0005 Parity test failed
DEe 86

Error Codes
POWER-ON SELFTEST LED INTERPRETA TION
Table A-I. Power-On SeUtest LED Interpretation
ACTIVITY
LED
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
ON
FAULT
LED
Flashing single
blink
Flashing
double
blink
Flashing triple
blink
Flashing triple
blink
OFF
LED
INTERPRET ATION
No Power.
Processor completely dead.
Executing selftest.
System in ba
ttery
back -up mode.
CPU or 0-2 Mb memory
failed.
llnsupported ATP
detected.
Console
ATP failed.
Fast/slow 51MB I/F
failed.
Console failed
to speed
sense.
Console failed to speed
sense.
Selftest execution
complete.
"H for help" prompt
displayed.
ACTION
TOTAKE
Check for AC. Measure
DC
supply output.
Replace processor.
Wait for self test
completion.
Wait for AC power
return.
Replace processor PCA.
Remove unsupported
ATP.
Replace A TP in slot I or
replace processor PCA.
Check cable connection
between console and ATP.
Check that console is in
REMOTE mode.
Console rnay be defective.
Attempt loopback
da lacomm test.
Replace A
TP.
DEC 86
A-II