IBASE Technology ET976 Guide

COM EXPRESS
CARRIER BOARD
DESIGN GUIDE
Version 1.0
(January 2022)

ii COM Express® Carrier Board Design Guide
Disclaimer
IBASE reserves the right to make changes and improvements to this document without prior notice. Every effort has
been made to ensure the information in the document is correct; however, IBASE does not guarantee this document
is error-free. IBASE assumes no liability for incidental or consequential damages arising from misapplication or
inability to use the information contained herein, nor for any infringements of rights of third parties, which may result
from its use.
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COM Express® Carrier Board Design Guide ii
i
TableofContents
Chapter 1 General Information ................................................................. 1
1.1ABOUT COM EXPRESS ........................................................................... 1
Chapter 2 COM Express Interfaces ............................................................... 2
2.1General Purpose PCIe Lanes .................................................................... 3
2.1.1Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors ......... 3
2.1.2Schematic Examples .............................................................................. 4
2.1.3PCI Express Routing Considerations ..................................................... 7
2.2PEG (PCI Express Graphics) ..................................................................... 8
2.2.1Reference Schematics ......................................................................... 10
2.3Digital Display Interfaces ......................................................................... 11
2.3.1DisplayPort / HDMI / DVI .................................................................... 11
2.3.1.1Reference Schematic ......................................................................... 12
2.3.1.2Routing Considerations ...................................................................... 17
2.3.2SDVO ................................................................................................. 18
2.3.2.1Signal Definitions ............................................................................... 18
2.3.2.2Reference Schematics ....................................................................... 18
2.3.2.3Routing Considerations ...................................................................... 18
2.4LAN .......................................................................................................... 19
2.4.1Signal Definitions ............................................................................... 19
2.4.2Reference Schematics ....................................................................... 20
2.4.3Routing Considerations ...................................................................... 20
2.5USB Ports ................................................................................................ 21
2.5.1Signal Definitions ............................................................................... 21
2.5.2Reference Schematics ....................................................................... 22
2.5.3Routing Considerations ...................................................................... 22
2.6USB 3.0 .................................................................................................... 23
2.6.1Signal Definitions ............................................................................... 23
2.6.2Reference Schematics ....................................................................... 24
2.6.3Routing Considerations ...................................................................... 26
2.7SATA ........................................................................................................ 27
2.7.1Signal Definitions ............................................................................... 27
2.7.2Reference Schematic ......................................................................... 28
2.7.3Routing Considerations ...................................................................... 28

iv COM Express® Carrier Board Design Guide
2.8LVDS ........................................................................................................ 29
2.8.1Signal Definitions ............................................................................... 29
2.8.2Reference Schematics ....................................................................... 30
2.8.3Routing Considerations ...................................................................... 32
2.9Embedded DisplayPort (eDP) .................................................................. 33
2.9.1Signal Definitions ..................................................................................... 33
2.9.2Reference Schematics ............................................................................. 34
2.9.3Routing Considerations ............................................................................ 35
2.10VGA ......................................................................................................... 36
2.10.1Signal Definitions ............................................................................... 36
2.10.2VGA Reference Schematics .............................................................. 37
2.10.3Routing Considerations ...................................................................... 39
2.10.3.1RGB Analog Signals .................................................................... 39
2.10.3.2HSYNC and VSYNC Signals ....................................................... 39
2.10.3.3DDC Interface .............................................................................. 39
2.11Digital Audio Interfaces ............................................................................ 40
2.11.1Reference Schematics ....................................................................... 41
2.11.1.1High Definition Audio .......................................................................... 41
2.11.2Routing Considerations ...................................................................... 43
2.12LPC Bus – Low Pin Count Interface ........................................................ 44
2.12.1Signal Definition ................................................................................. 44
2.12.2LPC Bus Reference Schematics ........................................................ 45
2.12.2.1Super I/O ...................................................................................... 45
2.12.3Routing Considerations ...................................................................... 47
2.12.3.1General Signals ............................................................................ 47
2.13Serial Peripheral Interface Bus ................................................................ 48
2.13.1Signal Definition ................................................................................. 48
2.13.2SPI Reference Schematics ................................................................ 49
2.13.3Routing Considerations ...................................................................... 49
2.14General Purpose I2C Bus Interface ......................................................... 50
2.14.1Signal Definitions ............................................................................... 50
2.14.2Reference Schematics ....................................................................... 50
2.14.3Connectivity Considerations ............................................................... 5 0 
2.15System Management Bus (SMBus) ......................................................... 51
2.15.1Signal Definitions ............................................................................... 52
2.15.2Routing Considerations ...................................................................... 52

COM Express® Carrier Board Design Guide
v

2.16General Purpose Serial Interface ............................................................. 53
2.16.1Signal Definitions ............................................................................... 53
2.16.2Reference Schematics ....................................................................... 54
2.16.2.1 General Purpose Serial Port Example ................................................ 54
2.16.3Routing Considerations ...................................................................... 56
2.17CAN Interface .......................................................................................... 56
2.17.1Signal Definitions ............................................................................... 56
2.17.2Reference Schematics ....................................................................... 57
2.17.3Routing Considerations ...................................................................... 58
2.18Miscellaneous Signals ............................................................................. 59
2.18.1Speaker Output .................................................................................. 60
2.18.2RTC Battery Implementation .............................................................. 61
2.18.3Power Management Signals .............................................................. 62
2.18.4Watchdog Timer ................................................................................. 65
2.18.5General Purpose Input/Output (GPIO) ............................................... 65
2.18.6Fan Connector ................................................................................... 66
2.18.7Thermal Interface ............................................................................... 67
2.19PCI Bus .................................................................................................... 68
2.19.1Signal Definitions ............................................................................... 68
2.19.2Reference Schematics ....................................................................... 70
2.20IDE and CompactFlash (PATA) ............................................................... 72
2.20.1Signal Definitions ............................................................................... 72
Chapter 3 Power and Reset .......................................................................... 74
3.1ATX Style Power Control ......................................................................... 75
Chapter 4 Carrier Board PCB Layout Guidelines ....................................... 78
4.1General .................................................................................................... 79
4.2PCB Stack-ups ......................................................................................... 79
4.3Trace Impedance Considerations ............................................................ 82
Chapter 5 Mechanical Considerations ........................................................ 83
5.1Form Factors ............................................................................................ 83
5.2Heatspreader ........................................................................................... 84
5.3COM Express Carrier Board .................................... 錯誤! 尚未定義書籤。
5.4COM Express Module and Heatsink ........................ 錯誤! 尚未定義書籤。

vi COM Express® Carrier Board Design Guide
5.5 COM Express Connector (Tyco) .............................. 錯誤! 尚未定義書籤。
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General Information
COM Express® Carrier Board Design Guide 1
1
Chapter 1
General Information
This design guide provides suggestions on designing IBASE COM-Express products
including carrier boards and systems. For other carrier board schematic guidelines
please refer to the full specification in the PICMG® COM Express® Carrier Board
Design Guide.
This design guide is not a specification and should not be your sole reference. The
guide is intended for electronics engineers and PCB layout engineers involved in the
design of the COM Express Modules Carrier Boards. The schematic examples in
this document are believed to be correct, however, no guarantee is given. The
examples shown here have been taken from the designs that were already tested.
For any questions that you may have in the design of carrier boards, please contact
IBASE sales representatives or engineers in your area.
1.1 ABOUT COM EXPRESS
COM Express is a highly integrated computer module that is integrated with the
CPU, memory and I/O functions including USB, audio, graphics and Ethernet, which
signals are mapped to two high-density, low-profile connectors at the bottom of the
module.
COM Express uses a mezzanine concept, with a module inserted onto customized
base boards. The module and base boards can be both upgraded to newer versions
and to earlier-designed compatible versions. Common applications for COM Express
modules are in various applications in the field of IoT, industrial automation, military,
gaming, medical and transportation.

2 COM Express® Carrier Board Design Guide
Chapter 2
COM Express Interfaces
The information provided in this chapter includes:
 General Purpose PCIe Lanes
 PEG (PCI Express Graphics)
 Digital Display Interfaces
 LAN
 USB Ports
 USB 3.0
 SATA
 LVDS
 Embedded DisplayPort (eDP)
 VGA
 Digital Audio Interfaces
 LPC Bus – Low Pin Count Interface
 Serial Peripheral Interface Bus
 General Purpose I2C Bus Interface
 System Management Bus (SMBus)
 General Purpose Serial Interface
 CAN Interface
 Miscellaneous Signals
 PCI Bus
 IDE and CompactFlash (PATA)

COM Express® Carrier Board Design Guide 3
2.1 General Purpose PCIe Lanes
2.1.1 Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors
Figure 1: PCIe Rx Coupling Capacitors
The coupling caps for the Module PCIe TX lines are to be on the Module, as indicated in the COM
Express specification.

4 COM Express® Carrier Board Design Guide
2.1.2 Schematic Examples
Figure 2: PCI Express x1 Slot Example

COM Express® Carrier Board Design Guide 5
Figure 3: PCI Express x4 Slot Example

6 COM Express® Carrier Board Design Guide
Figure 4: PCIe Mini Card Reference Circuitry

COM Express® Carrier Board Design Guide 7
2.1.3 PCI Express Routing Considerations
New Carrier designs route the PCIe lanes with 85Ω (+/- 15%) differential impedance. Past designs
for Gen1 and Gen2 signaling used 92Ω (+/- 10%) differential impedance. Gen1 designs used 100Ω
(+/- 20%) differential impedance. New designs use 85Ω (+/- 15%) differential impedance for Gen1,
Gen2 and Gen3 signaling. Route the traces as differential pairs, referenced to a continuous GND
plane with a minimum of via transitions. PCIe pairs must have length-matched within a given pair
(“intra-pair”). Different pairs do not need to be closely matched (“inter-pair”).

8 COM Express® Carrier Board Design Guide
2.2 PEG (PCI Express Graphics)
Table 1: PEG Signal Definitions
Signal Pin# Description I/O Remarks
PEG_RX0+
PEG_RX0-
C52
C53
PEG channel 0, Receive
Input differential pair.
I PCIE Type 2 SDVO_TVCLKIN+
Shared with: SDVO_TVCLKIN-
PEG_TX0+
PEG_TX0-
D52
D53
PEG channel 0, Transmit
Output differential pair.
O PCIE Type 2 SDVOB_RED+
Shared with: SDVOB_RED-
PEG_RX1+
PEG_RX1-
C55
C56
PEG channel 1, Receive
Input differential pair.
I PCIE Type 2 SDVOB_INT+
Shared with: SDVOB_INT-
PEG_TX1+
PEG_TX1-
D55
D56
PEG channel 1, Transmit
Output differential pair.
O PCIE Type 2 SDVOB_GRN+
Shared with: SDVOB_GRN-
PEG_RX2+
PEG_RX2-
C58
C59
PEG channel 2, Receive
Input differential pair.
I PCIE Type 2 SDVO_FLDSTALL+
Shared with: SDVO_FLDSTALL-
PEG_TX2+
PEG_TX2-
D58
D59
PEG channel 2, Transmit
Output differential pair.
O PCIE Type 2 SDVOB_BLU+
Shared with: SDVOB_BLU-
PEG_RX3+
PEG_RX3-
C61
C62
PEG channel 3, Receive
Input differential pair.
I PCIE
PEG_TX3+
PEG_TX3-
D61
D62
PEG channel 3, Transmit
Output differential pair.
O PCIE Type 2 SDVOB_CK+
Shared with: SDVOB_CK-
PEG_RX4+
PEG_RX4-
C65
C66
PEG channel 4, Receive
Input differential pair.
I PCIE
PEG_TX4+
PEG_TX4-
D65
D66
PEG channel 4, Transmit
Output differential pair.
O PCIE Type 2 SDVOC_RED+
Shared with: SDVOC_RED-
PEG_RX5+
PEG_RX5-
C68
C69
PEG channel 5, Receive
Input differential pair.
I PCIE Type 2 SDVOC_INT+
Shared with: SDVOC_INT-
PEG_TX5+
PEG_TX5-
D68
D69
PEG channel 5, Transmit
Output differential pair.
O PCIE Type 2 SDVOC_GRN+
Shared with: SDVOC_GRN-
PEG_RX6+
PEG_RX6-
C71
C72
PEG channel 6, Receive
Input differential pair.
I PCIE
PEG_TX6+
PEG_TX6-
D71
D72
PEG channel 6, Transmit
Output differential pair.
O PCIE Type 2 SDVOC_BLU+
Shared with SDVOC_BLU-
PEG_RX7+
PEG_RX7-
C74
C75
PEG channel 7, Receive
Input differential pair.
I PCIE
PEG_TX7+
PEG_TX7-
D74
D75
PEG channel 7, Transmit
Output differential pair.
O PCIE Type 2 SDVOC_CK+
Shared with SDVOC_CK-
PEG_RX8+
PEG_RX8-
C78
C79
PEG channel 8, Receive
Input differential pair.
I PCIE
PEG_TX8+
PEG_TX8-
D78
D79
PEG channel 8, Transmit
Output differential pair.
O PCIE
PEG_RX9+
PEG_RX9-
C81
C82
PEG channel 9, Receive
Input differential pair.
I PCIE
PEG_TX9+
PEG_TX9-
D81
D82
PEG channel 9,
Transmit Output
O PCIE
PEG_RX10+
PEG_RX10-
C85
C86
PEG channel 10,
Receive Input differential
I PCIE
PEG_TX10+
PEG_TX10-
D85
D86
PEG channel 10,
Transmit Output
O PCIE
PEG_RX11+
PEG_RX11-
C88
C89
PEG channel 11,
Receive Input differential
I PCIE
PEG_TX11+
PEG_TX11-
D88
D89
PEG channel 11,
Transmit Output
O PCIE

COM Express® Carrier Board Design Guide 9
Signal Pin# Description I/O Remarks
PEG_RX12+
PEG_RX12-
C91
C92
PEG channel 12, Receive
Input differential pair.
I PCIE
PEG_TX12+
PEG_TX12-
D91
D92
PEG channel 12, Transmit
Output differential pair.
O PCIE
PEG_RX13+
PEG_RX13-
C94
C95
PEG channel 13, Receive
Input differential pair.
I PCIE
PEG_TX13+
PEG_TX13-
D94
D95
PEG channel 13 Transmit
Output differential pair.
O PCIE
PEG_RX14+
PEG_RX14-
C98
C99
PEG channel 14, Receive
Input differential pair.
I PCIE
PEG_TX14+
PEG_TX14-
D98
D99
PEG channel 14, Transmit
Output differential pair.
O PCIE
PEG_RX15+
PEG_RX15-
C101
C102
PEG channel 15, Receive
Input differential pair.
I PCIE
PEG_TX15+
PEG_TX15-
D101
D102
PEG channel 15, Transmit
Output differential pair.
O PCIE
SDVO_I2C_CLK D73 I2C based control signal
(clock) for SDVO device.
O 2.5V
CMOS
SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only
)
SDVO_I2C_DATA C73 I2C based control signal
(data) for SDVO device
I/O 2.5V
OD CMOS
SDVO enabled if this line is pulled up to
2.5V on Carrier or on ADD2 (Type 2 only
)
PEG_LANE_RV# D54 PCI Express Graphics lane
reversal input strap. Pull
low on the carrier board to
reverse lane order.
I 3.3V
CMOS
PEG_ENABLE# D97 PEG enable function.
Strap to enable PCI
Express x16 external
graphics interface. Pull
low to disable internal
graphics and enable the
x16 interface.
I 3.3V
CMOS
Type 2 only
PCIE_CLK_REF+
PCIE_CLK_REF-
A88
A89
PCIe Reference Clock for
all COM Express PCIe
lanes, and for PEG lanes
O CMOS COM Express only allocates a
single reference clock

10 COM Express® Carrier Board Design Guide
2.2.1 Reference Schematics
Figure 5: x1, x4, x8, x16 Slot

COM Express® Carrier Board Design Guide 11
2.3 Digital Display Interfaces
Module Types 6 and 10 use Digital Display Interfaces (DDI) to provide DisplayPort, HDMI/DVI, and
SDVO interfaces. Type 10 Modules can contain a single DDI (DDI[0]) that can support DisplayPort,
HDMI/DVI, and SDVO. Type 6 Modules can contain up to 3 DDIs (DDI[1:3]) of which DDI[1:3] can
support DisplayPort, HDMI/DVI and DDI[1] can support DisplayPort, HDMI/DVI, and SDVO. The
main difference is that SDVO is only supported on DDI[0] for Type 10 Modules and DDI[1] for Type
6 Modules.
2.3.1 DisplayPort / HDMI / DVI
Type 10 offers up to one DisplayPort interface and Type 6 Modules up to 3 DisplayPort interfaces.
Both implementations are similar, so only one reference schematic is necessary to show Carrier
Board implementation.
Each DisplayPort interface consists of 4 differential lanes, 1 auxiliary lane and 1 hot-plug-detect
signal. The DDC_AUX_SEL pin should be routed to pin 13 of the DisplayPort connector, to enable
Dual-Mode. When HDMI/DVI is directly done on the Carrier Board, this pin shall be pulled to 3.3V
with a 100k Ohm resistor to configure the AUX pairs as DDC channels.
Table 2: Display Port / HDMI / DVI Pin-out of Type 10 and Type 6
COM Express
Pin Name
DDI0
Type 10
DDI1
Type 6
DDI2
Type 6
DDI3
Type 6
Function
(DDIX)
Function (DDIX)
HDMI / DVI
DDIX
_
P
A
IR0+ B71 D26 D39 C39 DPX
_
L
A
NE0+ TMDSX
_
D
A
T
A
2+
DDIX
_
P
A
IR0- B72 D27 D40 C40 DPX
_
L
A
NE0- TMDSX
_
D
A
T
A
2-
DDIX
_
P
A
IR1+ B73 D29 D42 C42 DPX
_
L
A
NE1+ TMDSX
_
D
A
T
A
1+
DDIX
_
P
A
IR1- B74 D30 D43 C43 DPX
_
L
A
NE1- TMDSX
_
D
A
T
A
1-
DDIX
_
P
A
IR2+ B75 D32 D46 C46 DPX
_
L
A
NE2+ TMDSX
_
D
A
T
A
0+
DDIX
_
P
A
IR2- B76 D33 D47 C47 DPX
_
L
A
NE2- TMDSX
_
D
A
T
A
0-
DDIX
_
P
A
IR3+ B81 D36 D49 C49 DPX
_
L
A
NE3+ TMDSX
_
CL
K
+
DDIX
_
P
A
IR3- B82 D37 D50 C50 DPX
_
L
A
NE3- TMDSX
_
CL
K
-
DDIX
_
HPD B89 C24 D44 C44 DPX
_
HPD HDMIX
_
HPD
DDIX
_
CTRLCL
K
_
A
UX B98 D15 C32 C36 DPX
_
A
UX+ HDMIX
_
CTRLCLK
DDIX
_
CTRLD
A
T
A
_
A
UB99 D16 C33 C37 DPX
_
A
UX- HDMIX
_
CTRLD
A
T
A
DDIX
_
DDC
_A
UX
_
SEL B95 D34 C34 C38

12 COM Express® Carrier Board Design Guide
2.3.1.1 Reference Schematic
Figure 6: DisplayPort Reference Schematics

COM Express® Carrier Board Design Guide 13
Figure 7: HDMI Example (1)

14 COM Express® Carrier Board Design Guide
Figure 7: HDMI Example (2)